clash-vhdl 0.5.6 → 0.5.7
raw patch · 20 files changed
+544/−201 lines, 20 filesdep ~clash-libdep ~clash-preludePVP ok
version bump matches the API change (PVP)
Dependency ranges changed: clash-lib, clash-prelude
API changes (from Hackage documentation)
Files
- CHANGELOG.md +8/−0
- clash-vhdl.cabal +7/−3
- primitives/CLaSH.Prelude.BlockRam.File.json +61/−0
- primitives/CLaSH.Prelude.BlockRam.json +33/−20
- primitives/CLaSH.Prelude.RAM.json +46/−0
- primitives/CLaSH.Prelude.ROM.File.json +88/−0
- primitives/CLaSH.Prelude.ROM.json +62/−0
- primitives/CLaSH.Prelude.Testbench.json +19/−11
- primitives/CLaSH.Signal.Internal.json +13/−4
- primitives/CLaSH.Sized.Internal.BitVector.json +66/−62
- primitives/CLaSH.Sized.Internal.Index.json +4/−10
- primitives/CLaSH.Sized.Internal.Signed.json +8/−4
- primitives/CLaSH.Sized.Internal.Unsigned.json +2/−8
- primitives/CLaSH.Sized.Vector.json +89/−67
- primitives/GHC.Base.json +4/−2
- primitives/GHC.CString.json +3/−3
- primitives/GHC.Classes.json +4/−2
- primitives/GHC.Integer.Type.json +4/−2
- primitives/GHC.Prim.json +18/−0
- src/CLaSH/Backend/VHDL.hs +5/−3
CHANGELOG.md view
@@ -1,5 +1,13 @@ # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package +## 0.5.7 *June 25 2015*+* New features:+ * Support `clash-prelude-0.9`++* Fixes bug:+ * Can not operate "shiftR" on Int [#63](https://github.com/clash-lang/clash-compiler/issues/63)+ * Fail to generate verilog when using "quot" and "div" on Index [#64](https://github.com/clash-lang/clash-compiler/issues/64)+ ## 0.5.6 *June 5th 2015* * Fixes bugs: * Incorrect extraction of `Bool` value out of a Sum-of-Product type
clash-vhdl.cabal view
@@ -1,5 +1,5 @@ Name: clash-vhdl-Version: 0.5.6+Version: 0.5.7 Synopsis: CAES Language for Synchronous Hardware - VHDL backend Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -29,6 +29,10 @@ primitives/CLaSH.Driver.TopWrapper.json primitives/CLaSH.GHC.GHC2Core.json primitives/CLaSH.Prelude.BlockRam.json+ primitives/CLaSH.Prelude.BlockRam.File.json+ primitives/CLaSH.Prelude.RAM.json+ primitives/CLaSH.Prelude.ROM.json+ primitives/CLaSH.Prelude.ROM.File.json primitives/CLaSH.Prelude.Testbench.json primitives/CLaSH.Promoted.Nat.json primitives/CLaSH.Promoted.Symbol.json@@ -66,8 +70,8 @@ CPP-Options: -DCABAL Build-depends: base >= 4.6.0.1 && < 5,- clash-lib >= 0.5.6,- clash-prelude >= 0.8,+ clash-lib >= 0.5.7,+ clash-prelude >= 0.9, fgl >= 5.4.2.4, lens >= 3.9.2, mtl >= 2.1.2,
+ primitives/CLaSH.Prelude.BlockRam.File.json view
@@ -0,0 +1,61 @@+[ { "BlackBox" :+ { "name" : "CLaSH.Prelude.BlockRam.File.blockRamFile#"+ , "type" :+"blockRamFile# :: KnownNat m -- ARG[0]+ => SClock clk -- clk, ARG[1]+ -> SNat n -- sz, ARG[2]+ -> FilePath -- file, ARG[3]+ -> Signal' clk Int -- wr, ARG[4]+ -> Signal' clk Int -- rd, ARG[5]+ -> Signal' clk Bool -- wren, ARG[6]+ -> Signal' clk (BitVector m) -- din, ARG[7]+ -> Signal' clk (BitVector m)"+ , "templateD" :+"-- blockRamFile begin+blockRamFile_~COMPNAME_~SYM[0] : block+ type RamType is array(0 to ~LIT[2]-1) of bit_vector(~LIT[0]-1 downto 0);++ impure function InitRamFromFile (RamFileName : in string) return RamType is+ FILE RamFile : text open read_mode is RamFileName;+ variable RamFileLine : line;+ variable RAM : RamType;+ begin+ for i in RamType'range loop+ readline(RamFile,RamFileLine);+ read(RamFileLine,RAM(i));+ end loop;+ return RAM;+ end function;++ signal RAM : RamType := InitRamFromFile(~FILE[~LIT[3]]);+ signal dout : ~TYP[7];+ signal wr : integer range 0 to ~LIT[2]-1;+ signal rd : integer range 0 to ~LIT[2]-1;+begin+ wr <= ~ARG[4]+ -- pragma translate_off+ mod ~LIT[2]+ -- pragma translate_on+ ;++ rd <= ~ARG[5]+ -- pragma translate_off+ mod ~LIT[2]+ -- pragma translate_on+ ;++ blockRamFile_~SYM[1] : process(~CLK[1])+ begin+ if (rising_edge(~CLK[1])) then+ if ~ARG[6] then+ RAM(to_integer(wr)) <= to_bitvector(~ARG[7]);+ end if;++ ~RESULT <= to_stdlogicvector(RAM(rd));+ end if;+ end process;+end block;+-- blockRamFile end"+ }+ }+]
primitives/CLaSH.Prelude.BlockRam.json view
@@ -1,34 +1,47 @@ [ { "BlackBox" :- { "name" : "CLaSH.Prelude.BlockRam.blockRam'"+ { "name" : "CLaSH.Prelude.BlockRam.blockRam#" , "type" :-"blockRam' :: (KnownNat n, KnownNat m) -- (ARG[0],ARG[1])- => SClock clk -- clk, ARG[2]- -> Vec n a -- init, ARG[3]- -> Signal' clk (Unsigned m) -- wr, ARG[4]- -> Signal' clk (Unsigned m) -- rd, ARG[5]- -> Signal' clk Bool -- wren, ARG[6]- -> Signal' clk a -- din, ARG[7]+"blockRam# :: KnownNat n -- ARG[0]+ => SClock clk -- clk, ARG[1]+ -> Vec n a -- init, ARG[2]+ -> Signal' clk Int -- wr, ARG[3]+ -> Signal' clk Int -- rd, ARG[4]+ -> Signal' clk Bool -- wren, ARG[5]+ -> Signal' clk a -- din, ARG[6] -> Signal' clk a" , "templateD" :-"blockRam_~COMPNAME_~SYM[0] : block- signal ~SYM[1] : ~TYP[3] := ~LIT[3]; -- ram- signal ~SYM[2] : ~TYP[7]; -- inp- signal ~SYM[3] : ~TYP[7]; -- outp+"-- blockRam begin+blockRam_~COMPNAME_~SYM[0] : block+ signal RAM : ~TYP[2] := ~LIT[2];+ signal dout : ~TYP[6];+ signal wr : integer range 0 to ~LIT[0] - 1;+ signal rd : integer range 0 to ~LIT[0] - 1; begin- ~SYM[2] <= ~ARG[7];+ wr <= ~ARG[3]+ -- pragma translate_off+ mod ~LIT[0]+ -- pragma translate_on+ ; - process(~CLK[2])+ rd <= ~ARG[4]+ -- pragma translate_off+ mod ~LIT[0]+ -- pragma translate_on+ ;++ blockRam_~SYM[1] : process(~CLK[1]) begin- if rising_edge(~CLK[2]) then- if ~ARG[6] then- ~SYM[1](to_integer(~ARG[4])) <= ~SYM[2];+ if rising_edge(~CLK[1]) then+ if ~ARG[5] then+ RAM(wr) <= ~ARG[6]; end if;- ~SYM[3] <= ~SYM[1](to_integer(~ARG[5]));+ dout <= RAM(rd); end if; end process; - ~RESULT <= ~SYM[3];-end block;"+ ~RESULT <= dout;+end block;+-- blockRam end" } } ]
+ primitives/CLaSH.Prelude.RAM.json view
@@ -0,0 +1,46 @@+[ { "BlackBox" :+ { "name" : "CLaSH.Prelude.RAM.asyncRam#"+ , "type" :+"asyncRam# :: SClock wclk -- ^ wclk, ARG[0]+ -> SClock rclk -- ^ rclk, ARG[1]+ -> SNat n -- ^ sz, ARG[2]+ -> Signal' wclk Int -- ^ wr, ARG[3]+ -> Signal' rclk Int -- ^ rd, ARG[4]+ -> Signal' wclk Bool -- ^ en, ARG[5]+ -> Signal' wclk a -- ^ din, ARG[6]+ -> Signal' rclk a"+ , "templateD" :+"-- asyncRam begin+asyncRam_~COMPNAME_~SYM[0] : block+ type RamType is array(0 to ~LIT[2]-1) of ~TYP[6];+ signal RAM : RamType;+ signal wr : integer range 0 to ~LIT[2] - 1;+ signal rd : integer range 0 to ~LIT[2] - 1;+begin+ wr <= ~ARG[3]+ -- pragma translate_off+ mod ~LIT[2]+ -- pragma translate_on+ ;++ rd <= ~ARG[4]+ -- pragma translate_off+ mod ~LIT[2]+ -- pragma translate_on+ ;++ asyncRam_~SYM[1] : process(~CLK[0])+ begin+ if rising_edge(~CLK[0]) then+ if ~ARG[5] then+ RAM(wr) <= ~ARG[6];+ end if;+ end if;+ end process;++ ~RESULT <= RAM(rd);+end block;+-- asyncRam end"+ }+ }+]
+ primitives/CLaSH.Prelude.ROM.File.json view
@@ -0,0 +1,88 @@+[ { "BlackBox" :+ { "name" : "CLaSH.Prelude.ROM.File.asyncRomFile#"+ , "type" :+"asyncRomFile# :: KnownNat m -- ARG[0]+ => SNat n -- sz, ARG[1]+ -> FilePath -- file, ARG[2]+ -> Int -- rd, ARG[3]+ -> BitVector m"+ , "templateD" :+"-- asyncRomFile begin+asyncROMFile_~SYM[0] : block+ type RomType is array(0 to ~LIT[1]-1) of bit_vector(~LIT[0]-1 downto 0);++ impure function InitRomFromFile (RomFileName : in string) return RomType is+ FILE RomFile : text open read_mode is RomFileName;+ variable RomFileLine : line;+ variable ROM : RomType;+ begin+ for i in RomType'range loop+ readline(RomFile,RomFileLine);+ read(RomFileLine,ROM(i));+ end loop;+ return ROM;+ end function;++ signal ROM : RomType := InitRomFromFile(~FILE[~LIT[2]]);+ signal rd : integer range 0 to ~LIT[1]-1;+begin+ rd <= ~ARG[3]+ -- pragma translate_off+ mod ~LIT[1]+ -- pragma translate_on+ ;++ ~RESULT <= to_stdlogicvector(ROM(rd));+end block;+-- asyncRomFile end"+ }+ }+, { "BlackBox" :+ { "name" : "CLaSH.Prelude.ROM.File.romFile#"+ , "type" :+"romFile# :: KnownNat m -- ARG[0]+ => SClock clk -- clk, ARG[1]+ -> SNat n -- sz, ARG[2]+ -> FilePath -- file, ARG[3]+ -> Signal' clk Int -- rd, ARG[4]+ -> Signal' clk (BitVector m)"+ , "templateD" :+"-- romFile begin+romFile_~COMPNAME_~SYM[0] : block+ type RomType is array(0 to ~LIT[2]-1) of bit_vector(~LIT[0]-1 downto 0);++ impure function InitRomFromFile (RomFileName : in string) return RomType is+ FILE RomFile : text open read_mode is RomFileName;+ variable RomFileLine : line;+ variable ROM : RomType;+ begin+ for i in RomType'range loop+ readline(RomFile,RomFileLine);+ read(RomFileLine,ROM(i));+ end loop;+ return ROM;+ end function;++ signal ROM : RomType := InitRomFromFile(~FILE[~LIT[3]]);+ signal rd : integer range 0 to ~LIT[2]-1;+ signal dout : ~TYPO;+begin+ rd <= ~ARG[4]+ -- pragma translate_off+ mod ~LIT[2]+ -- pragma translate_on+ ;++ romFile_~SYM[1] : process (~CLK[1])+ begin+ if (rising_edge(~CLK[1])) then+ dout <= to_stdlogicvector(ROM(rd));+ end if;+ end process;++ ~RESULT <= dout;+end block;+-- romFile end"+ }+ }+]
+ primitives/CLaSH.Prelude.ROM.json view
@@ -0,0 +1,62 @@+[ { "BlackBox" :+ { "name" : "CLaSH.Prelude.ROM.asyncRom#"+ , "type" :+"asyncRom# :: KnownNat n -- ^ ARG[0]+ => Vec n a -- ^ ARG[1]+ -> Int -- ^ ARG[2]+ -> a"+ , "templateD" :+"-- asyncRom begin+asyncRom_~SYM[0] : block+ signal ROM : ~TYP[1];+ signal rom_index : integer range 0 to ~LIT[0]-1;+begin+ ROM <= ARG[1];++ rom_index <= ~ARG[2]+ -- pragma translate_off+ mod ~LIT[0]+ -- pragma translate_on+ ;++ ~RESULT <= ROM(rom_index);+end block;+-- asyncRom end"+ }+ }+, { "BlackBox" :+ { "name" : "CLaSH.Prelude.ROM.rom#"+ , "type" :+"rom# :: KnownNat n -- ARG[0]+ => SClock clk -- clk, ARG[1]+ -> Vec n a -- init, ARG[2]+ -> Signal' clk Int -- rd, ARG[3]+ -> Signal' clk a"+ , "templateD" :+"-- rom begin+rom_~COMPNAME_~SYM[0] : block+ signal ROM : ~TYP[2];+ signal rd : integer range 0 to ~LIT[0]-1;+ signal dout : ~TYPO;+begin+ ROM <= ~ARG[2];++ rd <= ~ARG[3]+ -- pragma translate_off+ mod ~LIT[0]+ -- pragma translate_on+ ;++ rom : process (~CLK[1])+ begin+ if (rising_edge(~CLK[1])) then+ dout <= ROM(rd);+ end if;+ end process;++ ~RESULT <= dout;+end block;+-- rom end"+ }+ }+]
primitives/CLaSH.Prelude.Testbench.json view
@@ -1,13 +1,16 @@ [ { "BlackBox" :- { "name" : "CLaSH.Prelude.Testbench.assert"+ { "name" : "CLaSH.Prelude.Testbench.assert'" , "type" :-"assert :: (Eq a,Show a) -- (ARG[0],ARG[1])- => Signal' t a -- ^ Checked value (ARG[2])- -> Signal' t a -- ^ Expected value (ARG[3])- -> Signal' t b -- ^ Return valued (ARG[4])- -> Signal' t b"+"assert' :: (Eq a,Show a) -- (ARG[0],ARG[1])+ => SClock t -- ^ ARG[2]+ -> String -- ^ ARG[3]+ -> Signal' t a -- ^ Checked value (ARG[4])+ -> Signal' t a -- ^ Expected value (ARG[5])+ -> Signal' t b -- ^ Return valued (ARG[6])+ -> Signal' t b" , "templateD" :-"assert_~SYM[0] : block+"-- assert begin+assert_~SYM[0] : block -- pragma translate_off function slv2string (slv : std_logic_vector) return STRING is variable result : string (1 to slv'length);@@ -22,18 +25,23 @@ end loop; return result; end;+ signal actual : ~TYP[4];+ signal expected : ~TYP[5]; -- pragma translate_on begin -- pragma translate_off- process(~CLK[2],~RST[2],~ARG[2],~ARG[3]) is+ actual <= ~ARG[4];+ expected <= ~ARG[5];+ process(~CLK[2],~RST[2]) is begin if (rising_edge(~CLK[2]) or rising_edge(~RST[2])) then- assert (~ARG[2] = ~ARG[3]) report (\"expected: \" & slv2string(toSLV(~ARG[3])) & \", actual: \" & slv2string(toSLV(~ARG[2]))) severity error;+ assert (actual = expected) report (~LIT[3] & \", expected: \" & slv2string(toSLV(expected)) & \", actual: \" & slv2string(toSLV(actual))) severity error; end if; end process; -- pragma translate_on- ~RESULT <= ~ARG[4];-end block;"+ ~RESULT <= ~ARG[6];+end block;+-- assert end" } } ]
primitives/CLaSH.Signal.Internal.json view
@@ -6,7 +6,8 @@ -> Signal' clk a -- ARG[2] -> Signal' clk a" , "templateD" :-"register_~COMPNAME_~SYM[0] : block+"-- register begin+register_~COMPNAME_~SYM[0] : block signal ~SYM[1] : ~TYP[1]; signal ~SYM[2] : ~TYP[2]; begin@@ -22,7 +23,8 @@ end process; ~RESULT <= ~SYM[2];-end block;"+end block;+-- register end" } } , { "BlackBox" :@@ -34,7 +36,8 @@ -> Signal' clk a -- ARG[3] -> Signal' clk a" , "templateD" :-"regEn_~COMPNAME_~SYM[0] : block+"-- regEn begin+regEn_~COMPNAME_~SYM[0] : block signal ~SYM[1] : ~TYP[1]; signal ~SYM[2] : ~TYP[2]; signal ~SYM[3] : ~TYP[3];@@ -54,7 +57,8 @@ end process; ~RESULT <= ~SYM[3];-end block;"+end block;+-- regEn end" } } @@ -80,6 +84,11 @@ } , { "Primitive" : { "name" : "CLaSH.Signal.Internal.traverse#"+ , "primType" : "Function"+ }+ }+, { "Primitive" :+ { "name" : "CLaSH.Signal.Internal.joinSignal#" , "primType" : "Function" } }
primitives/CLaSH.Sized.Internal.BitVector.json view
@@ -32,7 +32,8 @@ { "name" : "CLaSH.Sized.Internal.BitVector.reduceAnd#" , "type" : "reduceAnd# :: KnownNat n => BitVector n -> BitVector 1" , "templateD" :-"reduceAnd_~SYM[0] : block+"-- reduceAnd begin+reduceAnd_~SYM[0] : block function and_reduce (arg : std_logic_vector) return std_logic is variable upper, lower : std_logic; variable half : integer;@@ -56,14 +57,16 @@ end; begin ~RESULT <= (0 => and_reduce(~ARG[1]));-end block;"+end block;+-- reduceAnd end" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Internal.BitVector.reduceOr#" , "type" : "reduceOr# :: BitVector n -> BitVector 1" , "templateD" :-"reduceOr_~SYM[0] : block+"-- reduceOr begin+reduceOr_~SYM[0] : block function or_reduce (arg : std_logic_vector) return std_logic is variable upper, lower : std_logic; variable half : integer;@@ -87,14 +90,16 @@ end; begin ~RESULT <= (0 => or_reduce(~ARG[0]));-end block;"+end block;+-- reduceOr end" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Internal.BitVector.reduceXor#" , "type" : "reduceXor# :: BitVector n -> BitVector 1" , "templateD" :-"reduceXor_~SYM[0] : block+"-- reduceXor begin+reduceXor_~SYM[0] : block function xor_reduce (arg : std_logic_vector) return std_logic is variable upper, lower : std_logic; variable half : integer;@@ -118,7 +123,8 @@ end; begin ~RESULT <= (0 => xor_reduce(~ARG[0]));-end block;"+end block;+-- reduceXor end" } } , { "BlackBox" :@@ -129,26 +135,22 @@ -> Int -- ARG[2] -> Bit" , "templateD" :-"indexBit_~SYM[0] : block- signal ~SYM[1] : ~TYP[1];- signal ~SYM[2] : ~TYP[2];+"-- indexBitVector begin+indexBitVector_~SYM[0] : block+ signal vec : ~TYP[1];+ signal vec_index : integer range 0 to ~LIT[0]-1; begin- ~SYM[1] <= ~ARG[1];- ~SYM[2] <= ~ARG[2];+ vec <= ~ARG[1];++ vec_index <= ~ARG[2] -- pragma translate_off- process (~SYM[1],~SYM[2])- begin- if ~SYM[2] < ~SYM[1]'low or ~SYM[2] > ~SYM[1]'high then- assert false report (\"Index: \" & integer'image(~SYM[2]) & \", is out of bounds: \" & integer'image(~SYM[1]'low) & \" downto \" & integer'image(~SYM[1]'high)) severity warning;- ~RESULT <= ~ERRORO;- else- -- pragma translate_on- ~RESULT <= ~SYM[1](~SYM[2] downto ~SYM[2]);- -- pragma translate_off- end if;- end process;+ mod ~LIT[0] -- pragma translate_on-end block;"+ ;++ ~RESULT <= vec(vec_index downto vec_index);+end block;+-- indexBitVector end" } } , { "BlackBox" :@@ -160,31 +162,29 @@ -> Bit -- ARG[3] -> BitVector n" , "templateD" :-"replaceBit_~SYM[0] : block- signal ~SYM[1] : ~TYP[1];- signal ~SYM[2] : ~TYP[2];- signal ~SYM[3] : ~TYP[3];+"-- replaceBit begin+replaceBit_~SYM[0] : block+ signal vec : ~TYP[1];+ signal vec_index : integer range 0 to ~LIT[0]-1;+ signal din : ~TYP[3]; begin- ~SYM[1] <= ~ARG[1];- ~SYM[2] <= ~ARG[2];- ~SYM[3] <= ~ARG[3];- process(~SYM[1],~SYM[2],~SYM[3])- variable ~SYM[4] : ~TYP[1];+ vec <= ~ARG[1];+ vec_index <= ~ARG[2]+ -- pragma translate_off+ mod ~LIT[0]+ -- pragma translate_on+ ;+ din <= ~ARG[3];++ process(vec,vec_index,din)+ variable ivec : ~TYP[1]; begin- ~SYM[4] := ~SYM[1];- -- pragma translate_off- if ~SYM[2] < ~SYM[4]'low or ~SYM[2] > ~SYM[4]'high then- assert false report (\"Index: \" & integer'image(~SYM[2]) & \", is out of bounds: \" & integer'image(~SYM[1]'low) & \" downto \" & integer'image(~SYM[1]'high)) severity warning;- ~SYM[4] := ~ERROR[1];- else- -- pragma translate_on- ~SYM[4](~SYM[2] downto ~SYM[2]) := ~SYM[3];- -- pragma translate_off- end if;- -- pragma translate_on- ~RESULT <= ~SYM[4];+ ivec := vec;+ ivec(vec_index downto vec_index) := din;+ ~RESULT <= ivec; end process;-end block;"+end block;+-- replaceBit end" } } , { "BlackBox" :@@ -196,7 +196,8 @@ -> BitVector (m + 1 - n) -- ARG[3] -> BitVector (m + 1 + i)" , "templateD" :-"setSlice_~SYM[0] : block+"-- setSlice begin+setSlice_~SYM[0] : block signal ~SYM[1] : ~TYP[0]; signal ~SYM[2] : ~TYP[3]; begin@@ -209,7 +210,8 @@ ~SYM[3](~LIT[1] downto ~LIT[2]) := ~SYM[2]; ~RESULT <= ~SYM[3]; end process;-end block;"+end block;+-- setSlice end" } } , { "BlackBox" :@@ -220,12 +222,14 @@ -> SNat n -- ARG[2] -> BitVector (m + 1 - n)" , "templateD" :-"slice_~SYM[0] : block+"-- slice begin+slice_~SYM[0] : block signal ~SYM[1] : ~TYP[0]; begin ~SYM[1] <= ~ARG[0]; ~RESULT <= ~SYM[1](~LIT[1] downto ~LIT[2]);-end block;"+end block;+-- slice end" } } , { "BlackBox" :@@ -235,7 +239,8 @@ => BitVector (m + n) -- ARG[1] -> (BitVector m, BitVector n)" , "templateD" :-"split_~SYM[0]: block+"-- split begin+split_~SYM[0]: block signal ~SYM[1] : ~TYP[1]; begin ~SYM[1] <= ~ARG[1];@@ -243,7 +248,8 @@ ~RESULT.~TYPMO_sel0'right + ~RESULT.~TYPMO_sel1'length) , ~SYM[1](~RESULT.~TYPMO_sel1'left downto ~RESULT.~TYPMO_sel1'right) );-end block;"+end block;+-- split end" } } , { "BlackBox" :@@ -253,7 +259,8 @@ => BitVector n -- ARG[1] -> Bit" , "templateD" :-"msb_~SYM[0] : block+"-- msb begin+msb_~SYM[0] : block signal ~SYM[1] : ~TYP[1]; begin ~SYM[2]_generate : if ~SYM[1]'length = 0 generate@@ -265,7 +272,8 @@ ~SYM[1] <= ~ARG[1]; ~RESULT <= ~SYM[1](~SYM[1]'high downto ~SYM[1]'high); end generate;-end block;"+end block;+-- msb end" } } , { "BlackBox" :@@ -274,7 +282,8 @@ "lsb# :: BitVector n -- ARG[0] -> Bit" , "templateD" :-"lsb_~SYM[0] : block+"-- lsb begin+lsb_~SYM[0] : block signal ~SYM[1] : ~TYP[0]; begin ~SYM[2]_generate : if ~SYM[1]'length = 0 generate@@ -287,7 +296,8 @@ ~SYM[1] <= ~ARG[0]; ~RESULT <= ~SYM[1](0 downto 0); end generate;-end block;"+end block;+-- lsb end" } } , { "BlackBox" :@@ -397,13 +407,7 @@ , { "BlackBox" : { "name" : "CLaSH.Sized.Internal.BitVector.rem#" , "type" : "rem# :: BitVector n -> BitVector n -> BitVector n"- , "templateE" : "~ARG[1] rem ~ARG[2]"- }- }-, { "BlackBox" :- { "name" : "CLaSH.Sized.Internal.BitVector.mod#"- , "type" : "mod# :: BitVector n -> BitVector n -> BitVector n"- , "templateE" : "~ARG[1] mod ~ARG[2]"+ , "templateE" : "std_logic_vector(unsigned(~ARG[1]) rem unsigned(~ARG[2]))" } } , { "BlackBox" :
primitives/CLaSH.Sized.Internal.Index.json view
@@ -66,20 +66,14 @@ } , { "BlackBox" : { "name" : "CLaSH.Sized.Internal.Index.quot#"- , "type" : "quot# :: KnownNat n => Index n -> Index n -> Index n"- , "templateE" : "~ARG[1] / ~ARG[2]"+ , "type" : "quot# :: Index n -> Index n -> Index n"+ , "templateE" : "~ARG[0] / ~ARG[1]" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Internal.Index.rem#"- , "type" : "rem# :: KnownNat n => Index n -> Index n -> Index n"- , "templateE" : "~ARG[1] rem ~ARG[2]"- }- }-, { "BlackBox" :- { "name" : "CLaSH.Sized.Internal.Index.mod#"- , "type" : "mod# :: KnownNat n => Index n -> Index n -> Index n"- , "templateE" : "~ARG[1] mod ~ARG[2]"+ , "type" : "rem# :: Index n -> Index n -> Index n"+ , "templateE" : "~ARG[0] rem ~ARG[1]" } } , { "BlackBox" :
primitives/CLaSH.Sized.Internal.Signed.json view
@@ -138,7 +138,8 @@ { "name" : "CLaSH.Sized.Internal.Signed.div#" , "type" : "div# :: KnownNat n => Signed n -> Signed n -> Signed n" , "templateD" :-"divSigned_~SYM[0] : block+"-- divSigned begin+divSigned_~SYM[0] : block signal ~SYM[1] : ~TYP[1]; signal ~SYM[2] : ~TYP[2]; signal ~SYM[3] : ~TYP[1];@@ -148,7 +149,8 @@ ~SYM[3] <= ~SYM[1] / ~SYM[2]; ~RESULT <= ~SYM[3] - to_signed(1,~LIT[0]) when ~SYM[1](~SYM[1]'high) = not (~SYM[2](~SYM[2]'high)) else ~SYM[3];-end block;"+end block;+-- divSigned end" } } , { "BlackBox" :@@ -221,12 +223,14 @@ { "name" : "CLaSH.Sized.Internal.Signed.truncateB#" , "type" : "truncateB# :: KnownNat m => Signed (n + m) -> Signed m" , "templateD" :-"truncateB_~SYM[0] : block+"-- truncateB begin+truncateB_~SYM[0] : block signal ~SYM[1] : ~TYP[1]; begin ~SYM[1] <= ~ARG[1]; ~RESULT <= ~SYM[1](~LIT[0]-1 downto 0);-end block;"+end block;+-- truncateB end" } } ]
primitives/CLaSH.Sized.Internal.Unsigned.json view
@@ -117,19 +117,13 @@ , { "BlackBox" : { "name" : "CLaSH.Sized.Internal.Unsigned.quot#" , "type" : "quot# :: Unsigned n -> Unsigned n -> Unsigned n"- , "templateE" : "~ARG[1] / ~ARG[2]"+ , "templateE" : "~ARG[0] / ~ARG[1]" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Internal.Unsigned.rem#" , "type" : "rem# :: Unsigned n -> Unsigned n -> Unsigned n"- , "templateE" : "~ARG[1] rem ~ARG[2]"- }- }-, { "BlackBox" :- { "name" : "CLaSH.Sized.Internal.Unsigned.mod#"- , "type" : "mod# :: Unsigned n -> Unsigned n -> Unsigned n"- , "templateE" : "~ARG[1] mod ~ARG[2]"+ , "templateE" : "~ARG[0] rem ~ARG[1]" } } , { "BlackBox" :
primitives/CLaSH.Sized.Vector.json view
@@ -14,48 +14,56 @@ { "name" : "CLaSH.Sized.Vector.head" , "type" : "head :: Vec (n + 1) a -> a" , "templateD" :-"head_~SYM[0] : block+"-- head begin+head_~SYM[0] : block signal ~SYM[1] : ~TYP[0]; begin ~SYM[1] <= ~ARG[0]; ~RESULT <= ~SYM[1](0);-end block;"+end block;+-- head end" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Vector.tail" , "type" : "tail :: Vec (n + 1) a -> Vec n a" , "templateD" :-"tail_~SYM[0] : block+"-- tail begin+tail_~SYM[0] : block signal ~SYM[1] : ~TYP[0]; begin ~SYM[1] <= ~ARG[0]; ~RESULT <= ~SYM[1](1 to ~SYM[1]'high);-end block;"+end block;+-- tail end" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Vector.last" , "type" : "Vec (n + 1) a -> a" , "templateD" :-"last_~SYM[0] : block+"-- last begin+last_~SYM[0] : block signal ~SYM[1] : ~TYP[0]; begin ~SYM[1] <= ~ARG[0]; ~RESULT <= ~SYM[1](~SYM[1]'high);-end block;"+end block;+-- last end" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Vector.init" , "type" : "Vec (n + 1) a -> Vec n a" , "templateD" :-"init_~SYM[0] : block+"-- init begin+init_~SYM[0] : block signal ~SYM[1] : ~TYP[0]; begin ~SYM[1] <= ~ARG[0]; ~RESULT <= ~SYM[1](0 to ~SYM[1]'high - 1);-end block;"+end block;+-- init end" } } , { "BlackBox" :@@ -68,7 +76,8 @@ -> Vec i a -- ARG[4] -> Vec n a" , "templateD" :-"select_~SYM[0] : block+"-- select begin+select_~SYM[0] : block signal ~SYM[1] : ~TYP[4]; begin ~SYM[1] <= ~ARG[4];@@ -83,7 +92,8 @@ ~RESULT(~SYM[5]) <= ~SYM[1](~LIT[1]+(~LIT[2]*~SYM[5])); end generate; end generate;-end block;"+end block;+-- select end" } } , { "BlackBox" :@@ -96,7 +106,8 @@ { "name" : "CLaSH.Sized.Vector.concat" , "type" : "concat :: Vec n (Vec m a) -> Vec (n * m) a" , "templateD" :-"concat_~SYM[0] : block+"-- concat begin+concat_~SYM[0] : block signal ~SYM[1] : ~TYP[0]; begin ~SYM[1] <= ~ARG[0];@@ -111,20 +122,23 @@ ~RESULT((~SYM[5] * ~SYM[1](0)'length) to ((~SYM[5] * ~SYM[1](0)'length) + ~SYM[1](0)'high)) <= ~SYM[1](~SYM[5]); end generate; end generate;-end block;"+end block;+-- concat end" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Vector.splitAt" , "type" : "splitAt :: SNat m -> Vec (m + n) a -> (Vec m a, Vec n a)" , "templateD" :-"splitAt_~SYM[0] : block+"-- sliptAt begin+splitAt_~SYM[0] : block signal ~SYM[1] : ~TYP[1]; begin ~SYM[1] <= ~ARG[1]; ~RESULT <= (~SYM[1](~RESULT.~TYPMO_sel0'left to ~RESULT.~TYPMO_sel0'right) ,~SYM[1](~RESULT.~TYPMO_sel1'left + ~RESULT.~TYPMO_sel0'length to ~RESULT.~TYPMO_sel1'right + ~RESULT.~TYPMO_sel0'length));-end block;"+end block;+-- splitAt end" } } , { "BlackBox" :@@ -135,7 +149,8 @@ -> Vec (n * m) a -- ARG[2] -> Vec n (Vec m a)" , "templateD" :-"unconcat_~SYM[0] : block+"-- unconcat begin+unconcat_~SYM[0] : block signal ~SYM[1] : ~TYP[2]; begin ~SYM[1] <= ~ARG[2];@@ -150,14 +165,16 @@ ~RESULT(~SYM[5]) <= ~SYM[1]((~SYM[5] * ~LIT[1]) to ((~SYM[5] * ~LIT[1]) + ~LIT[1] - 1)); end generate; end generate;-end block;"+end block;+-- unconcat end" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Vector.merge" , "type" : "merge :: Vec n a -> Vec n a -> Vec (n + n) a" , "templateD" :-"merge_~SYM[0] : block+"-- merge begin+merge_~SYM[0] : block signal ~SYM[1] : ~TYP[0]; signal ~SYM[2] : ~TYP[1]; begin@@ -175,14 +192,16 @@ ~RESULT(2*~SYM[6]+1) <= ~SYM[2](~SYM[6]); end generate; end generate;-end block;"+end block;+-- merge end" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Vector.map" , "type" : "map :: (a -> b) -> Vec n a -> Vec n b" , "templateD" :-"map_~SYM[0] : block+"-- map begin+map_~SYM[0] : block signal ~SYM[1] : ~TYP[1]; begin ~SYM[1] <= ~ARG[1];@@ -200,14 +219,16 @@ ~INST end generate; end generate;-end block;"+end block;+-- map end" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Vector.zipWith" , "type" : "zipWith :: (a -> b -> c) -> Vec n a -> Vec n b -> Vec n c" , "templateD" :-"zipWith_~SYM[0] : block+"-- zipWith begin+zipWith_~SYM[0] : block signal ~SYM[1] : ~TYP[1]; signal ~SYM[2] : ~TYP[2]; begin@@ -228,64 +249,59 @@ ~INST end generate; end generate;-end block;"+end block;+-- zipWith end" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Vector.index_int" , "type" : "index_int :: KnownNat n => Vec n a -> Int -> a" , "templateD" :-"indexVec_~SYM[0] : block- signal ~SYM[1] : ~TYP[1];- signal ~SYM[2] : ~TYP[2];+"-- index begin+indexVec_~SYM[0] : block+ signal vec : ~TYP[1];+ signal vec_index : integer range 0 to ~LIT[0]-1; begin- ~SYM[1] <= ~ARG[1];- ~SYM[2] <= ~ARG[2];+ vec <= ~ARG[1];++ vec_index <= ~ARG[2] -- pragma translate_off- process (~SYM[1],~SYM[2])- begin- if ~SYM[2] < ~SYM[1]'low or ~SYM[2] > ~SYM[1]'high then- assert false report (\"Index: \" & integer'image(~SYM[2]) & \", is out of bounds: \" & integer'image(~SYM[1]'low) & \" to \" & integer'image(~SYM[1]'high)) severity warning;- ~RESULT <= ~ERRORO;- else- -- pragma translate_on- ~RESULT <= ~SYM[1](~SYM[2]);- -- pragma translate_off- end if;- end process;+ mod ~LIT[0] -- pragma translate_on-end block;"+ ;++ ~RESULT <= vec(vec_index);+end block;+-- index end" } } , { "BlackBox" : { "name" : "CLaSH.Sized.Vector.replace_int" , "type" : "replace_int :: KnownNat n => Vec n a -> Int -> a -> Vec n a" , "templateD" :-"replaceVec_~SYM[0] : block- signal ~SYM[1] : ~TYP[1];- signal ~SYM[2] : ~TYP[2];- signal ~SYM[3] : ~TYP[3];+"-- replace begin+replaceVec_~SYM[0] : block+ signal vec : ~TYP[1];+ signal vec_index : integer range 0 to ~LIT[0]-1;+ signal din : ~TYP[3]; begin- ~SYM[1] <= ~ARG[1];- ~SYM[2] <= ~ARG[2];- ~SYM[3] <= ~ARG[3];- process(~SYM[1],~SYM[2],~SYM[3])- variable ~SYM[4] : ~TYP[1];+ vec <= ~ARG[1];+ vec_index <= ~ARG[2]+ -- pragma translate_off+ mod ~LIT[0]+ -- pragma translate_on+ ;+ din <= ~ARG[3];++ process(vec,vec_index,din)+ variable ivec : ~TYP[1]; begin- ~SYM[4] := ~SYM[1];- -- pragma translate_off- if ~SYM[2] < ~SYM[4]'low or ~SYM[2] > ~SYM[4]'high then- assert false report (\"Index: \" & integer'image(~SYM[2]) & \", is out of bounds: \" & integer'image(~SYM[1]'low) & \" to \" & integer'image(~SYM[1]'high)) severity warning;- ~SYM[4] := ~ERROR[1];- else- -- pragma translate_on- ~SYM[4](~SYM[2]) := ~SYM[3];- -- pragma translate_off- end if;- -- pragma translate_on- ~RESULT <= ~SYM[4];+ ivec := vec;+ ivec(vec_index) := din;+ ~RESULT <= ivec; end process;-end block;"+end block;+-- replace end" } } , { "BlackBox" :@@ -310,7 +326,8 @@ { "name" : "CLaSH.Sized.Vector.reverse" , "type" : "reverse :: Vec n a -> Vec n a" , "templateD" :-"reverse_~SYM[0] : block+"-- reverse begin+reverse_~SYM[0] : block signal ~SYM[1] : ~TYP[0]; begin ~SYM[1] <= ~ARG[0];@@ -324,7 +341,8 @@ ~RESULT(~SYM[1]'high - ~SYM[5]) <= ~SYM[1](~SYM[5]); end generate; end generate;-end block;"+end block;+-- reverse end" } } , { "BlackBox" :@@ -340,7 +358,8 @@ => Vec n (BitVector m) -- ARG[1] -> BitVector (n * m)" , "templateD" :-"concatBitVector_~SYM[0] : block+"-- concatBitVector begin+concatBitVector_~SYM[0] : block signal ~SYM[1] : ~TYP[1]; begin ~SYM[1] <= ~ARG[1];@@ -354,7 +373,8 @@ ~RESULT(((~SYM[5] * ~LIT[0]) + ~LIT[0] - 1) downto (~SYM[5] * ~LIT[0])) <= ~TYPMO(~SYM[1](~SYM[1]'high - ~SYM[5])); end generate; end generate;-end block;"+end block;+-- concatBitVector end" } } , { "BlackBox" :@@ -364,7 +384,8 @@ => BitVector (n * m) -- ARG[2] -> Vec n (BitVector m)" , "templateD" :-"unconcatBitVector_~SYM[0] : block+"-- unconcatBitVector begin+unconcatBitVector_~SYM[0] : block signal ~SYM[1] : ~TYP[2]; begin ~SYM[1] <= ~ARG[2];@@ -378,7 +399,8 @@ ~RESULT(~RESULT'high - ~SYM[5]) <= ~SYM[1](((~SYM[5] * ~LIT[1]) + ~LIT[1] - 1) downto (~SYM[5] * ~LIT[1])); end generate; end generate;-end block;"+end block;+-- unconcatBitVector end" } } ]
primitives/GHC.Base.json view
@@ -19,13 +19,15 @@ { "name" : "GHC.Base.divInt" , "type" : "divInt :: Int -> Int -> Int" , "templateD" :-"divInt_~SYM[0] : block+"-- divInt begin+divInt_~SYM[0] : block signal ~SYM[1] : ~TYP[1]; begin ~SYM[1] <= ~ARG[0] / ~ARG[1]; ~RESULT <= ~SYM[1] - 1 when ((~ARG[0] = abs ~ARG[0]) /= (~ARG[1] = abs ~ARG[1])) else ~SYM[1];-end block;"+end block;+-- divInt end" } } , { "BlackBox" :
primitives/GHC.CString.json view
@@ -1,6 +1,6 @@-[ { "Primitive" :- { "name" : "GHC.CString.unpackCString#"- , "primType" : "Function"+[ { "BlackBox" :+ { "name" : "GHC.CString.unpackCString#"+ , "templateE" : "~LIT[0]" } } , { "Primitive" :
primitives/GHC.Classes.json view
@@ -56,13 +56,15 @@ { "name" : "GHC.Classes.divInt#" , "type" : "divInt# :: Int# -> Int# -> Int#" , "templateD" :-"divInt_~SYM[0] : block+"-- divInt begin+divInt_~SYM[0] : block signal ~SYM[1] : ~TYP[1]; begin ~SYM[1] <= ~ARG[0] / ~ARG[1]; ~RESULT <= ~SYM[1] - 1 when ((~ARG[0] = abs ~ARG[0]) /= (~ARG[1] = abs ~ARG[1])) else ~SYM[1];-end block;"+end block;+-- divInt end" } } , { "BlackBox" :
primitives/GHC.Integer.Type.json view
@@ -44,13 +44,15 @@ { "name" : "GHC.Integer.Type.divInteger" , "type" : "divInteger :: Integer -> Integer -> Integer" , "templateD" :-"divInteger_~SYM[0] : block+"-- divInteger begin+divInteger_~SYM[0] : block signal ~SYM[1] : ~TYP[1]; begin ~SYM[1] <= ~ARG[0] / ~ARG[1]; ~RESULT <= ~SYM[1] - 1 when ((~ARG[0] = abs ~ARG[0]) /= (~ARG[1] = abs ~ARG[1])) else ~SYM[1];-end block;"+end block;+-- divInteger end" } } , { "BlackBox" :
primitives/GHC.Prim.json view
@@ -86,4 +86,22 @@ , "templateE" : "~ARG[0]" } }+, { "BlackBox" :+ { "name" : "GHC.Prim.uncheckedIShiftRA#"+ , "type" : "uncheckedIShiftRA# :: Int# -> Int# -> Int#"+ , "templateE" : "to_integer(shift_right(to_signed(~ARG[0],32),~ARG[1]))"+ }+ }+, { "BlackBox" :+ { "name" : "GHC.Prim.uncheckedIShiftRL#"+ , "type" : "uncheckedIShiftRL# :: Int# -> Int# -> Int#"+ , "templateE" : "to_integer(to_signed(~ARG[0],32) srl ~ARG[1])"+ }+ }+, { "BlackBox" :+ { "name" : "GHC.Prim.uncheckedIShiftL#"+ , "type" : "uncheckedIShiftL# :: Int# -> Int# -> Int#"+ , "templateE" : "to_integer(shift_left(to_signed(~ARG[0],32),~ARG[1]))"+ }+ } ]
src/CLaSH/Backend/VHDL.hs view
@@ -302,6 +302,7 @@ , "use IEEE.STD_LOGIC_1164.ALL" , "use IEEE.NUMERIC_STD.ALL" , "use IEEE.MATH_REAL.ALL"+ , "use std.textio.all" , "use work.all" , "use work." <> text (T.pack modName) <> "_types.all" ]@@ -570,9 +571,10 @@ where blit = bits (toBits sz i)-exprLit _ (BoolLit t) = if t then "true" else "false"-exprLit _ (BitLit b) = squotes $ bit_char b-exprLit _ l = error $ $(curLoc) ++ "exprLit: " ++ show l+exprLit _ (BoolLit t) = if t then "true" else "false"+exprLit _ (BitLit b) = squotes $ bit_char b+exprLit _ (StringLit s) = text . T.pack $ show s+exprLit _ l = error $ $(curLoc) ++ "exprLit: " ++ show l toBits :: Integral a => Int -> a -> [Bit] toBits size val = map (\x -> if odd x then H else L)