clash-vhdl-0.5.7: primitives/CLaSH.Prelude.BlockRam.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.BlockRam.blockRam#"
    , "type" :
"blockRam# :: KnownNat n       -- ARG[0]
           => SClock clk       -- clk,  ARG[1]
           -> Vec n a          -- init, ARG[2]
           -> Signal' clk Int  -- wr,   ARG[3]
           -> Signal' clk Int  -- rd,   ARG[4]
           -> Signal' clk Bool -- wren, ARG[5]
           -> Signal' clk a    -- din,  ARG[6]
           -> Signal' clk a"
    , "templateD" :
"-- blockRam begin
blockRam_~COMPNAME_~SYM[0] : block
  signal RAM  : ~TYP[2] := ~LIT[2];
  signal dout : ~TYP[6];
  signal wr   : integer range 0 to ~LIT[0] - 1;
  signal rd   : integer range 0 to ~LIT[0] - 1;
begin
  wr <= ~ARG[3]
  -- pragma translate_off
        mod ~LIT[0]
  -- pragma translate_on
        ;

  rd <= ~ARG[4]
  -- pragma translate_off
        mod ~LIT[0]
  -- pragma translate_on
        ;

  blockRam_~SYM[1] : process(~CLK[1])
  begin
    if rising_edge(~CLK[1]) then
      if ~ARG[5] then
        RAM(wr) <= ~ARG[6];
      end if;
      dout <= RAM(rd);
    end if;
  end process;

  ~RESULT <= dout;
end block;
-- blockRam end"
    }
  }
]