clash-vhdl-0.5.7: primitives/CLaSH.Prelude.ROM.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.ROM.asyncRom#"
    , "type" :
"asyncRom# :: KnownNat n -- ^ ARG[0]
           => Vec n a    -- ^ ARG[1]
           -> Int        -- ^ ARG[2]
           -> a"
    , "templateD" :
"-- asyncRom begin
asyncRom_~SYM[0] : block
  signal ROM       : ~TYP[1];
  signal rom_index : integer range 0 to ~LIT[0]-1;
begin
  ROM <= ARG[1];

  rom_index <= ~ARG[2]
  -- pragma translate_off
               mod ~LIT[0]
  -- pragma translate_on
               ;

  ~RESULT <= ROM(rom_index);
end block;
-- asyncRom end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Prelude.ROM.rom#"
    , "type" :
"rom# :: KnownNat n      -- ARG[0]
      => SClock clk      -- clk,  ARG[1]
      -> Vec n a         -- init, ARG[2]
      -> Signal' clk Int -- rd,   ARG[3]
      -> Signal' clk a"
    , "templateD" :
"-- rom begin
rom_~COMPNAME_~SYM[0] : block
  signal ROM  : ~TYP[2];
  signal rd   : integer range 0 to ~LIT[0]-1;
  signal dout : ~TYPO;
begin
  ROM <= ~ARG[2];

  rd <= ~ARG[3]
  -- pragma translate_off
        mod ~LIT[0]
  -- pragma translate_on
        ;

  rom : process (~CLK[1])
  begin
    if (rising_edge(~CLK[1])) then
      dout <= ROM(rd);
    end if;
  end process;

  ~RESULT <= dout;
end block;
-- rom end"
    }
  }
]