netlist-to-vhdl 0.3.2 → 0.3.3

raw patch · 2 files changed

+5/−1 lines, 2 filesPVP ok

version bump matches the API change (PVP)

API changes (from Hackage documentation)

Files

• Language/Netlist/GenVHDL.hs +4/−0
• netlist-to-vhdl.cabal +1/−1

@@ -11,10 +11,14 @@ -- Translates a Netlist AST ('Language.Netlist.AST') to VHDL. -------------------------------------------------------------------------------- +{-# LANGUAGE CPP #-} module Language.Netlist.GenVHDL(genVHDL) where  import Language.Netlist.AST +#if MIN_VERSION_base(4,11,0)+import Prelude hiding ((<>))+#endif import Text.PrettyPrint import Data.Maybe(catMaybes, mapMaybe) 

@@ -1,5 +1,5 @@ name:           netlist-to-vhdl-version:        0.3.2+version:        0.3.3 synopsis:       Convert a Netlist AST to VHDL description:    Convert a Netlist AST to VHDL category:       Language