diff --git a/Language/Netlist/GenVHDL.hs b/Language/Netlist/GenVHDL.hs
--- a/Language/Netlist/GenVHDL.hs
+++ b/Language/Netlist/GenVHDL.hs
@@ -11,10 +11,14 @@
 -- Translates a Netlist AST ('Language.Netlist.AST') to VHDL.
 --------------------------------------------------------------------------------
 
+{-# LANGUAGE CPP #-}
 module Language.Netlist.GenVHDL(genVHDL) where
 
 import Language.Netlist.AST
 
+#if MIN_VERSION_base(4,11,0)
+import Prelude hiding ((<>))
+#endif
 import Text.PrettyPrint
 import Data.Maybe(catMaybes, mapMaybe)
 
diff --git a/netlist-to-vhdl.cabal b/netlist-to-vhdl.cabal
--- a/netlist-to-vhdl.cabal
+++ b/netlist-to-vhdl.cabal
@@ -1,5 +1,5 @@
 name:           netlist-to-vhdl
-version:        0.3.2
+version:        0.3.3
 synopsis:       Convert a Netlist AST to VHDL
 description:    Convert a Netlist AST to VHDL
 category:       Language