clash-vhdl 0.5.3 → 0.5.4

raw patch · 6 files changed

+18/−8 lines, 6 filesdep ~clash-libPVP ok

version bump matches the API change (PVP)

Dependency ranges changed: clash-lib

API changes (from Hackage documentation)

Files

• CHANGELOG.md +8/−0
• clash-vhdl.cabal +2/−2
• primitives/CLaSH.Prelude.BlockRam.json +1/−1
• primitives/CLaSH.Prelude.Testbench.json +3/−1
• primitives/CLaSH.Signal.Internal.json +2/−2
• primitives/CLaSH.Sized.Internal.Unsigned.json +2/−2

@@ -1,5 +1,13 @@ # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package +## 0.5.4+* New features:+  * Make VHDL 'assert' primitive GHDL friendly+  * Generate smarter labels for `register` and `blockRam` blackboxes to make finding longest paths easier++* Fixes bugs:+  * Incorrect primitives for BitVector `minBound` and `maxBound`+ ## 0.5.3 *May 1st 2015* * New features:   * Support wrapper generation

@@ -1,5 +1,5 @@ Name:                 clash-vhdl-Version:              0.5.3+Version:              0.5.4 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -66,7 +66,7 @@   CPP-Options:        -DCABAL    Build-depends:      base                    >= 4.6.0.1 && < 5,-                      clash-lib               >= 0.5,+                      clash-lib               >= 0.5.4,                       clash-prelude           >= 0.7.2,                       fgl                     >= 5.4.2.4,                       lens                    >= 3.9.2,

@@ -10,7 +10,7 @@            -> Signal' clk a            -- din,  ARG[7]            -> Signal' clk a"     , "templateD" :-"blockram_~SYM[0] : block+"blockRam_~COMPNAME_~SYM[0] : block   signal ~SYM[1] : ~TYP[3] := ~LIT[3]; -- ram   signal ~SYM[2] : ~TYP[7]; -- inp   signal ~SYM[3] : ~TYP[7]; -- outp

@@ -11,11 +11,13 @@   -- pragma translate_off   function slv2string (slv : std_logic_vector) return STRING is      variable result : string (1 to slv'length);+     variable res_l : string (1 to 3);      variable r : integer;    begin      r := 1;      for i in slv'range loop-        result(r) := std_logic'image(slv(i))(2);+        res_l := std_logic'image(slv(i));+        result(r) := res_l(2);         r := r + 1;      end loop;      return result;

@@ -6,7 +6,7 @@            -> Signal' clk a  -- ARG[2]            -> Signal' clk a"     , "templateD" :-"register_~SYM[0] : block+"register_~COMPNAME_~SYM[0] : block   signal ~SYM[1] : ~TYP[1];   signal ~SYM[2] : ~TYP[2]; begin@@ -34,7 +34,7 @@         -> Signal' clk a    -- ARG[3]         -> Signal' clk a"     , "templateD" :-"regEn_~SYM[0] : block+"regEn_~COMPNAME_~SYM[0] : block   signal ~SYM[1] : ~TYP[1];   signal ~SYM[2] : ~TYP[2];   signal ~SYM[3] : ~TYP[3];

@@ -56,14 +56,14 @@     { "name"      : "CLaSH.Sized.Internal.Unsigned.minBound#"     , "type"      : "minBound# :: KnownNat n => Unsigned n"     , "comment"   : "Generates incorrect VDHL for n=0"-    , "templateE" : "unsigned'(~LIT[0]-1 downto 0 => '0');"+    , "templateE" : "unsigned'(~LIT[0]-1 downto 0 => '0')"     }   } , { "BlackBox" :     { "name"      : "CLaSH.Sized.Internal.Unsigned.maxBound#"     , "type"      : "maxBound# :: KnownNat n => Unsigned n"     , "comment"   : "Generates incorrect VDHL for n=0"-    , "templateE" : "unsigned'(~LIT[0]-1 downto 0 => '1');"+    , "templateE" : "unsigned'(~LIT[0]-1 downto 0 => '1')"     }   } , { "BlackBox" :