diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,13 @@
 # Changelog for the [`clash-vhdl`](http://hackage.haskell.org/package/clash-vhdl) package
 
+## 0.5.4
+* New features:
+  * Make VHDL 'assert' primitive GHDL friendly
+  * Generate smarter labels for `register` and `blockRam` blackboxes to make finding longest paths easier
+
+* Fixes bugs:
+  * Incorrect primitives for BitVector `minBound` and `maxBound`
+
 ## 0.5.3 *May 1st 2015*
 * New features:
   * Support wrapper generation
diff --git a/clash-vhdl.cabal b/clash-vhdl.cabal
--- a/clash-vhdl.cabal
+++ b/clash-vhdl.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-vhdl
-Version:              0.5.3
+Version:              0.5.4
 Synopsis:             CAES Language for Synchronous Hardware - VHDL backend
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
@@ -66,7 +66,7 @@
   CPP-Options:        -DCABAL
 
   Build-depends:      base                    >= 4.6.0.1 && < 5,
-                      clash-lib               >= 0.5,
+                      clash-lib               >= 0.5.4,
                       clash-prelude           >= 0.7.2,
                       fgl                     >= 5.4.2.4,
                       lens                    >= 3.9.2,
diff --git a/primitives/CLaSH.Prelude.BlockRam.json b/primitives/CLaSH.Prelude.BlockRam.json
--- a/primitives/CLaSH.Prelude.BlockRam.json
+++ b/primitives/CLaSH.Prelude.BlockRam.json
@@ -10,7 +10,7 @@
            -> Signal' clk a            -- din,  ARG[7]
            -> Signal' clk a"
     , "templateD" :
-"blockram_~SYM[0] : block
+"blockRam_~COMPNAME_~SYM[0] : block
   signal ~SYM[1] : ~TYP[3] := ~LIT[3]; -- ram
   signal ~SYM[2] : ~TYP[7]; -- inp
   signal ~SYM[3] : ~TYP[7]; -- outp
diff --git a/primitives/CLaSH.Prelude.Testbench.json b/primitives/CLaSH.Prelude.Testbench.json
--- a/primitives/CLaSH.Prelude.Testbench.json
+++ b/primitives/CLaSH.Prelude.Testbench.json
@@ -11,11 +11,13 @@
   -- pragma translate_off
   function slv2string (slv : std_logic_vector) return STRING is
      variable result : string (1 to slv'length);
+     variable res_l : string (1 to 3);
      variable r : integer;
    begin
      r := 1;
      for i in slv'range loop
-        result(r) := std_logic'image(slv(i))(2);
+        res_l := std_logic'image(slv(i));
+        result(r) := res_l(2);
         r := r + 1;
      end loop;
      return result;
diff --git a/primitives/CLaSH.Signal.Internal.json b/primitives/CLaSH.Signal.Internal.json
--- a/primitives/CLaSH.Signal.Internal.json
+++ b/primitives/CLaSH.Signal.Internal.json
@@ -6,7 +6,7 @@
            -> Signal' clk a  -- ARG[2]
            -> Signal' clk a"
     , "templateD" :
-"register_~SYM[0] : block
+"register_~COMPNAME_~SYM[0] : block
   signal ~SYM[1] : ~TYP[1];
   signal ~SYM[2] : ~TYP[2];
 begin
@@ -34,7 +34,7 @@
         -> Signal' clk a    -- ARG[3]
         -> Signal' clk a"
     , "templateD" :
-"regEn_~SYM[0] : block
+"regEn_~COMPNAME_~SYM[0] : block
   signal ~SYM[1] : ~TYP[1];
   signal ~SYM[2] : ~TYP[2];
   signal ~SYM[3] : ~TYP[3];
diff --git a/primitives/CLaSH.Sized.Internal.Unsigned.json b/primitives/CLaSH.Sized.Internal.Unsigned.json
--- a/primitives/CLaSH.Sized.Internal.Unsigned.json
+++ b/primitives/CLaSH.Sized.Internal.Unsigned.json
@@ -56,14 +56,14 @@
     { "name"      : "CLaSH.Sized.Internal.Unsigned.minBound#"
     , "type"      : "minBound# :: KnownNat n => Unsigned n"
     , "comment"   : "Generates incorrect VDHL for n=0"
-    , "templateE" : "unsigned'(~LIT[0]-1 downto 0 => '0');"
+    , "templateE" : "unsigned'(~LIT[0]-1 downto 0 => '0')"
     }
   }
 , { "BlackBox" :
     { "name"      : "CLaSH.Sized.Internal.Unsigned.maxBound#"
     , "type"      : "maxBound# :: KnownNat n => Unsigned n"
     , "comment"   : "Generates incorrect VDHL for n=0"
-    , "templateE" : "unsigned'(~LIT[0]-1 downto 0 => '1');"
+    , "templateE" : "unsigned'(~LIT[0]-1 downto 0 => '1')"
     }
   }
 , { "BlackBox" :