clash-prelude 0.9 → 0.9.1
raw patch · 4 files changed
+64/−61 lines, 4 filesPVP ok
version bump matches the API change (PVP)
API changes (from Hackage documentation)
Files
- CHANGELOG.md +3/−0
- clash-prelude.cabal +1/−1
- src/CLaSH/Prelude/BlockRam/File.hs +24/−24
- src/CLaSH/Prelude/ROM/File.hs +36/−36
CHANGELOG.md view
@@ -1,5 +1,8 @@ # Changelog for [`clash-prelude` package](http://hackage.haskell.org/package/clash-prelude) +## 0.9.1 *June 26th 2015*+* Updated documentation on data-file support on Altera/Quartus+ ## 0.9 *June 25th 2015* * New features: * Add operations on singleton natural numbers: `addSNat`, `subSNat`, `mulSNat`, and `powSNat`.
clash-prelude.cabal view
@@ -1,5 +1,5 @@ Name: clash-prelude-Version: 0.9+Version: 0.9.1 Synopsis: CAES Language for Synchronous Hardware - Prelude library Description: CλaSH (pronounced ‘clash’) is a functional hardware description language that
src/CLaSH/Prelude/BlockRam/File.hs view
@@ -113,12 +113,12 @@ -- below: -- -- @--- | VHDL | Verilog | SystemVerilog |--- ===============+==========+=========================+===============+--- Altera/Quartus | Broken | No Verilog-2005 support | Works |--- Xilinx/ISE | Works | Works | Works |--- ASIC | Untested | Untested | Untested |--- ===============+==========+=========================+===============++-- | VHDL | Verilog | SystemVerilog |+-- ===============+==========+==========+===============++-- Altera/Quartus | Broken | Works | Works |+-- Xilinx/ISE | Works | Works | Works |+-- ASIC | Untested | Untested | Untested |+-- ===============+==========+==========+===============+ -- @ -- -- Additional helpful information:@@ -152,12 +152,12 @@ -- below: -- -- @--- | VHDL | Verilog | SystemVerilog |--- ===============+==========+=========================+===============+--- Altera/Quartus | Broken | No Verilog-2005 support | Works |--- Xilinx/ISE | Works | Works | Works |--- ASIC | Untested | Untested | Untested |--- ===============+==========+=========================+===============++-- | VHDL | Verilog | SystemVerilog |+-- ===============+==========+==========+===============++-- Altera/Quartus | Broken | Works | Works |+-- Xilinx/ISE | Works | Works | Works |+-- ASIC | Untested | Untested | Untested |+-- ===============+==========+==========+===============+ -- @ -- -- Additional helpful information:@@ -190,12 +190,12 @@ -- below: -- -- @--- | VHDL | Verilog | SystemVerilog |--- ===============+==========+=========================+===============+--- Altera/Quartus | Broken | No Verilog-2005 support | Works |--- Xilinx/ISE | Works | Works | Works |--- ASIC | Untested | Untested | Untested |--- ===============+==========+=========================+===============++-- | VHDL | Verilog | SystemVerilog |+-- ===============+==========+==========+===============++-- Altera/Quartus | Broken | Works | Works |+-- Xilinx/ISE | Works | Works | Works |+-- ASIC | Untested | Untested | Untested |+-- ===============+==========+==========+===============+ -- @ -- -- Additional helpful information:@@ -229,12 +229,12 @@ -- below: -- -- @--- | VHDL | Verilog | SystemVerilog |--- ===============+==========+=========================+===============+--- Altera/Quartus | Broken | No Verilog-2005 support | Works |--- Xilinx/ISE | Works | Works | Works |--- ASIC | Untested | Untested | Untested |--- ===============+==========+=========================+===============++-- | VHDL | Verilog | SystemVerilog |+-- ===============+==========+==========+===============++-- Altera/Quartus | Broken | Works | Works |+-- Xilinx/ISE | Works | Works | Works |+-- ASIC | Untested | Untested | Untested |+-- ===============+==========+==========+===============+ -- @ -- -- Additional helpful information:
src/CLaSH/Prelude/ROM/File.hs view
@@ -104,12 +104,12 @@ -- below: -- -- @--- | VHDL | Verilog | SystemVerilog |--- ===============+==========+=========================+===============+--- Altera/Quartus | Broken | No Verilog-2005 support | Works |--- Xilinx/ISE | Works | Works | Works |--- ASIC | Untested | Untested | Untested |--- ===============+==========+=========================+===============++-- | VHDL | Verilog | SystemVerilog |+-- ===============+==========+==========+===============++-- Altera/Quartus | Broken | Works | Works |+-- Xilinx/ISE | Works | Works | Works |+-- ASIC | Untested | Untested | Untested |+-- ===============+==========+==========+===============+ -- @ -- -- Additional helpful information:@@ -133,12 +133,12 @@ -- below: -- -- @--- | VHDL | Verilog | SystemVerilog |--- ===============+==========+=========================+===============+--- Altera/Quartus | Broken | No Verilog-2005 support | Works |--- Xilinx/ISE | Works | Works | Works |--- ASIC | Untested | Untested | Untested |--- ===============+==========+=========================+===============++-- | VHDL | Verilog | SystemVerilog |+-- ===============+==========+==========+===============++-- Altera/Quartus | Broken | Works | Works |+-- Xilinx/ISE | Works | Works | Works |+-- ASIC | Untested | Untested | Untested |+-- ===============+==========+==========+===============+ -- @ -- -- Additional helpful information:@@ -175,12 +175,12 @@ -- below: -- -- @--- | VHDL | Verilog | SystemVerilog |--- ===============+==========+=========================+===============+--- Altera/Quartus | Broken | No Verilog-2005 support | Works |--- Xilinx/ISE | Works | Works | Works |--- ASIC | Untested | Untested | Untested |--- ===============+==========+=========================+===============++-- | VHDL | Verilog | SystemVerilog |+-- ===============+==========+==========+===============++-- Altera/Quartus | Broken | Works | Works |+-- Xilinx/ISE | Works | Works | Works |+-- ASIC | Untested | Untested | Untested |+-- ===============+==========+==========+===============+ -- @ -- -- Additional helpful information:@@ -207,12 +207,12 @@ -- below: -- -- @--- | VHDL | Verilog | SystemVerilog |--- ===============+==========+=========================+===============+--- Altera/Quartus | Broken | No Verilog-2005 support | Works |--- Xilinx/ISE | Works | Works | Works |--- ASIC | Untested | Untested | Untested |--- ===============+==========+=========================+===============++-- | VHDL | Verilog | SystemVerilog |+-- ===============+==========+==========+===============++-- Altera/Quartus | Broken | Works | Works |+-- Xilinx/ISE | Works | Works | Works |+-- ASIC | Untested | Untested | Untested |+-- ===============+==========+==========+===============+ -- @ -- -- Additional helpful information:@@ -238,12 +238,12 @@ -- below: -- -- @--- | VHDL | Verilog | SystemVerilog |--- ===============+==========+=========================+===============+--- Altera/Quartus | Broken | No Verilog-2005 support | Works |--- Xilinx/ISE | Works | Works | Works |--- ASIC | Untested | Untested | Untested |--- ===============+==========+=========================+===============++-- | VHDL | Verilog | SystemVerilog |+-- ===============+==========+==========+===============++-- Altera/Quartus | Broken | Works | Works |+-- Xilinx/ISE | Works | Works | Works |+-- ASIC | Untested | Untested | Untested |+-- ===============+==========+==========+===============+ -- @ -- -- Additional helpful information:@@ -272,12 +272,12 @@ -- below: -- -- @--- | VHDL | Verilog | SystemVerilog |--- ===============+==========+=========================+===============+--- Altera/Quartus | Broken | No Verilog-2005 support | Works |--- Xilinx/ISE | Works | Works | Works |--- ASIC | Untested | Untested | Untested |--- ===============+==========+=========================+===============++-- | VHDL | Verilog | SystemVerilog |+-- ===============+==========+==========+===============++-- Altera/Quartus | Broken | Works | Works |+-- Xilinx/ISE | Works | Works | Works |+-- ASIC | Untested | Untested | Untested |+-- ===============+==========+==========+===============+ -- @ -- -- Additional helpful information: