diff --git a/CHANGELOG.md b/CHANGELOG.md
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@@ -1,5 +1,8 @@
 # Changelog for [`clash-prelude` package](http://hackage.haskell.org/package/clash-prelude)
 
+## 0.9.1 *June 26th 2015*
+* Updated documentation on data-file support on Altera/Quartus
+
 ## 0.9 *June 25th 2015*
 * New features:
   * Add operations on singleton natural numbers: `addSNat`, `subSNat`, `mulSNat`, and `powSNat`.
diff --git a/clash-prelude.cabal b/clash-prelude.cabal
--- a/clash-prelude.cabal
+++ b/clash-prelude.cabal
@@ -1,5 +1,5 @@
 Name:                 clash-prelude
-Version:              0.9
+Version:              0.9.1
 Synopsis:             CAES Language for Synchronous Hardware - Prelude library
 Description:
   CλaSH (pronounced ‘clash’) is a functional hardware description language that
diff --git a/src/CLaSH/Prelude/BlockRam/File.hs b/src/CLaSH/Prelude/BlockRam/File.hs
--- a/src/CLaSH/Prelude/BlockRam/File.hs
+++ b/src/CLaSH/Prelude/BlockRam/File.hs
@@ -113,12 +113,12 @@
 -- below:
 --
 --     @
---                    | VHDL     | Verilog                 | SystemVerilog |
---     ===============+==========+=========================+===============+
---     Altera/Quartus | Broken   | No Verilog-2005 support | Works         |
---     Xilinx/ISE     | Works    | Works                   | Works         |
---     ASIC           | Untested | Untested                | Untested      |
---     ===============+==========+=========================+===============+
+--                    | VHDL     | Verilog  | SystemVerilog |
+--     ===============+==========+==========+===============+
+--     Altera/Quartus | Broken   | Works    | Works         |
+--     Xilinx/ISE     | Works    | Works    | Works         |
+--     ASIC           | Untested | Untested | Untested      |
+--     ===============+==========+==========+===============+
 --     @
 --
 -- Additional helpful information:
@@ -152,12 +152,12 @@
 -- below:
 --
 --     @
---                    | VHDL     | Verilog                 | SystemVerilog |
---     ===============+==========+=========================+===============+
---     Altera/Quartus | Broken   | No Verilog-2005 support | Works         |
---     Xilinx/ISE     | Works    | Works                   | Works         |
---     ASIC           | Untested | Untested                | Untested      |
---     ===============+==========+=========================+===============+
+--                    | VHDL     | Verilog  | SystemVerilog |
+--     ===============+==========+==========+===============+
+--     Altera/Quartus | Broken   | Works    | Works         |
+--     Xilinx/ISE     | Works    | Works    | Works         |
+--     ASIC           | Untested | Untested | Untested      |
+--     ===============+==========+==========+===============+
 --     @
 --
 -- Additional helpful information:
@@ -190,12 +190,12 @@
 -- below:
 --
 --     @
---                    | VHDL     | Verilog                 | SystemVerilog |
---     ===============+==========+=========================+===============+
---     Altera/Quartus | Broken   | No Verilog-2005 support | Works         |
---     Xilinx/ISE     | Works    | Works                   | Works         |
---     ASIC           | Untested | Untested                | Untested      |
---     ===============+==========+=========================+===============+
+--                    | VHDL     | Verilog  | SystemVerilog |
+--     ===============+==========+==========+===============+
+--     Altera/Quartus | Broken   | Works    | Works         |
+--     Xilinx/ISE     | Works    | Works    | Works         |
+--     ASIC           | Untested | Untested | Untested      |
+--     ===============+==========+==========+===============+
 --     @
 --
 -- Additional helpful information:
@@ -229,12 +229,12 @@
 -- below:
 --
 --     @
---                    | VHDL     | Verilog                 | SystemVerilog |
---     ===============+==========+=========================+===============+
---     Altera/Quartus | Broken   | No Verilog-2005 support | Works         |
---     Xilinx/ISE     | Works    | Works                   | Works         |
---     ASIC           | Untested | Untested                | Untested      |
---     ===============+==========+=========================+===============+
+--                    | VHDL     | Verilog  | SystemVerilog |
+--     ===============+==========+==========+===============+
+--     Altera/Quartus | Broken   | Works    | Works         |
+--     Xilinx/ISE     | Works    | Works    | Works         |
+--     ASIC           | Untested | Untested | Untested      |
+--     ===============+==========+==========+===============+
 --     @
 --
 -- Additional helpful information:
diff --git a/src/CLaSH/Prelude/ROM/File.hs b/src/CLaSH/Prelude/ROM/File.hs
--- a/src/CLaSH/Prelude/ROM/File.hs
+++ b/src/CLaSH/Prelude/ROM/File.hs
@@ -104,12 +104,12 @@
 -- below:
 --
 --     @
---                    | VHDL     | Verilog                 | SystemVerilog |
---     ===============+==========+=========================+===============+
---     Altera/Quartus | Broken   | No Verilog-2005 support | Works         |
---     Xilinx/ISE     | Works    | Works                   | Works         |
---     ASIC           | Untested | Untested                | Untested      |
---     ===============+==========+=========================+===============+
+--                    | VHDL     | Verilog  | SystemVerilog |
+--     ===============+==========+==========+===============+
+--     Altera/Quartus | Broken   | Works    | Works         |
+--     Xilinx/ISE     | Works    | Works    | Works         |
+--     ASIC           | Untested | Untested | Untested      |
+--     ===============+==========+==========+===============+
 --     @
 --
 -- Additional helpful information:
@@ -133,12 +133,12 @@
 -- below:
 --
 --     @
---                    | VHDL     | Verilog                 | SystemVerilog |
---     ===============+==========+=========================+===============+
---     Altera/Quartus | Broken   | No Verilog-2005 support | Works         |
---     Xilinx/ISE     | Works    | Works                   | Works         |
---     ASIC           | Untested | Untested                | Untested      |
---     ===============+==========+=========================+===============+
+--                    | VHDL     | Verilog  | SystemVerilog |
+--     ===============+==========+==========+===============+
+--     Altera/Quartus | Broken   | Works    | Works         |
+--     Xilinx/ISE     | Works    | Works    | Works         |
+--     ASIC           | Untested | Untested | Untested      |
+--     ===============+==========+==========+===============+
 --     @
 --
 -- Additional helpful information:
@@ -175,12 +175,12 @@
 -- below:
 --
 --     @
---                    | VHDL     | Verilog                 | SystemVerilog |
---     ===============+==========+=========================+===============+
---     Altera/Quartus | Broken   | No Verilog-2005 support | Works         |
---     Xilinx/ISE     | Works    | Works                   | Works         |
---     ASIC           | Untested | Untested                | Untested      |
---     ===============+==========+=========================+===============+
+--                    | VHDL     | Verilog  | SystemVerilog |
+--     ===============+==========+==========+===============+
+--     Altera/Quartus | Broken   | Works    | Works         |
+--     Xilinx/ISE     | Works    | Works    | Works         |
+--     ASIC           | Untested | Untested | Untested      |
+--     ===============+==========+==========+===============+
 --     @
 --
 -- Additional helpful information:
@@ -207,12 +207,12 @@
 -- below:
 --
 --     @
---                    | VHDL     | Verilog                 | SystemVerilog |
---     ===============+==========+=========================+===============+
---     Altera/Quartus | Broken   | No Verilog-2005 support | Works         |
---     Xilinx/ISE     | Works    | Works                   | Works         |
---     ASIC           | Untested | Untested                | Untested      |
---     ===============+==========+=========================+===============+
+--                    | VHDL     | Verilog  | SystemVerilog |
+--     ===============+==========+==========+===============+
+--     Altera/Quartus | Broken   | Works    | Works         |
+--     Xilinx/ISE     | Works    | Works    | Works         |
+--     ASIC           | Untested | Untested | Untested      |
+--     ===============+==========+==========+===============+
 --     @
 --
 -- Additional helpful information:
@@ -238,12 +238,12 @@
 -- below:
 --
 --     @
---                    | VHDL     | Verilog                 | SystemVerilog |
---     ===============+==========+=========================+===============+
---     Altera/Quartus | Broken   | No Verilog-2005 support | Works         |
---     Xilinx/ISE     | Works    | Works                   | Works         |
---     ASIC           | Untested | Untested                | Untested      |
---     ===============+==========+=========================+===============+
+--                    | VHDL     | Verilog  | SystemVerilog |
+--     ===============+==========+==========+===============+
+--     Altera/Quartus | Broken   | Works    | Works         |
+--     Xilinx/ISE     | Works    | Works    | Works         |
+--     ASIC           | Untested | Untested | Untested      |
+--     ===============+==========+==========+===============+
 --     @
 --
 -- Additional helpful information:
@@ -272,12 +272,12 @@
 -- below:
 --
 --     @
---                    | VHDL     | Verilog                 | SystemVerilog |
---     ===============+==========+=========================+===============+
---     Altera/Quartus | Broken   | No Verilog-2005 support | Works         |
---     Xilinx/ISE     | Works    | Works                   | Works         |
---     ASIC           | Untested | Untested                | Untested      |
---     ===============+==========+=========================+===============+
+--                    | VHDL     | Verilog  | SystemVerilog |
+--     ===============+==========+==========+===============+
+--     Altera/Quartus | Broken   | Works    | Works         |
+--     Xilinx/ISE     | Works    | Works    | Works         |
+--     ASIC           | Untested | Untested | Untested      |
+--     ===============+==========+==========+===============+
 --     @
 --
 -- Additional helpful information: