clash-prelude 0.10.6 → 0.10.7

raw patch · 4 files changed

+8/−5 lines, 4 filesdep ~doctest

Dependency ranges changed: doctest

Files

• CHANGELOG.md +3/−0
• clash-prelude.cabal +2/−2
• src/CLaSH/Annotations/TopEntity.hs +2/−2
• src/CLaSH/Tutorial.hs +1/−1

@@ -1,5 +1,8 @@ # Changelog for [`clash-prelude` package](http://hackage.haskell.org/package/clash-prelude) +## 0.10.7 *April 7th 2016*+* Support doctest-0.11.0+ ## 0.10.6 *February 10th 2016* * Fixes bugs:   * `CLaSH.Prelude.DataFlow.parNDF` is not lazy enough

@@ -1,5 +1,5 @@ Name:                 clash-prelude-Version:              0.10.6+Version:              0.10.7 Synopsis:             CAES Language for Synchronous Hardware - Prelude library Description:   CλaSH (pronounced ‘clash’) is a functional hardware description language that@@ -189,4 +189,4 @@   else     build-depends:       base    >= 4     && < 5,-      doctest >= 0.9.1 && < 0.11+      doctest >= 0.9.1 && < 0.12

@@ -205,8 +205,8 @@   -- * __Verilog__: @[n-1:0]@   -- * __SystemVerilog__: @logic [n-1:0]@   , t_extraOut :: [(String,Int)]-  -- ^ Extra output ports, where every tuple holds the name of the input port-  -- and the number of bits are used for that input port.+  -- ^ Extra output ports, where every tuple holds the name of the output port+  -- and the number of bits are used for that output port.   --   -- So given a bit-width @n@, the port has type:   --

@@ -1226,7 +1226,7 @@  @ { \"BlackBox\" :-    { "name"      : "CLaSH.Prelude.BlockRam.blockRam'"+    { "name"      : "CLaSH.Prelude.BlockRam.blockRam#"     , "templateD" : "// blockRam ~SIGD[RAM_~SYM[0]][2];