clash-lib 1.6.6 → 1.8.0

raw patch · 143 files changed

+8227/−3082 lines, 143 filesdep +docoptdep +doctest-paralleldep +infinite-listdep −interpolatedep ~ansi-terminaldep ~basedep ~clash-preludenew-component:exe:static-filesPVP ok

version bump matches the API change (PVP)

Dependencies added: docopt, doctest-parallel, infinite-list, prettyprinter-interp, string-interpolate, tasty-th

Dependencies removed: interpolate

Dependency ranges changed: ansi-terminal, base, clash-prelude, deepseq, directory, extra, filepath, ghc, ghc-bignum, mtl, tasty, template-haskell

API changes (from Hackage documentation)

Files

• CHANGELOG.md +141/−3
• README.md +2/−3
• clash-lib.cabal +83/−13
• data-files/tcl/clashConnector.tcl +606/−0
• prims/common/Clash_Explicit_Signal.primitives.yaml +16/−3
• prims/common/Clash_Intel_ClockGen.primitives.yaml +2/−2
• prims/common/Clash_Magic.primitives.yaml +6/−0
• prims/common/Clash_XException.primitives.yaml +1/−2
• prims/common/Clash_Xilinx_ClockGen.primitives.yaml +22/−0
• prims/common/GHC_Prim.primitives.yaml +64/−0
• prims/common/GHC_Prim_Panic.primitives.yaml +7/−0
• prims/common/GHC_TypeNats.primitives.yaml +6/−1
• prims/common/GHC_Types.primitives.yaml +14/−0
• prims/commonverilog/Clash_Explicit_SimIO.primitives.yaml +4/−0
• prims/commonverilog/Clash_Explicit_Testbench.primitives.yaml +4/−0
• prims/commonverilog/Clash_Signal_Internal.primitives.yaml +2/−2
• prims/commonverilog/Clash_Xilinx_ClockGen.primitives.yaml +0/−42
• prims/commonverilog/GHC_Num_Integer.primitives.yaml +25/−0
• prims/commonverilog/GHC_Prim.primitives.yaml +616/−0
• prims/systemverilog/Clash_Explicit_BlockRam.primitives.yaml +3/−60
• prims/systemverilog/Clash_Explicit_DDR.primitives.yaml +4/−3
• prims/systemverilog/Clash_Explicit_ROM.primitives.yaml +1/−1
• prims/systemverilog/Clash_Explicit_Testbench.primitives.yaml +0/−62
• prims/systemverilog/Clash_Prelude_ROM.primitives.yaml +9/−7
• prims/systemverilog/Clash_Signal_Internal.primitives.yaml +66/−14
• prims/systemverilog/Clash_Sized_Internal_BitVector.primitives.yaml +2/−0
• prims/systemverilog/Clash_Sized_Vector.primitives.yaml +1/−0
• prims/systemverilog/GHC_Base.primitives.yaml +17/−5
• prims/systemverilog/GHC_Prim.primitives.yaml +84/−0
• prims/verilog/Clash_Explicit_BlockRam.primitives.yaml +6/−64
• prims/verilog/Clash_Explicit_BlockRam_Blob.primitives.yaml +1/−1
• prims/verilog/Clash_Explicit_BlockRam_File.primitives.yaml +1/−1
• prims/verilog/Clash_Explicit_DDR.primitives.yaml +13/−4
• prims/verilog/Clash_Explicit_ROM.primitives.yaml +2/−2
• prims/verilog/Clash_Explicit_ROM_Blob.primitives.yaml +1/−1
• prims/verilog/Clash_Explicit_ROM_File.primitives.yaml +1/−1
• prims/verilog/Clash_Explicit_Testbench.primitives.yaml +0/−67
• prims/verilog/Clash_Prelude_ROM.primitives.yaml +9/−7
• prims/verilog/Clash_Signal_Internal.primitives.yaml +66/−17
• prims/verilog/Clash_Sized_Internal_BitVector.primitives.yaml +2/−2
• prims/verilog/Clash_Sized_Vector.primitives.yaml +5/−5
• prims/verilog/GHC_Base.primitives.yaml +17/−5
• prims/verilog/GHC_Prim.primitives.yaml +84/−0
• prims/vhdl/Clash_Explicit_BlockRam.primitives.yaml +6/−67
• prims/vhdl/Clash_Explicit_BlockRam_Blob.primitives.yaml +1/−0
• prims/vhdl/Clash_Explicit_BlockRam_File.primitives.yaml +1/−0
• prims/vhdl/Clash_Explicit_DDR.primitives.yaml +3/−3
• prims/vhdl/Clash_Explicit_ROM.primitives.yaml +2/−1
• prims/vhdl/Clash_Explicit_ROM_Blob.primitives.yaml +1/−0
• prims/vhdl/Clash_Explicit_ROM_File.primitives.yaml +1/−0
• prims/vhdl/Clash_Explicit_Testbench.primitives.yaml +4/−32
• prims/vhdl/Clash_Prelude_ROM.primitives.yaml +9/−7
• prims/vhdl/Clash_Signal_Internal.primitives.yaml +55/−10
• prims/vhdl/Clash_Sized_Internal_BitVector.primitives.yaml +2/−0
• prims/vhdl/Clash_Sized_Vector.primitives.yaml +1/−0
• prims/vhdl/Clash_Xilinx_ClockGen.primitives.yaml +0/−65
• prims/vhdl/GHC_Base.primitives.yaml +12/−5
• prims/vhdl/GHC_Num_Integer.primitives.yaml +26/−4
• prims/vhdl/GHC_Prim.primitives.yaml +1000/−0
• src/Clash/Backend.hs +8/−3
• src/Clash/Backend/SystemVerilog.hs +62/−31
• src/Clash/Backend/VHDL.hs +129/−78
• src/Clash/Backend/Verilog.hs +120/−46
• src/Clash/Backend/Verilog/Time.hs +127/−0
• src/Clash/Core/Evaluator/Types.hs +13/−2
• src/Clash/Core/HasType.hs +13/−7
• src/Clash/Core/Literal.hs +9/−0
• src/Clash/Core/PartialEval/AsTerm.hs +0/−1
• src/Clash/Core/PartialEval/NormalForm.hs +0/−2
• src/Clash/Core/Pretty.hs +32/−17
• src/Clash/Core/Subst.hs +2/−8
• src/Clash/Core/Subst.hs-boot +1/−0
• src/Clash/Core/Term.hs +18/−6
• src/Clash/Core/TermInfo.hs +4/−6
• src/Clash/Core/TermLiteral.hs +141/−17
• src/Clash/Core/TermLiteral/TH.hs +147/−8
• src/Clash/Core/TyCon.hs +7/−6
• src/Clash/Core/Type.hs +81/−14
• src/Clash/Core/TysPrim.hs +178/−11
• src/Clash/Core/Util.hs +98/−81
• src/Clash/Core/Var.hs +1/−21
• src/Clash/Core/VarEnv.hs +48/−37
• src/Clash/Data/UniqMap.hs +235/−0
• src/Clash/DataFiles.hs +63/−0
• src/Clash/Driver.hs +60/−39
• src/Clash/Driver/Manifest.hs +8/−8
• src/Clash/Driver/Types.hs +22/−10
• src/Clash/Netlist.hs +145/−132
• src/Clash/Netlist.hs-boot +7/−3
• src/Clash/Netlist/BlackBox.hs +235/−147
• src/Clash/Netlist/BlackBox/Parser.hs +4/−1
• src/Clash/Netlist/BlackBox/Types.hs +9/−7
• src/Clash/Netlist/BlackBox/Util.hs +163/−98
• src/Clash/Netlist/Expr.hs +172/−0
• src/Clash/Netlist/Id.hs +13/−6
• src/Clash/Netlist/Id/Common.hs +1/−1
• src/Clash/Netlist/Id/Internal.hs +4/−2
• src/Clash/Netlist/Types.hs +187/−26
• src/Clash/Netlist/Types.hs-boot +29/−1
• src/Clash/Netlist/Util.hs +308/−109
• src/Clash/Normalize.hs +11/−14
• src/Clash/Normalize/PrimitiveReductions.hs +303/−258
• src/Clash/Normalize/Transformations/Case.hs +14/−10
• src/Clash/Normalize/Transformations/DEC.hs +14/−10
• src/Clash/Normalize/Transformations/EtaExpand.hs +2/−2
• src/Clash/Normalize/Transformations/Inline.hs +9/−9
• src/Clash/Normalize/Transformations/Letrec.hs +18/−13
• src/Clash/Normalize/Transformations/Reduce.hs +244/−159
• src/Clash/Normalize/Transformations/Specialize.hs +49/−13
• src/Clash/Normalize/Util.hs +8/−7
• src/Clash/Primitives/Annotations/SynthesisAttributes.hs +79/−0
• src/Clash/Primitives/DSL.hs +370/−142
• src/Clash/Primitives/GHC/Int.hs +8/−2
• src/Clash/Primitives/GHC/Word.hs +19/−3
• src/Clash/Primitives/Intel/ClockGen.hs +265/−233
• src/Clash/Primitives/Magic.hs +31/−0
• src/Clash/Primitives/Sized/Signed.hs +5/−3
• src/Clash/Primitives/Sized/ToInteger.hs +57/−3
• src/Clash/Primitives/Sized/Vector.hs +62/−64
• src/Clash/Primitives/Types.hs +29/−16
• src/Clash/Primitives/Util.hs +4/−4
• src/Clash/Primitives/Verification.hs +22/−15
• src/Clash/Primitives/Xilinx/ClockGen.hs +195/−0
• src/Clash/Rewrite/Combinators.hs +1/−1
• src/Clash/Rewrite/Types.hs +8/−0
• src/Clash/Rewrite/Util.hs +29/−15
• src/Clash/Unique.hs +6/−438
• src/Clash/Util.hs +30/−4
• src/Clash/Util/Graph.hs +2/−2
• src/Clash/Util/Interpolate.hs +31/−6
• src/Data/Aeson/Extra.hs +7/−5
• src/Data/List/Extra.hs +2/−0
• src/GHC/BasicTypes/Extra.hs +47/−1
• src/GHC/SrcLoc/Extra.hs +7/−4
• tests/Clash/Tests/Core/TermLiteral.hs +67/−0
• tests/Clash/Tests/Core/TermLiteral/Types.hs +5/−0
• tests/Clash/Tests/Driver/Manifest.hs +3/−1
• tests/Clash/Tests/Netlist/Id.hs +4/−4
• tests/Clash/Tests/Normalize/Transformations.hs +31/−30
• tests/Test/Clash/Rewrite.hs +3/−3
• tests/doctests.hs +7/−0
• tests/unittests.hs +4/−2
• tools/static-files.hs +71/−0

@@ -1,8 +1,147 @@ # Changelog for the Clash project++## 1.8.0++Release highlights:++* Support for GHC 9.2, 9.4, 9.6 and 9.8. While GHC 9.2 is supported, we recommend users to skip this version as there is a severe degradation of error message quality. With this change, Clash now supports GHC versions 8.6 through 9.8.+* Major overhaul of the clocking functionality in `Clash.Xilinx.ClockGen` and `Clash.Intel.ClockGen`, see their respective entries below+* `mealyS` function (and several variations) to make writing state machines using the strict `State` monad easier+* Overhaul of `resetGlitchFilter`, see its respective entries below.++Added:++* `altpllSync` and `alteraPllSync` in `Clash.Intel.ClockGen`. These replace the deprecated functions without the `Sync` suffix. Unlike the old functions, these functions are safe to use and have a reset signal for each output domain that can be used to keep the domain in reset while the clock output stabilizes. All PLL functions now also support multiple clock outputs like the old `alteraPll` did. [#2592](https://github.com/clash-lang/clash-compiler/pull/2592)+*  A new clock type `DiffClock` is introduced to signify a differential clock signal that is passed to the design on two ports in antiphase. This is used by the differential Xilinx clock wizards in `Clash.Xilinx.ClockGen`. [#2592](https://github.com/clash-lang/clash-compiler/pull/2592)+* `Clash.Explicit.Testbench.clockToDiffClock`, to create a differential clock signal in a test bench. It is not suitable for synthesizing a differential output in hardware. [#2592](https://github.com/clash-lang/clash-compiler/pull/2592)+* `resetGlitchFilterWithReset`, which accomplishes the same task as `resetGlitchFilter` in domains with unknown initial values by adding a power-on reset input to reset the glitch filter itself. [#2544](https://github.com/clash-lang/clash-compiler/pull/2544)+* Convenience functions: `noReset`, `andReset`, `orReset` plus their unsafe counterparts [#2539](https://github.com/clash-lang/clash-compiler/pull/2539)+* Convenience constraint aliases: `HasSynchronousReset`, `HasAsynchronousReset`, and `HasDefinedInitialValues` [#2539](https://github.com/clash-lang/clash-compiler/pull/2539)+* `Clash.Prelude.Mealy.mealyS` and `Clash.Explicit.Mealy.mealyS` and their bundled equivalents `mealySB` which make writing state machines using the strict `State` monad easier. The tutorial has also been simplified by using this change. [#2484](https://github.com/clash-lang/clash-compiler/pull/2484)+* An experimental feature allowing clocks to vary their periods over time, called "dynamic clocks". Given that this is an experimental feature, it is not part of the public API. [#2295](https://github.com/clash-lang/clash-compiler/pull/2295)+* The prelude now exports `+>>.` and `.<<+`, which can be used to shift in a bit into a `BitVector` from the left or right respectively - similar to `+>>` and `<<+` for `Vec`s. [#2307](https://github.com/clash-lang/clash-compiler/pull/2307)+* `Clash.DataFiles.tclConnector` and the executable `static-files` in `clash-lib`. They provide the Tcl Connector, a Tcl script that allows Vivado to interact with the metadata generated by Clash (Quartus support will be added later). See `Clash.DataFiles.tclConnector` for further information. More documentation about the Tcl Connector and the Clash<->Tcl API will be made available later. [#2335](https://github.com/clash-lang/clash-compiler/pull/2335)+* Add `BitPack`, `NFDataX` and `ShowX` instances for `Ordering` [#2366](https://github.com/clash-lang/clash-compiler/pull/2366)+* Verilog users can now influence the "precision" part of the generated `timescale` pragma using `-fclash-timescale-precision`. [#2353](https://github.com/clash-lang/clash-compiler/pull/2353)+* Clash now includes blackboxes for `integerToFloat#`, `integerToDouble#` [#2342](https://github.com/clash-lang/clash-compiler/issues/2342)+* Instances `Arbitrary (Erroring a)`, `Arbitrary (Saturating a)`, `Arbitrary (Saturating a)`, and `Arbitrary (Zeroing a)` [#2356](https://github.com/clash-lang/clash-compiler/pull/2356)+* `Clash.Magic.clashSimulation`, a way to differentiate between Clash simulation and generating HDL. [#2473](https://github.com/clash-lang/clash-compiler/pull/2473)+* `Clash.Magic.clashCompileError`: make HDL generation error out with a custom error message. Simulation in Clash will also error when the function is evaluated, including a call stack. HDL generation unfortunately does not include a call stack. [#2399](https://github.com/clash-lang/clash-compiler/pull/2399)+* Added `Clash.XException.MaybeX`, a data structure with smart constructors that can help programmers deal with `XException` values in their blackbox model implementations [#2442](https://github.com/clash-lang/clash-compiler/pull/2442)+*  `Clash.Magic.SimOnly`, A container for data you only want to have around during simulation and is ignored during synthesis. Useful for carrying around things such as: a map of simulation/vcd traces, co-simulation state or meta-data, etc. [#2464](https://github.com/clash-lang/clash-compiler/pull/2464)+* `KnownNat (DomainPeriod dom)` as an implied constraint to `KnownDomain dom`. This reduces the amount of code needed to write - for example - clock speed dependent code. [#2541](https://github.com/clash-lang/clash-compiler/pull/2541)+* `Clash.Annotations.SynthesisAttributes.annotate`: a term level way of annotating signals with synthesis attributes [#2547](https://github.com/clash-lang/clash-compiler/pull/2547)+* `Clash.Annotations.SynthesisAttributes.markDebug`: a way of marking a signals "debug", instructing synthesizers to leave the signal alone and offer debug features [#2547](https://github.com/clash-lang/clash-compiler/pull/2547)+* Add hex and octal BitVector parsing. [#1772](https://github.com/clash-lang/clash-compiler/pull/2505)+* `1 <= n => Foldable1 (Vec n)` instance (`base-4.18+` only) [#2563](https://github.com/clash-lang/clash-compiler/pull/2563)+* You can now use `~PERIOD`, `~ISSYNC`, `~ISINITDEFINED` and `~ACTIVEEDGE` on arguments of type `Clock`, `Reset`, `Enable`,`ClockN` and `DiffClock`. [#2590](https://github.com/clash-lang/clash-compiler/pull/2590)++Removed:++* Deprecated module `Clash.Prelude.BitIndex`: functions have been moved to `Clash.Class.BitPack` [#2555](https://github.com/clash-lang/clash-compiler/pull/2555)+* Deprecated module `Clash.Prelude.BitReduction`: functions have been moved to `Clash.Class.BitPack` [#2555](https://github.com/clash-lang/clash-compiler/pull/2555)+* Deprecated function `Clash.Explicit.Signal.enable`: function has been renamed to `andEnable` [#2555](https://github.com/clash-lang/clash-compiler/pull/2555)+* The module `Clash.Clocks.Deriving` has been removed. [#2592](https://github.com/clash-lang/clash-compiler/pull/2592)++Deprecated:++* `unsafeFromLowPolarity`, `unsafeFromHighPolarity`, `unsafeToLowPolarity`, `unsafeToHighPolarity` have been replaced by `unsafeFromActiveLow`, `unsafeFromActiveHigh`, `unsafeToActiveLow`, `unsafeToActiveHigh`. While former ones will continue to exist, a deprecation warning has been added pointing to the latter ones. [#2540](https://github.com/clash-lang/clash-compiler/pull/2540)+* The functions `altpll` and `alteraPll` in `Clash.Intel.ClockGen` have been deprecated because they are unsafe to use while this is not apparent from the name. The `locked` output signal of these functions is an asynchronous signal which needs to be synchronized before it can be used (something the examples did in fact demonstrate). For the common use case, new functions are available, named `altpllSync` and `alteraPllSync`. These functions are safe. For advanced use cases, the old functionality can be obtained through `unsafeAltpll` and `unsafeAlteraPll`. [#2592](https://github.com/clash-lang/clash-compiler/pull/2592)++Changed:++* The wizards in `Clash.Xilinx.ClockGen` have been completely overhauled. The original functions were unsafe and broken in several ways. See the documentation in `Clash.Xilinx.ClockGen` for how to use the new functions. Significant changes are:+  * `clockWizard` and `clockWizardDifferential` now output a `Clock` and a `Reset` which can be directly used by logic. Previously, it outputted a clock and an asynchronous `locked` signal which first needed to be synchronized before it could be used (hence the old function being unsafe). Additionally, the original `locked` signal was strange: it mistakenly was an `Enable` instead of a `Signal dom Bool` and there was a polarity mismatch between Clash simulation and HDL. The `locked` signal was also not resampled to the output domain in Clash simulation.+  * There are new functions `unsafeClockWizard` and `unsafeClockWizardDifferential` for advanced use cases which directly expose the `locked` output of the wizard.+  * All clock generators now have the option to output multiple clocks from a single instance.+  * `clockWizardDifferential` now gets its input clock as a `DiffClock` type; use `clockToDiffClock` to generate this in your test bench if needed. Previously, the function received two clock inputs, but this generated `create_clock` statements in the top-level SDC file for both phases which is incorrect.+  * A constraint was removed: The _output_ clock domain no longer requires asynchronous resets. This was originally intended to signal that the outgoing lock signal is an asynchronous signal. The constraint does not convey this  information at all and is wrong; it also prevents using synchronous resets in the circuit as recommended by Xilinx. Note that if you use the `unsafe` functions, it is still necessary to synchronize the `locked` output in your design.+  * The port names of the primitives in HDL are now correctly lower case.+  * Add Tcl generation. This moves the responsibility of MMCM component generation from the user to `clashConnector.tcl`, which can be found in [`clash-lib:Clash.DataFiles`](https://hackage.haskell.org/package/clash-lib-1.8.0/docs/Clash-DataFiles.html).+  * The wizards now use the user-provided name as the name of the _instance_ rather than the name of the _IP core_. This change was also done for `Clash.Intel.ClockGen` in Clash v1.2.0 in March 2020, when Clash started generating Intel Qsys files. Before that, the user needed to generate a Qsys component manually. Now, in Clash v1.8.0, we also generate the Tcl for Xilinx wizards. When the user is responsible for creating the IP core, it makes sense to always set the component name to the user-provided value. But when that is also generated by Clash, that is no longer needed. Allowing users to set the instance name instead makes it possible to match on the instance in SDC files and such.+  [#2592](https://github.com/clash-lang/clash-compiler/pull/2592)+* The IP core generators in `Clash.Intel.ClockGen` now declare that their input domain needs to have asynchronous resets (`HasAsynchronousReset`), as the functions react asynchronously to their reset input and thus need to be glitch-free. The functions marked `unsafe` do not have this constraint; instead, the function documentation calls attention to the requirement. [#2592](https://github.com/clash-lang/clash-compiler/pull/2592)+* `resetGlitchFilter` now uses a counter instead of shift register, allowing glitch filtering over much larger periods. [#2374](https://github.com/clash-lang/clash-compiler/pull/2374)+* `resetGlitchFilter` now filters glitches symmetrically, only deasserting the reset after the incoming reset has stabilized. For more information, read [#2374](https://github.com/clash-lang/clash-compiler/pull/2374).+* `resetGlitchFilter` does not support domains with unknown initial values anymore. Its previous behavior could lead to unstable circuits. Domains not supporting initial values should consider using `resetGlitchFilterWithReset` or `holdReset`. The previous behavior can still be attained through the new `unsafeResetGlitchFilter`. [#2544](https://github.com/clash-lang/clash-compiler/pull/2544)+* `fromJustX` now uses `deepErrorX` instead of `errorX`. This adds `NFDataX` constraints to `blockRam` like functions, `asyncRam` and `writeToBiSignal`. [#2113](https://github.com/clash-lang/clash-compiler/pull/2113)+*  All memory functions now use `deepErrorX` for `XException`s. This adds `NFDataX` constraints to `asyncRom`, `asyncRomPow2` and `asyncRom#`. [#2113](https://github.com/clash-lang/clash-compiler/pull/2113)+* Before this release, `scanl1` was re-exported from the Haskell Prelude. Clash's Prelude now exports a `Vec` specialized version. [#2172](https://github.com/clash-lang/clash-compiler/pull/2172)+* When generating (System)Verilog, Clash now sets the default net type to `none`. This means any implicitly declared signal in the design will trigger an error when elaborating the design. [#2174](https://github.com/clash-lang/clash-compiler/pull/2174)+* Blackbox templates no longer have the `outputReg` key, it has been replaced with the more general `outputUsage` which specifies how signals are used in terms of whether writes are++    * continuous (i.e. a concurrent context)+    * procedural non-blocking (i.e. `signal` in a VHDL process)+    * procedural blocking (i.e. `variable` in a VHDL process)++  The `~OUTPUTWIREREG` tag continues to work for backwards compatibility, but there is also a new `~OUTPUTUSAGE` tag which is recommended. In the future, the `~OUTPUTWIREREG` tag may be removed. [#2230](https://github.com/clash-lang/clash-compiler/pull/2230)+* `Clash.Explicit.Testbench.outputVerifier` now takes an additional clock as an argument: the clock used by the circuit under test. If your tests use the same domain for the test circuit and design under test, consider using `Clash.Explicit.Testbench.outputVerifier'`. [#2295](https://github.com/clash-lang/clash-compiler/pull/2295)+* `Clash.Explicit.Signal.veryUnsafeSynchronizer` now accepts either a static clock period or a dynamic one. If you don't use dynamic clocks, convert your calls to use `Left`. [#2295](https://github.com/clash-lang/clash-compiler/pull/2295)+* `SDomainConfiguration` is now a record, easing field access. [#2349](https://github.com/clash-lang/clash-compiler/pull/2349)+*  Generalized the return types of `periodToHz` and `hzToPeriod`. Use a type application (`periodToHz @(Ratio Natural)`, `hzToPeriod @Natural`) to get the old behavior back, in case type errors arise. [#2436](https://github.com/clash-lang/clash-compiler/pull/2436)+* `periodToHz` and `hzToPeriod` now throw an `ErrorCall` with call stack when called with the argument 0 (zero), instead of a `RatioZeroDenominator :: ArithException`. [#2436](https://github.com/clash-lang/clash-compiler/pull/2436)+* `hasX` now needs an `NFDataX` constraint, in addition to an `NFData` one. This API change was made to fix an issue where `hasX` would hide error calls in certain situations, see [#2450](https://github.com/clash-lang/clash-compiler/issues/2450).+* Clock generators now wait at least 100 ns before producing their first tick. This change has been implemented to account for Xilinx's GSR in clock synchronization primitives. This change does not affect Clash simulation. See [#2455](https://github.com/clash-lang/clash-compiler/issues/2455).+* From GHC 9.4.1 onwards the following types: `BiSignalOut`, `Index`, `Signed`, `Unsigned`, `File`, `Ref`, and `SimIO` are all encoded as `newtype` instead of `data` now that [#2511](https://github.com/clash-lang/clash-compiler/pull/2511) is merged. This means you can once again use `Data.Coerce.coerce` to coerce between these types and their underlying representation. [#2535](https://github.com/clash-lang/clash-compiler/pull/2535)+* The `Foldable (Vec n)` instance and `Traversable (Vec n)` instance no longer have the `1 <= n` constraint. `Foldable.{foldr1,foldl1,maximum,minimum}` functions now throw an error at run-/simulation-time, and also at HDL-generation time, for vectors of length zero. [#2563](https://github.com/clash-lang/clash-compiler/pull/2563)+* The `maximum` and `minimum` functions exported by `Clash.Prelude` work on non-empty vectors, instead of the more generic version from `Data.Foldable`. [#2563](https://github.com/clash-lang/clash-compiler/pull/2563)+* `unsafeToReset` and `invertReset` now have a KnownDomain constraint This was done in preparation for [Remove KnownDomain #2589](https://github.com/clash-lang/clash-compiler/pull/2589)++Fixed:++* `altpll` and `alteraPll` in `Clash.Intel.ClockGen` now account for the input domain's `ResetPolarity`. Before this fix, the reset was always interpreted as an active-high signal. [#2592](https://github.com/clash-lang/clash-compiler/pull/2592)+* Fix `alteraPll` `qsys` generation. PR [#2417](https://github.com/clash-lang/clash-compiler/pull/2417) (included in Clash v1.6.5) caused a bug in the generation of the `qsys` file: it generated a spurious extra output clock which was completely unused otherwise. [#2587](https://github.com/clash-lang/clash-compiler/pull/2587)+* Files in `clash-manifest.json` are now (correctly) listed in reverse topological order [#2334](https://github.com/clash-lang/clash-compiler/issues/2334)+* Dependencies in `clash-manifest.json` are now listed in reverse topological ordering [#2325](https://github.com/clash-lang/clash-compiler/issues/2325)+* Clash now renders undefined bits set via `-fclash-force-undefined` correctly [#2360](https://github.com/clash-lang/clash-compiler/issues/2360)+* `resetGen`'s documentation now mentions it is non-synthesizable ([#2375](https://github.com/clash-lang/clash-compiler/issues/2375))+* `trueDualPortBlockRam` now handles undefined values in its input correctly  [#2350](https://github.com/clash-lang/clash-compiler/issues/2350)+* `trueDualPortBlockRam` now correctly handles port enables when clock edges coincide [#2351](https://github.com/clash-lang/clash-compiler/issues/2351)+* `Clash.Primitives.DSL.deconstructProduct` now projects fields out of a product [#2469](https://github.com/clash-lang/clash-compiler/issues/2469)+* BiSignal test does not look through `Annotate` [#2472](https://github.com/clash-lang/clash-compiler/issues/2472)+* Port size not rendered when type has more than one `Annotate` [#2475](https://github.com/clash-lang/clash-compiler/pull/2475)+* Clash now preserves `NOINLINE` of functions being specialized [#2502](https://github.com/clash-lang/clash-compiler/issues/2502)+* When `convertReset` was used with two domains that had a different reset polarity, the polarity of the signal was not changed.+* Functional arguments of primitives cannot have 0-bit results [#2549](https://github.com/clash-lang/clash-compiler/issues/2549)+* If the source reset of `convertReset` is synchronous, a flip-flop in the source domain is inserted to filter glitches from the source reset. [#2573](https://github.com/clash-lang/clash-compiler/pull/2573)+* SystemVerilog backend: Assignment patterns for unpacked arrays now have an index for every element; improves QuestaSim compatibility. [#2595](https://github.com/clash-lang/clash-compiler/pull/2595)+* Name duplication in generated Verilog involving reset synchronizer [#2598](https://github.com/clash-lang/clash-compiler/issues/2598)++Internal added:++* `Clash.Primitives.DSL.instDecl` now accepts `TExpr`s instead of `LitHDL`s as generics/parameters. This allows for VHDL black boxes to use all possible generic types. To ease transition, `litTExpr` has been added to `Clash.Primitives.DSL`. [#2471](https://github.com/clash-lang/clash-compiler/issues/2471)+* `Clash.Core.TermLiteral.deriveTermToData` now works on records [#2270](https://github.com/clash-lang/clash-compiler/pull/2270)+* `Clash.Primitives.getVec` tries to get all elements in a Vector from an expression [#2483](https://github.com/clash-lang/clash-compiler/pull/2483)+* Added `Clash.Primitives.DSL.deconstructMaybe`. This DSL function makes it easy to deconstruct a `Maybe` into its constructor bit and data. This is often useful for primitives taking 'enable' and 'data' signals. [#2202](https://github.com/clash-lang/clash-compiler/pull/2202)+* Added `unsafeToActiveHigh` and `unsafeToActiveLow` to `Clash.Primitives.DSL`. [#2270](https://github.com/clash-lang/clash-compiler/pull/2270)+* Added `TermLiteral` instance for `Either` [#2329](https://github.com/clash-lang/clash-compiler/pull/2329)+* `Clash.Primitives.DSL.declareN`, a companion to `declare` which declares multiple signals in one go. [#2592](https://github.com/clash-lang/clash-compiler/pull/2592)++Internal changes:++* `Clash.Primitives.DSL.boolFromBit` is now polymorphic in its HDL backend. [#2202](https://github.com/clash-lang/clash-compiler/pull/2202)+* `Clash.Primitives.DSL.unsignedFromBitVector` is now polymorphic in its HDL backend. [#2202](https://github.com/clash-lang/clash-compiler/pull/2202)+* `Clash.Primitives.DSL.fromBV` now converts some `BitVector` expression into some type. [#2202](https://github.com/clash-lang/clash-compiler/pull/2202)+* Add `CompDecl` to `Clash.Netlist.Types.Declaration` to accomodate VHDL's `component` declarations.+* Black box functions declare their usage, necessary for implicit netlist usage analysis implemented in [#2230](https://github.com/clash-lang/clash-compiler/pull/2230)+* Added `showsTypePrec` to `TermLiteral` to make `TermLiteral SNat` work as expected. Deriving an instance is now a bit simpler. Instances which previously had to be defined as:++  ```haskell+  instance TermLiteral Bool where+    termToData = $(deriveTermToData ''Bool)+  ```++  can now be defined using:++  ```haskell+  deriveTermLiteral ''Bool+  ```+  [#2329](https://github.com/clash-lang/clash-compiler/pull/2329)+ ## 1.6.6 *Oct 2nd 2023* -* Support Aeson 2.2 [#2578](https://github.com/clash-lang/clash-compiler/pull/2578)-* Drop the snap package [#2439](https://github.com/clash-lang/clash-compiler/pull/2439)+* Support Aeson 2.2+* Dropped the snap package      The Clash snap package has not been a recommended way to use Clash for quite some time, and it is a hassle to support. @@ -63,7 +202,6 @@ Internal change:   * Clash now always generates non-extended identifiers for port names, so that generated names play nicer with different vendor tools. [#2142](https://github.com/clash-lang/clash-compiler/pull/2142)   * Top entity name available in netlist context. Top entity name used in generated name for include files. [#2146](https://github.com/clash-lang/clash-compiler/pull/2146)-  ## 1.6.2 *Feb 25th 2022* Fixed:

@@ -10,9 +10,8 @@  Features of Clash: -  * Strongly typed (like VHDL), yet with a very high degree of type inference,-    enabling both safe and fast prototying using consise descriptions (like-    Verilog).+  * Strongly typed, but with a very high degree of type inference, enabling both+    safe and fast prototyping using concise descriptions.    * Interactive REPL: load your designs in an interpreter and easily test all     your component without needing to setup a test bench.

@@ -1,6 +1,6 @@ Cabal-version:        2.2 Name:                 clash-lib-Version:              1.6.6+Version:              1.8.0 Synopsis:             Clash: a functional hardware description language - As a library Description:   Clash is a functional hardware description language that borrows both its@@ -51,7 +51,7 @@ Maintainer:           QBayLogic B.V. <devops@qbaylogic.com> Copyright:            Copyright © 2012-2016, University of Twente,                                   2016-2019, Myrtle Software Ltd,-                                  2017-2019, QBayLogic B.V., Google Inc.+                                  2017-2023, QBayLogic B.V., Google Inc. Category:             Hardware Build-type:           Simple @@ -61,6 +61,7 @@   src/ClashDebug.h  Data-files:+  data-files/tcl/clashConnector.tcl   prims/common/*.primitives.yaml,   prims/commonverilog/*.primitives.yaml,   prims/verilog/*.primitives.yaml,@@ -84,6 +85,18 @@   default: True   manual: True +flag doctests+  description:+    You can disable testing with doctests using `-f-doctests`.+  default: True+  manual: True++flag workaround-ghc-mmap-crash+  description:+    Only use this flag when hit by GHC bug #19421. See clash-compiler PR #2444.+  default: False+  manual: True+ common common-options   default-language:   Haskell2010   default-extensions: BangPatterns@@ -100,6 +113,7 @@                       InstanceSigs                       KindSignatures                       NoStarIsType+                      PostfixOperators                       ScopedTypeVariables                       StandaloneDeriving                       TupleSections@@ -129,7 +143,7 @@   Build-depends:      aeson                   >= 0.6.2.0  && < 2.3,                       attoparsec-aeson        >= 2.1      && < 2.3,                       aeson-pretty            >= 0.8      && < 0.9,-                      ansi-terminal           >= 0.8.0.0  && < 0.12,+                      ansi-terminal           >= 0.8.0.0  && < 1.1,                       array,                       async                   >= 2.2.0    && < 2.3,                       attoparsec              >= 0.10.4.0 && < 0.15,@@ -137,31 +151,33 @@                       base16-bytestring       >= 0.1.1    && < 1.1,                       binary                  >= 0.8.5    && < 0.11,                       bytestring              >= 0.10.0.2 && < 0.12,-                      clash-prelude           == 1.6.6,+                      clash-prelude           == 1.8.0,                       concurrent-supply       >= 0.1.7    && < 0.2,                       containers              >= 0.5.0.0  && < 0.7,                       cryptohash-sha256       >= 0.11     && < 0.12,                       data-binary-ieee754     >= 0.4.4    && < 0.6,                       data-default            >= 0.7      && < 0.8,-                      deepseq                 >= 1.3.0.2  && < 1.5,+                      deepseq                 >= 1.3.0.2  && < 1.6,                       dlist                   >= 0.8      && < 1.1,                       directory               >= 1.2.0.1  && < 1.4,                       exceptions              >= 0.8.3    && < 0.11.0,                       extra                   >= 1.6.17   && < 1.8,                       filepath                >= 1.3.0.1  && < 1.5,-                      ghc                     >= 8.6.0    && < 9.1,+                      ghc                     >= 8.6.0    && < 9.9,                       ghc-boot-th,                       hashable                >= 1.2.1.0  && < 1.5,                       haskell-src-meta        >= 0.8      && < 0.9,                       hint                    >= 0.7      && < 0.10,-                      interpolate             >= 0.2.0    && < 1.0,+                      infinite-list           ^>= 0.1,                       lens                    >= 4.10     && < 5.3,-                      mtl                     >= 2.1.2    && < 2.3,+                      mtl                     >= 2.1.2    && < 2.4,                       ordered-containers      >= 0.2      && < 0.3,                       prettyprinter           >= 1.2.0.1  && < 1.8,+                      prettyprinter-interp    ^>= 0.2,                       pretty-show             >= 1.9      && < 2.0,                       primitive               >= 0.5.0.1  && < 1.0,-                      template-haskell        >= 2.8.0.0  && < 2.18,+                      string-interpolate      ^>= 0.3,+                      template-haskell        >= 2.8.0.0  && < 2.22,                       temporary               >= 1.2.1    && < 1.4,                       terminal-size           >= 0.3      && < 0.4,                       text                    >= 1.2.2    && < 2.1,@@ -173,8 +189,11 @@                       unordered-containers    >= 0.2.3.3  && < 0.3,                       yaml                    >= 0.11     && < 0.12, +  if impl(ghc < 9.4.0)+    build-depends:+   if impl(ghc >= 9.0.0)-    build-depends:     ghc-bignum >=1.0 && <1.3+    build-depends:     ghc-bignum >=1.0 && <1.4   else     build-depends:     integer-gmp >=1.0 && <1.1 @@ -185,6 +204,7 @@                       Clash.Backend                       Clash.Backend.SystemVerilog                       Clash.Backend.Verilog+                      Clash.Backend.Verilog.Time                       Clash.Backend.VHDL                        Clash.Core.DataCon@@ -212,6 +232,10 @@                       Clash.Core.Var                       Clash.Core.VarEnv +                      Clash.Data.UniqMap++                      Clash.DataFiles+                       Clash.Debug                        Clash.Driver@@ -225,6 +249,7 @@                       Clash.Netlist.BlackBox.Parser                       Clash.Netlist.BlackBox.Types                       Clash.Netlist.BlackBox.Util+                      Clash.Netlist.Expr                       Clash.Netlist.Id                       Clash.Netlist.Id.Common                       Clash.Netlist.Id.Internal@@ -258,14 +283,17 @@                       Clash.Primitives.Types                       Clash.Primitives.Util +                      Clash.Primitives.Annotations.SynthesisAttributes                       Clash.Primitives.GHC.Int                       Clash.Primitives.GHC.Literal                       Clash.Primitives.GHC.Word                       Clash.Primitives.Intel.ClockGen+                      Clash.Primitives.Magic                       Clash.Primitives.Sized.ToInteger                       Clash.Primitives.Sized.Signed                       Clash.Primitives.Sized.Vector                       Clash.Primitives.Verification+                      Clash.Primitives.Xilinx.ClockGen                        Clash.Rewrite.Combinators                       Clash.Rewrite.Types@@ -288,6 +316,9 @@                       -- Used in clash-cores                       Data.Text.Prettyprint.Doc.Extra +                      -- Used in clash-ghc+                      GHC.BasicTypes.Extra+   Other-Modules:      Clash.Annotations.TopEntity.Extra                       Data.IntMap.Extra                       Data.List.Extra@@ -296,7 +327,6 @@                       Data.Primitive.ByteArray.Extra                       Data.Set.Ordered.Extra                       Data.Text.Extra-                      GHC.BasicTypes.Extra                       GHC.SrcLoc.Extra                       Paths_clash_lib @@ -320,12 +350,49 @@   GHC-Options:        -Wall -Wcompat   default-language:   Haskell2010 +executable static-files+  Main-Is:            tools/static-files.hs+  Build-Depends:+    base,+    clash-lib,+    directory,+    docopt                  ^>= 0.7,+    extra,+    filepath+  GHC-Options:        -Wall -Wcompat+  default-language:   Haskell2010+  if impl(ghc >= 9.2.0)+    buildable: False+++test-suite doctests+  type:             exitcode-stdio-1.0+  default-language: Haskell2010+  main-is:          doctests.hs+  ghc-options:      -Wall -Wcompat -threaded+  hs-source-dirs:   tests++  if !flag(doctests)+    buildable: False+  else+    build-depends:+      base,+      clash-lib,+      doctest-parallel >= 0.2 && < 0.4,+      filepath+ test-suite unittests   import:           common-options   type:             exitcode-stdio-1.0   default-language: Haskell2010   main-is:          unittests.hs-  ghc-options:      -Wall -Wcompat -threaded -with-rtsopts=-N+  ghc-options:      -Wall -Wcompat -threaded+  -- Note that multiple -with-rtsopts are not cumulative, so we can't add the+  -- common RTS options in the unconditional GHC-Options+  if flag(workaround-ghc-mmap-crash)+    GHC-Options: "-with-rtsopts=-N -xm20000000"+  else+    GHC-Options: -with-rtsopts=-N   hs-source-dirs:   tests    if !flag(unittests)@@ -352,9 +419,10 @@       lens,       pretty-show,       quickcheck-text,-      tasty         >= 1.2      && < 1.5,+      tasty         >= 1.2      && < 1.6,       tasty-hunit,       tasty-quickcheck,+      tasty-th,       template-haskell,       text,       transformers,@@ -362,6 +430,8 @@    Other-Modules: Clash.Tests.Core.FreeVars                  Clash.Tests.Core.Subst+                 Clash.Tests.Core.TermLiteral+                 Clash.Tests.Core.TermLiteral.Types                  Clash.Tests.Driver.Manifest                  Clash.Tests.Netlist.Id                  Clash.Tests.Util.Interpolate

@@ -0,0 +1,606 @@+# Copyright  :  (C) 2021-2022, QBayLogic B.V.,+#                   2022     , Google Inc.,+# License    :  BSD2 (see the file LICENSE)+# Maintainer :  QBayLogic B.V. <devops@qbaylogic.com>+#+# Script to parse output generated by Clash to use in the synthesis tool.+#+# TODO: More user documentation++package require json++namespace eval clash {+    variable metadata {}+    variable topEntity++    # Set verbosity level. Range is 0-4, where 0 means "silent". Example:+    #     set clash::verbosity 3+    variable verbosity 1++    # Dry run can be enabled by+    #     set clash::dryRun true+    variable dryRun false++    # Invoke with $topEntityDir set to the path where the manifest file of+    # your top entity is. Read all the metadata generated by Tcl: manifests+    # and Tcl interface scripts, for the top entity and its dependencies.+    proc readMetadata topEntityDir {+        variable metadata+        variable topEntity++        # If we are called multiple times, we will remove the results of+        # earlier invocations.+        set metadata [dict create]+        if {[namespace exists tclIface]} {+            namespace delete tclIface+        }++        set topEntity [ParseManifest $topEntityDir true]+        Log 1 "Top entity is $topEntity"+        return+    }++    # Issue "read_vhdl" / "read_verilog" for all HDL files generated by Clash+    proc readHdl {} {+        variable metadata+        variable topEntity++        CheckMetadataExists+        set libs [dict get $metadata $topEntity dependencies]+        lappend libs $topEntity+        foreach lib $libs {+            foreach hdlFile [dict get $metadata $lib hdlFiles] {+                if {[string match {*.vhdl} $hdlFile]} {+                    PerformAction {+                        read_vhdl -library } -var lib { } -var hdlFile+                } elseif {[string match {*.v} $hdlFile]} {+                    PerformAction {+                        read_verilog } -var hdlFile+                } elseif {[string match {*.sv} $hdlFile]} {+                    PerformAction {+                        read_verilog -sv } -var hdlFile+                } else {+                    error "Error: Unknown extension on HDL file $hdlFile"+                }+            }+        }+        return+    }++    # Issue "read_xdc" for all constraint files generated by Clash for the top+    # entity, and all constraint files managed by the Clash<->Tcl API (not just+    # for the top entity, but for all libraries).+    proc readXdc orders {+        variable metadata+        variable topEntity++        CheckMetadataExists+        foreach order $orders {+            if {$order ni {early normal late}} {+                error "Error: readXdc: Invalid order $order"+            }+        }+        unset order++        set early {}+        set normal {}+        set late {}+        foreach tclIface [GetAllTclIfaces {purposes readXdc}] {+            namespace upvar ${tclIface} order order+            lappend $order $tclIface+        }++        if {{early} in $orders} {+            foreach tclIface $early {+                ReadManagedXdc $tclIface+            }+        }+        if {{normal} in $orders} {+            ReadUnmanagedXdc+            foreach tclIface $normal {+                ReadManagedXdc $tclIface+            }+        }+        if {{late} in $orders} {+            foreach tclIface $late {+                ReadManagedXdc $tclIface+            }+        }+        return+    }++    # Invoke all Clash-generated Tcl interfaces that specify a "createIp"+    # purpose, which will call Vivado's "create_ip" with any additional+    # arguments passed to this function (hint: "createIp -dir yourdir" will+    # create the IP in the subdirectory named "yourdir"). Following that, the+    # IP is configured.+    #+    # Also see "createAndReadIp" below; call it or use its code as+    # inspiration. It is suggested to call it like "createAndReadIp -dir ip"+    # so you keep the files in a separate directory named "ip". The directory+    # will need to exist already.+    proc createIp args {+        CheckMetadataExists+        # Identical names means identical IP, only one run needed even if it+        # occurs in multiple HDL directories.+        set seen {}+        foreach tclIface [GetAllTclIfaces {purposes createIp}] {+            namespace upvar ${tclIface} ipName ipName+            if {$ipName in $seen} {+                continue+            }+            PerformAction -var tclIface {::createIp } -var ipName { } \+                    -varexpand args+            LogProc 3 {    } ${tclIface}::createIp+            lappend seen $ipName+        }+        return $seen+    }++    # Convenience method to create the IP in a temporary in-memory project and+    # then read in the results in non-project mode. Finally, targets are+    # created for the IP.+    #+    # NOTE WELL: since this switches into and out of project mode, it should+    # probably be the very first thing you call in setting up the design.+    proc createAndReadIp args {+        CheckMetadataExists+        if {![llength [GetAllTclIfaces {purposes createIp}]]} {+            return+        }+        PerformAction {+            create_project -in_memory+        }+        set ips [createIp {*}$args]+        PerformAction {+            set ipFiles [get_property IP_FILE [get_ips } -var ips {]]+            close_project+            read_ip $ipFiles+            set_property GENERATE_SYNTH_CHECKPOINT false [get_files $ipFiles]+            generate_target {synthesis simulation} [get_ips } -var ips {]+        }+        return+    }++    #---------------------------------------------------------------------------+    # Private definitions+    #---------------------------------------------------------------------------++    proc Log {level msg} {+        variable verbosity++        if {$verbosity >= $level} {+            puts "Clash \[$level\]: $msg"+        }+        return+    }++    proc LogDry {level msg} {+        variable dryRun++        if {$dryRun} {+            puts "Clash \[$level\]: \[DRY-RUN\] $msg"+        } else {+            Log $level $msg+        }+        return+    }++    # Remove leading and trailing lines with just spaces+    proc TrimLines msg {+        return [regsub {^( *\n)*(.*?)\n?( *\n?)*$} $msg {\2}]+    }++    proc GetCommonIndent msg {+        set indent -1+        foreach line [split $msg \n] {+            regexp -indices {^ *} $line blanks+            if {[lindex $blanks 1] == [string length $line] - 1} {+                # Empty line or line of all blanks; ignore+                continue+            }+            set leader [expr {[lindex $blanks 1] - [lindex $blanks 0] + 1}]+            if {$indent < 0 || $leader < $indent} {+                set indent $leader+            }+        }+        if {$indent < 0} {+            return 0+        }+        return $indent+    }++    proc LogProc {level leader procName} {+        Log $level "${leader}proc [namespace tail $procName]\+                {[info args $procName]} \{"+        set body [TrimLines [info body $procName]]+        set outdent [GetCommonIndent $body]+        foreach line [split $body \n] {+            Log $level "$leader    [string range $line $outdent end]"+        }+        Log $level $leader\}+        return+    }++    proc PerformAction args {+        variable dryRun++        set action {}+        set trace {}+        set argsLen [llength $args]+        for {set i 0} {$i < $argsLen} {incr i} {+            set fragment [lindex $args $i]+            if {$fragment ni {-var -varexpand}} {+                set action $action$fragment+                set trace $trace$fragment+                continue+            }+            incr i+            if {$i == $argsLen} {+                error "Error: $fragment requires an argument"+            }+            set varName [lindex $args $i]+            upvar $varName var+            switch $fragment {+                -var {+                    set action "$action\${$varName}"+                    set trace $trace$var+                }+                -varexpand {+                    set action "$action{*}\${$varName}"+                    set trace $trace$var+                }+            }+        }+        set trace [TrimLines $trace]+        set outdent [GetCommonIndent $trace]+        foreach line [split $trace \n] {+            LogDry 2 [string range $line $outdent end]+        }+        if {$dryRun} {+            return+        }+        catch {+            uplevel 1 $action+        } msg opts+        dict incr opts -level+        return {*}$opts $msg+    }++    proc WriteIntVar {def gname name1 _name2 _op} {+        upvar $name1 var+        if {![string is integer -strict $var]} {+            set var $def+            error "Error: $gname: Only integer values are accepted;\+                    reset to default: $def"+        }+        return+    }++    proc WriteBoolVar {def gname name1 _name2 _op} {+        upvar $name1 var+        if {![string is boolean -strict $var]} {+            set var $def+            error "Error: $gname: Only {0 1 false true no yes off on} are\+                    accepted; reset to default: $def"+        }+        return+    }++    proc TraceWrite {varName cmd args} {+        set ns [namespace current]+        set commandPrefix [linsert $args 0 ${ns}::$cmd]+        lappend commandPrefix ${ns}::$varName+        uplevel 1 [list trace remove variable $varName write $commandPrefix]+        uplevel 1 [list trace add variable $varName write $commandPrefix]+        return+    }++    proc CheckMetadataExists {} {+        variable metadata+        if {![dict size $metadata]} {+            error "Error: Please invoke clash::readMetadata first."+        }+        return+    }++    proc GetNsVar {ns varName} {+        if {![llength [uplevel 1 [list info vars ${ns}::$varName]]]} {+            error "Error: $ns doesn't provide \"$varName\"\+                    variable."+        }+        return [uplevel 1 [list set ${ns}::$varName]]+    }++    proc ParseManifest {entityDir withDeps} {+        variable metadata++        set manC [open [file join $entityDir clash-manifest.json] r]+        set manifest [json::json2dict [read $manC]]+        close $manC+        set lib [dict get $manifest top_component name]+        Log 1 "New top component: $lib"+        # Clash sometimes lists files multiple times, process them only once+        set seen {}+        set topConstraintName [file join $entityDir "${lib}.sdc"]+        dict set metadata $lib hdlFiles {}+        dict set metadata $lib constraintFiles {}+        foreach fileEntry [dict get $manifest files] {+            set name [file join $entityDir [dict get $fileEntry name]]+            if {$name in $seen} {+                continue+            }+            lappend seen $name+            if {$name eq $topConstraintName} {+                dict set metadata $lib topConstraintFile $name+            } elseif {+                   [string match {*.vhdl} $name]+                || [string match {*.v} $name]+                || [string match {*.sv} $name]+            } then {+                Log 3 "Adding HDL file: $name"+                dict with metadata $lib {+                    lappend hdlFiles $name+                }+            } elseif {+                   [string match {*.sdc} $name]+                || [string match {*.xdc} $name]+            } then {+                Log 3 "Adding constraint file: $name"+                dict with metadata $lib {+                    lappend constraintFiles $name+                }+            } elseif {[string match {*.clash.tcl} $name]} {+                Log 3 "Adding Clash<->Tcl API file: $name"+                LoadTclIface $lib $name+            }+        }+        RemoveManagedFiles $lib++        if {!$withDeps} {+            return $lib+        }++        set dependencies {}+        foreach dependency [dict get $manifest dependencies transitive] {+            set dependencyDir [file join [file dirname $entityDir] $dependency]+            lappend dependencies [ParseManifest $dependencyDir false]+        }+        dict set metadata $lib dependencies $dependencies+        return $lib+    }++    # Populate a namespace with a Clash-generated Tcl interface.+    # Namespace is clash::tclIface::${lib}::$baseName+    proc LoadTclIface {lib tclIfaceFile} {+        set fileName [file tail $tclIfaceFile]+        # Strip all extensions+        set baseName [string range $fileName 0 [string first . $fileName]-1]+        set tclIface [namespace current]::tclIface::${lib}::$baseName+        # Evaluate script code inside temporary throwaway namespace to+        # separate its code from ours and reduce the chance of accidentally+        # corrupting our code.+        namespace eval tmp {}+        set tmp::tclIfaceFile $tclIfaceFile+        set tmp::tclIface $tclIface+        namespace eval tmp {+            # -notrace is a Vivado specific option inhibiting the printing of+            # the script to stdout+            source -notrace $tclIfaceFile+        }+        if {![namespace exists $tclIface]} {+            error "Error: $tclIfaceFile did not create the requested namespace\+                    specified by the \$tclIface variable. The Tcl script does\+                    not conform to the defined Clash<->Tcl API."+        }+        namespace delete tmp+        VerifyTclIface $tclIface $tclIfaceFile true+        return+    }++    # Verify that the read interface file is strictly something we support.+    proc VerifyTclIface {tclIface tclIfaceFile isRoot} {+        set api [GetNsVar $tclIface api]+        if {$api ne {1}} {+            error "Error: $tclIface doesn't implement an API we support:\+                    api = \"$api\"."+        }+        set purpose [GetNsVar $tclIface scriptPurpose]+        Log 3 "  API level / purpose: $api/$purpose"+        if {$purpose eq {multipleScripts}} {+            if {!$isRoot} {+                error "Error: ${tclIface}::scriptPurpose = \"multipleScripts\",\+                        nested use not allowed."+            }+            if {![namespace exists ${tclIface}::multipleScripts]} {+                error "Error: ${tclIface}::multipleScripts does not exist."+            }+            set children [namespace children ${tclIface}::multipleScripts]+            if {![llength $children]} {+                error "Error: ${tclIface}::multipleScripts doesn't provide any\+                        scripts."+            }+            foreach child $children {+                if {[llength [info vars ${child}::api]]} {+                    error "Error: $child cannot specify api: it is specified by\+                            parent script."+                }+                set ${child}::api $api+                VerifyTclIface $child $tclIfaceFile false+            }++        } elseif {$purpose eq {createIp}} {+            Log 3 "    IP name: [GetNsVar $tclIface ipName]"+            # In Tcl, you can call procedures with a partial name. So an+            # invocation of "createIp" could call "createIpAlt" if+            # "createIp" did not exist. Let's be strict here to prevent+            # confusion: only accept the exact name "createIp".+            if {![llength [info procs ${tclIface}::createIp]]} {+                error "Error: $tclIface doesn't provide \"createIp\"\+                        procedure."+            }+            LogProc 4 {    } ${tclIface}::createIp++        } elseif {$purpose eq {readXdc}} {+            set order [GetNsVar $tclIface order]+            if {$order ni {early normal late}} {+                error "Error: ${tclIface}::order bogus value \"$order\"."+            }+            set usedIn [GetNsVar $tclIface usedIn]+            foreach stage $usedIn {+                if {$stage ni {synthesis implementation}} {+                    error "Error: ${tclIface}::usedIn bogus value \"$stage\"."+                }+            }+            set xdcFile [GetNsVar $tclIface xdcFile]+            # "file join" also correctly handles an absolute $xdcFile+            set resolvedFile [file join [file dirname $tclIfaceFile] $xdcFile]+            # "file isfile" also positively matches a symlink to a regular+            # file+            if {![file isfile $resolvedFile]} {+                error "Error: ${tclIface}::xdcFile = \"$xdcFile\" does not\+                        refer to an existing file."+            }+            set ${tclIface}::xdcFile $resolvedFile+            Log 3 "    Constraint file: $resolvedFile"+            Log 4 "    Order: $order"+            if {[llength [info vars ${tclIface}::scopeRef]]} {+                namespace upvar ${tclIface} scopeRef scopeRef+                Log 4 "    Scoped to ref: $scopeRef"+            }+            Log 4 "    Used in: $usedIn"++        } else {+            error "Error: ${tclIface}::scriptPurpose bogus value \"$purpose\"."+        }+        return+    }++    # Remove constraint files that are managed by a Tcl interface script from+    # the list of constraint files for the library.+    proc RemoveManagedFiles lib {+        variable metadata++        foreach tclIface [GetAllTclIfaces {libs $lib purposes readXdc}] {+            namespace upvar ${tclIface} xdcFile xdcFile+            set constraintFiles [dict get $metadata $lib constraintFiles]+            if {[lsearch -exact $constraintFiles $xdcFile] >= 0} {+                Log 3 "Marking as managed by the Clash<->Tcl API: $xdcFile"+                set filtered [lsearch -all -inline -exact -not \+                        $constraintFiles $xdcFile]+                dict set metadata $lib constraintFiles $filtered+            }+        }+        return+    }++    # Return all the Tcl interface namespaces+    #+    # They can optionally be filtered by specifying a list of libraries to+    # consider, a list of interface names to consider, or a list of script+    # purposes to consider. The sole argument of the function is a dictionary of+    # options, with the possible keys "libs", "ifaces" and "purposes".+    #+    # For example, if these two interfaces exist:+    #   - ::clash::tclIface::libA::ifaceX+    #   - ::clash::tclIface::libB::ifaceX+    #+    # Then "GetAllTclIfaces {libs libA}" would only return the first, but+    # "GetAllTclIfaces {ifaces ifaceX}" would return both since the interface+    # names both match.+    proc GetAllTclIfaces {{opts {}}} {+        if {![namespace exists tclIface]} {+            # There are no scripts+            return+        }++        if {[dict exists $opts libs]} {+            set walkLibs {}+            foreach lib [dict get $opts libs] {+                if {[namespace exists tclIface::$lib]} {+                    lappend walkLibs tclIface::$lib+                }+            }+        } else {+            set walkLibs [namespace children tclIface]+        }+        set tclIfaces {}+        set hasIfaces [dict exists $opts ifaces]+        if {$hasIfaces} {+            set ifaces [dict get $opts ifaces]+        }+        set hasPurposes [dict exists $opts purposes]+        if {$hasPurposes} {+            set purposes [dict get $opts purposes]+        }+        foreach libNs $walkLibs {+            foreach tclIface [namespace children $libNs] {+                if {$hasIfaces && [namespace tail $tclIface] ni $ifaces} {+                    continue+                }+                namespace upvar ${tclIface} scriptPurpose purpose+                if {$purpose ne {multipleScripts}} {+                    if {(!$hasPurposes) || $purpose in $purposes} {+                        lappend tclIfaces $tclIface+                    }+                    continue+                }+                set childIfaces \+                        [namespace children ${tclIface}::multipleScripts]+                foreach childIface $childIfaces {+                    namespace upvar ${childIface} scriptPurpose purpose+                    if {(!$hasPurposes) || $purpose in $purposes} {+                        lappend tclIfaces $childIface+                    }+                }+            }+        }+        return $tclIfaces+    }++    # If Clash generates constraint files without an accompanying tclIface, they+    # fall into two categories. Given $lib as the name of the top component in a+    # library, ${lib}.sdc contains the "create_clock" statements. We only read+    # that for the top entity. All other constraint files are passed to Vivado+    # as-is and should match on unique identifiers in the HDL, such that they+    # can be read for all libraries without worrying about `current_instance` or+    # similar scoping mechanisms.+    proc ReadUnmanagedXdc {} {+        variable metadata+        variable topEntity++        if {[dict exists $metadata $topEntity topConstraintFile]} {+            set topConstraintFile \+                    [dict get $metadata $topEntity topConstraintFile]+            PerformAction {+                read_xdc } -var topConstraintFile+        }+        set libs [dict get $metadata $topEntity dependencies]+        lappend libs $topEntity+        foreach lib $libs {+            set constraintFiles [dict get $metadata $lib constraintFiles]+            foreach constraintFile $constraintFiles {+                PerformAction {+                    read_xdc } -var constraintFile+            }+        }+    }++    proc ReadManagedXdc tclIface {+        namespace upvar $tclIface xdcFile xdcFile usedIn usedIn+        if {[llength [info vars ${tclIface}::scopeRef]]} {+            namespace upvar ${tclIface} scopeRef scopeRef+            set scopeRefArg [list -ref $scopeRef]+        } else {+            set scopeRefArg {}+        }+        PerformAction {+            read_xdc } -varexpand scopeRefArg { } -var xdcFile {+            set_property USED_IN } -var usedIn { [get_files } -var xdcFile {]+        }+        return+    }++    TraceWrite verbosity WriteIntVar 1+    TraceWrite dryRun WriteBoolVar false+}

@@ -3,9 +3,22 @@     kind: Expression     type: |-       veryUnsafeSynchronizer-        :: Int                         -- ARG[0]-        -> Int                         -- ARG[1]-        -> Signal dom1 a               -- ARG[2]+        :: Either Int (Signal dom1 Int) -- ARG[0]+        -> Either Int (Signal dom2 Int) -- ARG[1]+        -> Signal dom1 a                -- ARG[2]         -> Signal dom2 a     template: ~ARG[2]+    workInfo: Never+- BlackBox:+    name: Clash.Explicit.Signal.unsafeSynchronizer+    kind: Expression+    type: |-+      unsafeSynchronizer+        :: ( KnownDomain dom1    -- ARG[0]+           , KnownDomain dom2 )  -- ARG[1]+        => Clock dom1            -- ARG[2]+        -> Clock dom2            -- ARG[3]+        -> Signal dom1 a         -- ARG[4]+        -> Signal dom2 a+    template: ~ARG[4]     workInfo: Never

@@ -1,5 +1,5 @@ - BlackBox:-    name: Clash.Intel.ClockGen.altpll+    name: Clash.Intel.ClockGen.unsafeAltpll     format: Haskell     includes:     - name: altpll@@ -10,7 +10,7 @@     templateFunction: Clash.Primitives.Intel.ClockGen.altpllTF     workInfo: Always - BlackBox:-    name: Clash.Intel.ClockGen.alteraPll+    name: Clash.Intel.ClockGen.unsafeAlteraPll     format: Haskell     includes:     - name: altera_pll

@@ -16,3 +16,9 @@ - Primitive:     name: Clash.Magic.setName     primType: Function+- BlackBox:+    name: Clash.Magic.SimOnly+    kind: Expression+    type: 'SimOnly :: a -> SimOnly a'+    template: ~ERRORO+    workInfo: Constant

@@ -22,8 +22,7 @@ - BlackBox:     name: Clash.XException.deepseqX     kind: Expression-    type: 'deepseqX :: Undefined-      a => a -> b -> b'+    type: 'deepseqX :: NFDataX a => a -> b -> b'     template: ~ARG[2]     workInfo: Never - BlackBox:

@@ -0,0 +1,22 @@+- BlackBox:+    name: Clash.Xilinx.ClockGen.unsafeClockWizard+    kind: Declaration+    format: Haskell+    templateFunction: Clash.Primitives.Xilinx.ClockGen.clockWizardTF+    includes:+      - name: clk_wiz+        extension: clash.tcl+        format: Haskell+        templateFunction: Clash.Primitives.Xilinx.ClockGen.clockWizardTclTF+    workInfo: Always+- BlackBox:+    name: Clash.Xilinx.ClockGen.unsafeClockWizardDifferential+    kind: Declaration+    format: Haskell+    templateFunction: Clash.Primitives.Xilinx.ClockGen.clockWizardDifferentialTF+    includes:+      - name: clk_wiz+        extension: clash.tcl+        format: Haskell+        templateFunction: Clash.Primitives.Xilinx.ClockGen.clockWizardDifferentialTclTF+    workInfo: Always

@@ -18,20 +18,84 @@       Int# -> Int#'     template: ~ARG[0] + ~ARG[1] - BlackBox:+    name: GHC.Prim.plusInt8#+    kind: Expression+    template: ~ARG[0] + ~ARG[1]+- BlackBox:+    name: GHC.Prim.plusInt16#+    kind: Expression+    template: ~ARG[0] + ~ARG[1]+- BlackBox:+    name: GHC.Prim.plusInt32#+    kind: Expression+    template: ~ARG[0] + ~ARG[1]+- BlackBox:+    name: GHC.Prim.plusInt64#+    kind: Expression+    template: ~ARG[0] + ~ARG[1]+- BlackBox:     name: GHC.Prim.-#     kind: Expression     type: '(-#) :: Int# ->       Int# -> Int#'     template: ~ARG[0] - ~ARG[1] - BlackBox:+    name: GHC.Prim.subInt8#+    kind: Expression+    template: ~ARG[0] - ~ARG[1]+- BlackBox:+    name: GHC.Prim.subInt16#+    kind: Expression+    template: ~ARG[0] - ~ARG[1]+- BlackBox:+    name: GHC.Prim.subInt32#+    kind: Expression+    template: ~ARG[0] - ~ARG[1]+- BlackBox:+    name: GHC.Prim.subInt64#+    kind: Expression+    template: ~ARG[0] - ~ARG[1]+- BlackBox:     name: GHC.Prim.plusWord#     kind: Expression     type: 'plusWord# :: Word#       -> Word# -> Word#'     template: ~ARG[0] + ~ARG[1] - BlackBox:+    name: GHC.Prim.plusWord8#+    kind: Expression+    template: ~ARG[0] + ~ARG[1]+- BlackBox:+    name: GHC.Prim.plusWord16#+    kind: Expression+    template: ~ARG[0] + ~ARG[1]+- BlackBox:+    name: GHC.Prim.plusWord32#+    kind: Expression+    template: ~ARG[0] + ~ARG[1]+- BlackBox:+    name: GHC.Prim.plusWord64#+    kind: Expression+    template: ~ARG[0] + ~ARG[1]+- BlackBox:     name: GHC.Prim.minusWord#     kind: Expression     type: 'minusWord# :: Word#       -> Word# -> Word#'+    template: ~ARG[0] - ~ARG[1]+- BlackBox:+    name: GHC.Prim.subWord8#+    kind: Expression+    template: ~ARG[0] - ~ARG[1]+- BlackBox:+    name: GHC.Prim.subWord16#+    kind: Expression+    template: ~ARG[0] - ~ARG[1]+- BlackBox:+    name: GHC.Prim.subWord32#+    kind: Expression+    template: ~ARG[0] - ~ARG[1]+- BlackBox:+    name: GHC.Prim.subWord64#+    kind: Expression     template: ~ARG[0] - ~ARG[1]

@@ -0,0 +1,7 @@+- BlackBox:+    name: GHC.Prim.Panic.absentError+    kind: Expression+    type: 'absentError ::+      Addr# -> a'+    template: ~ERRORO+    workInfo: Constant

@@ -7,6 +7,11 @@     workInfo: Never - Primitive:     name: GHC.TypeNats.someNatVal-    primType: Functions+    primType: Function     type: 'someNatVal :: Natural -> SomeNat'+    workInfo: Never+- Primitive:+    name: GHC.TypeNates.withSomeSNat+    primType: Function+    type: 'withSomeSNat :: forall rep (r :: TYPE rep). Natural -> (forall n. SNat n -> r) -> r'     workInfo: Never

@@ -2,3 +2,17 @@     name: GHC.Types.MkCoercible     primType: Constructor     workInfo: Never+- BlackBox:+    name: GHC.Types.I#+    kind: Expression+    comment: Needed to make the evaluator handle this constructor strictly+    type: 'I# :: Int# -> Int'+    template: ~ARG[0]+    workInfo: Never+- BlackBox:+    name: GHC.Types.W#+    kind: Expression+    comment: Needed to make the evaluator handle this constructor strictly+    type: 'W# :: Word# -> Word'+    template: ~ARG[0]+    workInfo: Never

@@ -29,6 +29,7 @@     name: Clash.Explicit.SimIO.writeReg     kind: Declaration     renderVoid: RenderVoid+    outputUsage: Blocking     template: ~ARG[0] = ~ARG[1]; - BlackBox:     name: Clash.Explicit.SimIO.openFile@@ -51,6 +52,7 @@ - BlackBox:     name: Clash.Explicit.SimIO.getLine     kind: Declaration+    outputUsage: Blocking     template: ~RESULT = $fgets(~ARG[2],~ARG[1]); - BlackBox:     name: Clash.Explicit.SimIO.isEOF@@ -64,10 +66,12 @@ - BlackBox:     name: Clash.Explicit.SimIO.seek     kind: Declaration+    outputUsage: Blocking     template: ~RESULT = $fseek(~ARG[0],~ARG[1],~ARG[2]); - BlackBox:     name: Clash.Explicit.SimIO.rewind     kind: Declaration+    outputUsage: Blocking     template: ~RESULT = $rewind(~ARG[0]); - BlackBox:     name: Clash.Explicit.SimIO.tell

@@ -5,3 +5,7 @@       Enable dom'     template: assign ~RESULT = 1'b1;     workInfo: Always+- BlackBox:+    name: Clash.Explicit.Testbench.clockToDiffClock+    kind: Expression+    template: '{~ARG[1], ~ ~ARG[1]}'

@@ -9,6 +9,6 @@     name: Clash.Signal.Internal.unsafeToReset     kind: Expression     type: 'unsafeToReset ::-      Signal dom Bool -> Reset dom'-    template: ~ARG[0]+      KnownDomain dom => Signal dom Bool -> Reset dom'+    template: ~ARG[1]     workInfo: Never

@@ -1,42 +0,0 @@-- BlackBox:-    name: Clash.Xilinx.ClockGen.clockWizard-    kind: Declaration-    type: |--      clockWizard-        :: ( KnownDomain domIn confIn       -- ARG[0]-           , KnownDomain domOut confOut )   -- ARG[1]-        => SSymbol name                    -- ARG[2]-        -> Clock  pllIn                    -- ARG[3]-        -> Reset pllIn                     -- ARG[4]-        -> (Clock pllOut, Enable pllOut)-    template: |--      // clockWizard begin-      ~NAME[2] ~GENSYM[clockWizard_inst][2]-      (.CLK_IN1  (~ARG[3])-      ,.RESET    (~IF ~ISACTIVEHIGH[0] ~THEN ~ELSE ! ~FI ~ARG[4])-      ,.CLK_OUT1 (~RESULT[1])-      ,.LOCKED   (~RESULT[0]));-      // clockWizard end-    workInfo: Always-- BlackBox:-    name: Clash.Xilinx.ClockGen.clockWizardDifferential-    kind: Declaration-    type: |--      clockWizardDifferential-        :: ( KnownDomain domIn confIn       -- ARG[0]-           , KnownDomain domOut confOut )   -- ARG[1]-        :: SSymbol name                    -- ARG[2]-        -> Clock  pllIn                    -- ARG[3]-        -> Clock  pllIn                    -- ARG[4]-        -> Reset pllIn                     -- ARG[5]-        -> (Clock pllOut, Enable pllOut)-    template: |--      // clockWizardDifferential begin-      ~NAME[2] ~GENSYM[clockWizardDifferential_inst][2]-      (.CLK_IN1_D_clk_n (~ARG[3])-      ,.CLK_IN1_D_clk_n (~ARG[4])-      ,.RESET           (~IF ~ISACTIVEHIGH[0] ~THEN ~ELSE ! ~FI ~ARG[5])-      ,.CLK_OUT1        (~RESULT[1])-      ,.LOCKED          (~RESULT[0]));-      // clockWizardDifferential end-    workInfo: Always

@@ -173,6 +173,14 @@       but fixed-length after synthesis. Use carefully.'     workInfo: Never - BlackBox:+    name: GHC.Num.Integer.integerToInt64#+    kind: Expression+    type: 'integerToInt64#:: Integer -> Int64#'+    template: ~ARG[0]+    warning: 'GHC.Num.Integer.integerToInt64#: Integers are dynamically sized in+      simulation, but fixed-length after synthesis. Use carefully.'+    workInfo: Never+- BlackBox:     name: GHC.Num.Integer.integerToWord64#     comment: only used by 32 bit GHC     kind: Declaration@@ -183,6 +191,14 @@       simulation, but fixed-length after synthesis. Use carefully.'     workInfo: Never - BlackBox:+    name: GHC.Num.Integer.integerFromWord64#+    kind: Declaration+    type: 'integerFromWord64# :: Word64# -> Integer'+    template: assign ~RESULT = $signed(~ARG[0]);+    warning: 'GHC.Num.Integer.integerFromWord64#: Integers are dynamically sized in+      simulation, but fixed-length after synthesis. Use carefully.'+    workInfo: Never+- BlackBox:     name: GHC.Num.Integer.integerBit#     kind: Expression     type: 'integerBit# ::@@ -279,3 +295,12 @@     template: ~ARG[0] / ~ARG[1]     warning: 'GHC.Num.Integer.integerQuot: Integers are dynamically sized in simulation,       but fixed-length after synthesis. Use carefully.'+- BlackBox:+    name: GHC.Num.Integer.$wintegerFromInt64#+    kind: Declaration+    type: '$wintegerFromInt64# :: Int64# -> Int#'+    template: |-+      // wintegerFromInt64 begin+      assign ~RESULT = ~ARG[0];+      // wintegerFromInt64 end+    workInfo: Never

@@ -432,3 +432,619 @@     type: 'quotWord# :: Word#       -> Word# -> Word#'     template: ~ARG[0] / ~ARG[1]+- BlackBox:+    name: GHC.Prim.int8ToInt#+    kind: Declaration+    template: |-+      // int8ToInt begin+      assign ~RESULT = ~ARG[0];+      // int8ToInt end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.intToInt8#+    kind: Declaration+    template: |-+      // intToInt8 begin+      assign ~RESULT = ~ARG[0];+      // intToInt8 end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.negateInt8#+    kind: Expression+    template: -(~ARG[0])+- BlackBox:+    name: GHC.Prim.timesInt8#+    kind: Expression+    template: ~ARG[0] * ~ARG[1]+- BlackBox:+    name: GHC.Prim.quotInt8#+    kind: Expression+    template: ~ARG[0] / ~ARG[1]+- BlackBox:+    name: GHC.Prim.remInt8#+    kind: Expression+    template: ~ARG[0] % ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedShiftLInt8#+    kind: Expression+    template: ~ARG[0] <<< ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedShiftRAInt8#+    kind: Expression+    template: ~ARG[0] >>> ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedShiftRLInt8#+    kind: Expression+    template: ~ARG[0] >> ~ARG[1]+- BlackBox:+    name: GHC.Prim.int8ToWord8#+    kind: Expression+    template: $unsigned(~ARG[0])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqInt8#+    kind: Expression+    template: "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.geInt8#+    kind: Expression+    template: "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.gtInt8#+    kind: Expression+    template: "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.leInt8#+    kind: Expression+    template: "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.ltInt8#+    kind: Expression+    template: "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.neInt8#+    kind: Expression+    template: "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.word8ToWord#+    kind: Declaration+    template: |-+      // word8ToWord begin+      assign ~RESULT = ~ARG[0];+      // word8ToWord end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.wordToWord8#+    kind: Declaration+    template: |-+      // wordToWord8 begin+      assign ~RESULT = ~ARG[0];+      // wordToWord8 end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.timesWord8#+    kind: Expression+    template: ~ARG[0] * ~ARG[1]+- BlackBox:+    name: GHC.Prim.quotWord8#+    kind: Expression+    template: ~ARG[0] / ~ARG[1]+- BlackBox:+    name: GHC.Prim.remWord8#+    kind: Expression+    template: ~ARG[0] % ~ARG[1]+- BlackBox:+    name: GHC.Prim.andWord8#+    kind: Expression+    template: ~ARG[0] & ~ARG[1]+- BlackBox:+    name: GHC.Prim.orWord8#+    kind: Expression+    template: ~ARG[0] | ~ARG[1]+- BlackBox:+    name: GHC.Prim.xorWord8#+    kind: Expression+    template: ~ARG[0] ^ ~ARG[1]+- BlackBox:+    name: GHC.Prim.notWord8#+    kind: Expression+    template: ~ ~ARG[0]+- BlackBox:+    name: GHC.Prim.uncheckedShiftLWord8#+    kind: Expression+    template: ~ARG[0] << ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedShiftRLWord8#+    kind: Expression+    template: ~ARG[0] >> ~ARG[1]+- BlackBox:+    name: GHC.Prim.word8ToInt8#+    kind: Expression+    template: $signed(~ARG[0])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqWord8#+    kind: Expression+    template: "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.geWord8#+    kind: Expression+    template: "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.gtWord8#+    kind: Expression+    template: "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.leWord8#+    kind: Expression+    template: "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.ltWord8#+    kind: Expression+    template: "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.neWord8#+    kind: Expression+    template: "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.int16ToInt#+    kind: Declaration+    template: |-+      // int16ToInt begin+      assign ~RESULT = ~ARG[0];+      // int16ToInt end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.intToInt16#+    kind: Declaration+    template: |-+      // intToInt16 begin+      assign ~RESULT = ~ARG[0];+      // intToInt16 end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.negateInt16#+    kind: Expression+    template: -(~ARG[0])+- BlackBox:+    name: GHC.Prim.timesInt16#+    kind: Expression+    template: ~ARG[0] * ~ARG[1]+- BlackBox:+    name: GHC.Prim.quotInt16#+    kind: Expression+    template: ~ARG[0] / ~ARG[1]+- BlackBox:+    name: GHC.Prim.remInt16#+    kind: Expression+    template: ~ARG[0] % ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedShiftLInt16#+    kind: Expression+    template: ~ARG[0] <<< ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedShiftRAInt16#+    kind: Expression+    template: ~ARG[0] >>> ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedShiftRLInt16#+    kind: Expression+    template: ~ARG[0] >> ~ARG[1]+- BlackBox:+    name: GHC.Prim.int16ToWord16#+    kind: Expression+    template: $unsigned(~ARG[0])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqInt16#+    kind: Expression+    template: "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.geInt16#+    kind: Expression+    template: "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.gtInt16#+    kind: Expression+    template: "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.leInt16#+    kind: Expression+    template: "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.ltInt16#+    kind: Expression+    template: "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.neInt16#+    kind: Expression+    template: "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.word16ToWord#+    kind: Declaration+    template: |-+      // word16ToWord begin+      assign ~RESULT = ~ARG[0];+      // word16ToWord end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.wordToWord16#+    kind: Declaration+    template: |-+      // wordToWord16 begin+      assign ~RESULT = ~ARG[0];+      // wordToWord16 end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.timesWord16#+    kind: Expression+    template: ~ARG[0] * ~ARG[1]+- BlackBox:+    name: GHC.Prim.quotWord16#+    kind: Expression+    template: ~ARG[0] / ~ARG[1]+- BlackBox:+    name: GHC.Prim.remWord16#+    kind: Expression+    template: ~ARG[0] % ~ARG[1]+- BlackBox:+    name: GHC.Prim.andWord16#+    kind: Expression+    template: ~ARG[0] & ~ARG[1]+- BlackBox:+    name: GHC.Prim.orWord16#+    kind: Expression+    template: ~ARG[0] | ~ARG[1]+- BlackBox:+    name: GHC.Prim.xorWord16#+    kind: Expression+    template: ~ARG[0] ^ ~ARG[1]+- BlackBox:+    name: GHC.Prim.notWord16#+    kind: Expression+    template: ~ ~ARG[0]+- BlackBox:+    name: GHC.Prim.uncheckedShiftLWord16#+    kind: Expression+    template: ~ARG[0] << ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedShiftRLWord16#+    kind: Expression+    template: ~ARG[0] >> ~ARG[1]+- BlackBox:+    name: GHC.Prim.word16ToInt16#+    kind: Expression+    template: $signed(~ARG[0])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqWord16#+    kind: Expression+    template: "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.geWord16#+    kind: Expression+    template: "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.gtWord16#+    kind: Expression+    template: "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.leWord16#+    kind: Expression+    template: "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.ltWord16#+    kind: Expression+    template: "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.neWord16#+    kind: Expression+    template: "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.int32ToInt#+    kind: Declaration+    template: |-+      // int32ToInt begin+      assign ~RESULT = ~ARG[0];+      // int32ToInt end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.intToInt32#+    kind: Declaration+    template: |-+      // intToInt32 begin+      assign ~RESULT = ~ARG[0];+      // intToInt32 end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.negateInt32#+    kind: Expression+    template: -(~ARG[0])+- BlackBox:+    name: GHC.Prim.timesInt32#+    kind: Expression+    template: ~ARG[0] * ~ARG[1]+- BlackBox:+    name: GHC.Prim.quotInt32#+    kind: Expression+    template: ~ARG[0] / ~ARG[1]+- BlackBox:+    name: GHC.Prim.remInt32#+    kind: Expression+    template: ~ARG[0] % ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedShiftLInt32#+    kind: Expression+    template: ~ARG[0] <<< ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedShiftRAInt32#+    kind: Expression+    template: ~ARG[0] >>> ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedShiftRLInt32#+    kind: Expression+    template: ~ARG[0] >> ~ARG[1]+- BlackBox:+    name: GHC.Prim.int32ToWord32#+    kind: Expression+    template: $unsigned(~ARG[0])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqInt32#+    kind: Expression+    template: "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.geInt32#+    kind: Expression+    template: "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.gtInt32#+    kind: Expression+    template: "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.leInt32#+    kind: Expression+    template: "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.ltInt32#+    kind: Expression+    template: "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.neInt32#+    kind: Expression+    template: "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.word32ToWord#+    kind: Declaration+    template: |-+      // word32ToWord begin+      assign ~RESULT = ~ARG[0];+      // word32ToWord end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.wordToWord32#+    kind: Declaration+    template: |-+      // wordToWord32 begin+      assign ~RESULT = ~ARG[0];+      // wordToWord32 end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.timesWord32#+    kind: Expression+    template: ~ARG[0] * ~ARG[1]+- BlackBox:+    name: GHC.Prim.quotWord32#+    kind: Expression+    template: ~ARG[0] / ~ARG[1]+- BlackBox:+    name: GHC.Prim.remWord32#+    kind: Expression+    template: ~ARG[0] % ~ARG[1]+- BlackBox:+    name: GHC.Prim.andWord32#+    kind: Expression+    template: ~ARG[0] & ~ARG[1]+- BlackBox:+    name: GHC.Prim.orWord32#+    kind: Expression+    template: ~ARG[0] | ~ARG[1]+- BlackBox:+    name: GHC.Prim.xorWord32#+    kind: Expression+    template: ~ARG[0] ^ ~ARG[1]+- BlackBox:+    name: GHC.Prim.notWord32#+    kind: Expression+    template: ~ ~ARG[0]+- BlackBox:+    name: GHC.Prim.uncheckedShiftLWord32#+    kind: Expression+    template: ~ARG[0] << ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedShiftRLWord32#+    kind: Expression+    template: ~ARG[0] >> ~ARG[1]+- BlackBox:+    name: GHC.Prim.word32ToInt32#+    kind: Expression+    template: $signed(~ARG[0])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqWord32#+    kind: Expression+    template: "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.geWord32#+    kind: Expression+    template: "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.gtWord32#+    kind: Expression+    template: "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.leWord32#+    kind: Expression+    template: "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.ltWord32#+    kind: Expression+    template: "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.neWord32#+    kind: Expression+    template: "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.int64ToInt#+    kind: Declaration+    template: |-+      // int64ToInt begin+      assign ~RESULT = ~ARG[0];+      // int64ToInt end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.intToInt64#+    kind: Declaration+    template: |-+      // intToInt64 begin+      assign ~RESULT = ~ARG[0];+      // intToInt64 end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.negateInt64#+    kind: Expression+    template: -(~ARG[0])+- BlackBox:+    name: GHC.Prim.timesInt64#+    kind: Expression+    template: ~ARG[0] * ~ARG[1]+- BlackBox:+    name: GHC.Prim.quotInt64#+    kind: Expression+    template: ~ARG[0] / ~ARG[1]+- BlackBox:+    name: GHC.Prim.remInt64#+    kind: Expression+    template: ~ARG[0] % ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedIShiftL64#+    kind: Expression+    template: ~ARG[0] <<< ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedIShiftRA64#+    kind: Expression+    template: ~ARG[0] >>> ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedIShiftRL64#+    kind: Expression+    template: ~ARG[0] >> ~ARG[1]+- BlackBox:+    name: GHC.Prim.int64ToWord64#+    kind: Expression+    template: $unsigned(~ARG[0])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqInt64#+    kind: Expression+    template: "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.geInt64#+    kind: Expression+    template: "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.gtInt64#+    kind: Expression+    template: "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.leInt64#+    kind: Expression+    template: "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.ltInt64#+    kind: Expression+    template: "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.neInt64#+    kind: Expression+    template: "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.word64ToWord#+    kind: Declaration+    template: |-+      // word64ToWord begin+      assign ~RESULT = ~ARG[0];+      // word64ToWord end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.wordToWord64#+    kind: Declaration+    template: |-+      // wordToWord64 begin+      assign ~RESULT = ~ARG[0];+      // wordToWord64 end+    workInfo: Never+- BlackBox:+    name: GHC.Prim.timesWord64#+    kind: Expression+    template: ~ARG[0] * ~ARG[1]+- BlackBox:+    name: GHC.Prim.quotWord64#+    kind: Expression+    template: ~ARG[0] / ~ARG[1]+- BlackBox:+    name: GHC.Prim.remWord64#+    kind: Expression+    template: ~ARG[0] % ~ARG[1]+- BlackBox:+    name: GHC.Prim.and64#+    kind: Expression+    template: ~ARG[0] & ~ARG[1]+- BlackBox:+    name: GHC.Prim.or64#+    kind: Expression+    template: ~ARG[0] | ~ARG[1]+- BlackBox:+    name: GHC.Prim.xor64#+    kind: Expression+    template: ~ARG[0] ^ ~ARG[1]+- BlackBox:+    name: GHC.Prim.not64#+    kind: Expression+    template: ~ ~ARG[0]+- BlackBox:+    name: GHC.Prim.uncheckedShiftL64#+    kind: Expression+    template: ~ARG[0] << ~ARG[1]+- BlackBox:+    name: GHC.Prim.uncheckedShiftRL64#+    kind: Expression+    template: ~ARG[0] >> ~ARG[1]+- BlackBox:+    name: GHC.Prim.word64ToInt64#+    kind: Expression+    template: $signed(~ARG[0])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqWord64#+    kind: Expression+    template: "(~ARG[0] == ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.geWord64#+    kind: Expression+    template: "(~ARG[0] >= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.gtWord64#+    kind: Expression+    template: "(~ARG[0] > ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.leWord64#+    kind: Expression+    template: "(~ARG[0] <= ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.ltWord64#+    kind: Expression+    template: "(~ARG[0] < ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"+- BlackBox:+    name: GHC.Prim.neWord64#+    kind: Expression+    template: "(~ARG[0] != ~ARG[1]) ? ~SIZE[~TYPO]'sd1 : ~SIZE[~TYPO]'sd0"

@@ -5,7 +5,7 @@       blockRam#         :: ( KnownDomain dom        ARG[0]            , HasCallStack  --       ARG[1]-           , Undefined a ) --       ARG[2]+           , NFDataX a )   --       ARG[2]         => Clock dom       -- clk,  ARG[3]         -> Enable dom      -- en,   ARG[4]         -> Vec n a         -- init, ARG[5]@@ -50,7 +50,7 @@       blockRamU#         :: ( KnownDomain dom        ARG[0]            , HasCallStack  --       ARG[1]-           , Undefined a ) --       ARG[2]+           , NFDataX a )   --       ARG[2]         => Clock dom       -- clk,  ARG[3]         -> Enable dom      -- en,   ARG[4]         -> SNat n          -- len,  ARG[5]@@ -92,7 +92,7 @@       blockRam1#         :: ( KnownDomain dom        ARG[0]            , HasCallStack  --       ARG[1]-           , Undefined a ) --       ARG[2]+           , NFDataX a )   --       ARG[2]         => Clock dom       -- clk,  ARG[3]         -> Enable dom      -- en,   ARG[4]         -> SNat n          -- len,  ARG[5]@@ -131,60 +131,3 @@       end~FI       assign ~RESULT = ~FROMBV[~SYM[2]][~TYP[10]];       // blockRam1 end-- BlackBox:-    name: Clash.Explicit.BlockRam.trueDualPortBlockRam#-    kind: Declaration-    type: |--      trueDualPortBlockRam# ::-        forall nAddrs domA domB a .-        ( HasCallStack           ~ARG[0]-        , KnownNat nAddrs        ~ARG[1]-        , KnownDomain domA       ~ARG[2]-        , KnownDomain domB       ~ARG[3]-        , NFDataX a              ~ARG[4]-        ) =>--        Clock domA ->                   ~ARG[5]-        Signal domA Bool ->             ~ARG[6]-        Signal domA Bool ->             ~ARG[7]-        Signal domA (Index nAddrs) ->   ~ARG[8]-        Signal domA a ->                ~ARG[9]--        Clock domB ->                   ~ARG[10]-        Signal domB Bool ->             ~ARG[11]-        Signal domB Bool ->             ~ARG[12]-        Signal domB (Index nAddrs) ->   ~ARG[13]-        Signal domB a ->                ~ARG[14]-        (Signal domA a, Signal domB a)-    template: |--      // trueDualPortBlockRam begin-      // Shared memory-      logic [~SIZE[~TYP[9]]-1:0] ~GENSYM[mem][0] [~LIT[1]-1:0];--      ~SIGD[~GENSYM[data_slow][1]][9];-      ~SIGD[~GENSYM[data_fast][2]][14];--      // Port A-      always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[5]) begin-          if(~ARG[6]) begin-              ~SYM[1] <= ~SYM[0][~IF~SIZE[~TYP[8]]~THEN~ARG[8]~ELSE0~FI];-              if(~ARG[7]) begin-                  ~SYM[1] <= ~ARG[9];-                  ~SYM[0][~IF~SIZE[~TYP[8]]~THEN~ARG[8]~ELSE0~FI] <= ~ARG[9];-              end-          end-      end--      // Port B-      always @(~IF~ACTIVEEDGE[Rising][3]~THENposedge~ELSEnegedge~FI ~ARG[10]) begin-          if(~ARG[11]) begin-              ~SYM[2] <= ~SYM[0][~IF~SIZE[~TYP[13]]~THEN~ARG[13]~ELSE0~FI];-              if(~ARG[12]) begin-                  ~SYM[2] <= ~ARG[14];-                  ~SYM[0][~IF~SIZE[~TYP[13]]~THEN~ARG[13]~ELSE0~FI] <= ~ARG[14];-              end-          end-      end--      assign ~RESULT = {~SYM[1], ~SYM[2]};-      // end trueDualPortBlockRam

@@ -4,7 +4,7 @@     type: |-       ddrIn# :: forall a slow fast n pFast gated synchronous.                  ( HasCallStack          -- ARG[0]-                 , Undefined a           -- ARG[1]+                 , NFDataX a             -- ARG[1]                  , KnownConfi~ fast domf -- ARG[2]                  , KnownConfi~ slow doms -- ARG[3]               => Clock slow              -- ARG[4], clk@@ -47,9 +47,10 @@ - BlackBox:     name: Clash.Explicit.DDR.ddrOut#     kind: Declaration+    outputUsage: Blocking     type: |--      ddrOut# :: ( HasCallStack               -- ARG[0]-                  , Undefined a                -- ARG[1]+      ddrOut# :: ( HasCallStack                -- ARG[0]+                  , NFDataX a                  -- ARG[1]                   , KnownConfi~ fast domf      -- ARG[2]                   , KnownConfi~ slow doms      -- ARG[3]                => Clock slow                   -- ARG[4]

@@ -4,7 +4,7 @@     type: |-       rom# :: ( KnownDomain dom        ARG[0]                , KnownNat n    --       ARG[1]-               , Undefined a ) --       ARG[2]+               , NFDataX a )   --       ARG[2]             => Clock dom       -- clk,  ARG[3]             => Enable dom      -- en,   ARG[4]             -> Vec n a         -- init, ARG[5]

@@ -53,66 +53,4 @@       // pragma translate_on       assign ~RESULT = ~ARG[7];       // assertBitVector end-- BlackBox:-    name: Clash.Explicit.Testbench.tbClockGen-    kind: Declaration-    type: |--      tbClockGen-        :: KnownDomain dom     -- ARG[0]-        => Signal dom Bool      -- ARG[1]-        -> Clock dom-    template: |--      // tbClockGen begin-      // pragma translate_off-      // 1 = 0.1ps-      localparam ~GENSYM[half_period][0] = (~PERIOD[0]0 / 2);-      always begin-        ~RESULT = ~IF~ACTIVEEDGE[Rising][0]~THEN 0 ~ELSE 1 ~FI;-        `ifndef VERILATOR-        #~LONGESTPERIOD0 forever begin-          if (~ ~ARG[1]) begin-            $finish;-          end-          ~RESULT = ~ ~RESULT;-          #~SYM[0];-          ~RESULT = ~ ~RESULT;-          #~SYM[0];-        end-        `else-        ~RESULT = $c("this->~GENSYM[tb_clock_gen][1](",~SYM[0],",~IF~ACTIVEEDGE[Rising][0]~THENtrue~ELSEfalse~FI,",(~ ~ARG[1]),")");-        `endif-      end -      `ifdef VERILATOR-        `systemc_interface-        CData ~SYM[1](vluint32_t half_period, bool active_rising, bool result_rec) {-          static vluint32_t init_wait = ~LONGESTPERIOD0;-          static vluint32_t to_wait = 0;-          static CData clock = active_rising ? 0 : 1;--          if(init_wait == 0) {-            if(result_rec) {-              std::exit(0);-            }-            else {-              if(to_wait == 0) {-                to_wait = half_period - 1;-                clock = clock == 0 ? 1 : 0;-              }-              else {-                to_wait = to_wait - 1;-              }-            }-          }-          else {-            init_wait = init_wait - 1;-          }--          return clock;-        }-        `verilog-      `endif-      // pragma translate_on-      // tbClockGen end-    warning: Clash.Signal.Internal.tbClockGen is not synthesizable!-    workInfo: Always

@@ -2,14 +2,16 @@     name: Clash.Prelude.ROM.asyncRom#     kind: Declaration     type: |--      asyncRom# :: KnownNat n -- ^ ARG[0]-                 => Vec n a    -- ^ ARG[1]-                 -> Int        -- ^ ARG[2]-                 -> a+      asyncRom#+        :: ( KnownNat n  -- ARG[0]+           , NFDataX a)  -- ARG[1]+        => Vec n a       -- ARG[2]+        -> Int           -- ARG[3]+        -> a     template: |-       // asyncRom begin-      ~SIGD[~GENSYM[ROM][0]][1];-      assign ~SYM[0] = ~CONST[1];+      ~SIGD[~GENSYM[ROM][0]][2];+      assign ~SYM[0] = ~CONST[2]; -      assign ~RESULT = ~FROMBV[~SYM[0][\~ARG[2]\]][~TYPO];+      assign ~RESULT = ~FROMBV[~SYM[0][\~ARG[3]\]][~TYPO];       // asyncRom end

@@ -1,10 +1,11 @@ - BlackBox:     name: Clash.Signal.Internal.delay#     kind: Declaration+    outputUsage: NonBlocking     type: |-       delay#         :: ( KnownDomain dom        -- ARG[0]-           , Undefined a )          -- ARG[1]+           , NFDataX a )            -- ARG[1]         => Clock dom                -- ARG[2]         -> Enable dom               -- ARG[3]         -> a                        -- ARG[4]@@ -28,6 +29,7 @@ - BlackBox:     name: Clash.Signal.Internal.asyncRegister#     kind: Declaration+    outputUsage: NonBlocking     type: |-       asyncRegister#         :: ( KnownDomain dom        -- ARG[0]@@ -56,10 +58,11 @@ - BlackBox:     name: Clash.Signal.Internal.register#     kind: Declaration+    outputUsage: NonBlocking     type: |-       register#         :: ( KnownDomain dom        -- ARG[0]-           , Undefined a )          -- ARG[1]+           , NFDataX a )            -- ARG[1]         => Clock dom                -- ARG[2]         -> Reset dom                -- ARG[3]         -> Enable dom               -- ARG[4]@@ -82,14 +85,16 @@       end       // register end - BlackBox:-    name: Clash.Signal.Internal.clockGen+    name: Clash.Signal.Internal.tbClockGen     kind: Declaration+    outputUsage: Blocking     type: |--      clockGen+      tbClockGen         :: KnownDomain dom     -- ARG[0]-        => Clock dom+        => Signal dom Bool     -- ARG[1]+        -> Clock dom     template: |--      // clockGen begin+      // tbClockGen begin       // pragma translate_off       // 1 = 0.1ps       localparam ~GENSYM[half_period][0] = (~PERIOD[0]0 / 2);@@ -97,30 +102,40 @@         ~RESULT = ~IF~ACTIVEEDGE[Rising][0]~THEN 0 ~ELSE 1 ~FI;         `ifndef VERILATOR         #~LONGESTPERIOD0 forever begin+          ~IF~ISACTIVEENABLE[1]~THEN+          if (~ ~ARG[1]) begin+            $finish;+          end+          ~ELSE~FI           ~RESULT = ~ ~RESULT;           #~SYM[0];           ~RESULT = ~ ~RESULT;           #~SYM[0];         end         `else-        ~RESULT = $c("this->~GENSYM[tb_clock_gen][1](",~SYM[0],",~IF~ACTIVEEDGE[Rising][0]~THENtrue~ELSEfalse~FI)");+        ~RESULT = $c("this->~GENSYM[tb_clock_gen][1](",~SYM[0],",~IF~ACTIVEEDGE[Rising][0]~THENtrue~ELSEfalse~FI,",(~ ~ARG[1]),")");         `endif       end        `ifdef VERILATOR         `systemc_interface-        CData ~SYM[1](vluint32_t half_period, bool active_rising) {+        CData ~SYM[1](vluint32_t half_period, bool active_rising, bool result_rec) {           static vluint32_t init_wait = ~LONGESTPERIOD0;           static vluint32_t to_wait = 0;           static CData clock = active_rising ? 0 : 1;            if(init_wait == 0) {-            if(to_wait == 0) {-              to_wait = half_period - 1;-              clock = clock == 0 ? 1 : 0;+            if(result_rec) {+              std::exit(0);             }             else {-              to_wait = to_wait - 1;+              if(to_wait == 0) {+                to_wait = half_period - 1;+                clock = clock == 0 ? 1 : 0;+              }+              else {+                to_wait = to_wait - 1;+              }             }           }           else {@@ -131,14 +146,50 @@         }         `verilog       `endif+      // pragma translate_on+      // tbClockGen end+    warning: Clash.Signal.Internal.tbClockGen is not synthesizable!+    workInfo: Always+- BlackBox:+    name: Clash.Signal.Internal.tbDynamicClockGen+    kind: Declaration+    outputUsage: Blocking+    type: |-+      tbDynamicClockGen+        :: KnownDomain dom     -- ARG[0]+        -> Signal dom Natural  -- ARG[1]+        -> Signal dom Bool     -- ARG[2]+        => Clock dom+    template: |-+      // tbDynamicClockGen begin+      // pragma translate_off+      // 1 = 0.1ps+      time ~GENSYM[half_period][0];+      always begin+        ~RESULT = ~IF~ACTIVEEDGE[Rising][0]~THEN 0 ~ELSE 1 ~FI;+        #~LONGESTPERIOD0 forever begin+          ~IF~ISACTIVEENABLE[2]~THEN+          if (~ ~ARG[2]) begin+            $finish;+          end+          ~ELSE~FI+          // 1 = 0.1ps+          ~SYM[0] = (~VAR[periods][1] / 2); +          ~RESULT = ~ ~RESULT;+          #(~SYM[0] * 0.01);+          ~RESULT = ~ ~RESULT;+          #(~SYM[0] * 0.01);+        end+      end       // pragma translate_on-      // clockGen end-    warning: Clash.Signal.Internal.clockGen is not synthesizable!+      // tbDynamicClockGen end+    warning: Clash.Signal.Internal.tbDynamicClockGen is not synthesizable!     workInfo: Always - BlackBox:     name: Clash.Signal.Internal.resetGenN     kind: Declaration+    outputUsage: Blocking     type: 'resetGenN :: (KnownDomain       dom, 1 <= n) => SNat n -> Reset dom'     template: |-@@ -180,4 +231,5 @@       `endif       // pragma translate_on       // resetGen end+    warning: Clash.Signal.Internal.resetGenN can not be synthesized to hardware!     workInfo: Always

@@ -1,6 +1,7 @@ - BlackBox:     name: Clash.Sized.Internal.BitVector.replaceBit#     kind: Declaration+    outputUsage: Blocking     type: |-       replaceBit# :: KnownNat n  -- ARG[0]                    => BitVector n -- ARG[1]@@ -17,6 +18,7 @@ - BlackBox:     name: Clash.Sized.Internal.BitVector.setSlice#     kind: Declaration+    outputUsage: Blocking     type: |-       setSlice# :: SNat (m + 1 + i)                  -> BitVector (m + 1 + i) -- ARG[1]

@@ -241,6 +241,7 @@ - BlackBox:     name: Clash.Sized.Vector.replace_int     kind: Declaration+    outputUsage: Blocking     type: 'replace_int ::       KnownNat n => Vec n a -> Int -> a -> Vec n a'     template: |-

@@ -5,12 +5,24 @@       Int -> Int'     template: |-       // divInt begin-      // divide (rounds towards zero)-      ~SIGD[~GENSYM[quot_res][0]][0];-      assign ~SYM[0] = ~VAR[dividend][0] / ~VAR[divider][1];+      logic ~GENSYM[resultPos][1];+      logic ~GENSYM[dividerNeg][2];+      logic signed [~SIZE[~TYPO]:0] ~GENSYM[dividend2][3];+      logic signed [~SIZE[~TYPO]:0] ~GENSYM[dividendE][4];+      logic signed [~SIZE[~TYPO]:0] ~GENSYM[dividerE][5];+      logic signed [~SIZE[~TYPO]:0] ~GENSYM[quot_res][6]; -      // round toward minus infinity-      assign ~RESULT = (~VAR[dividend][0][~SIZE[~TYPO]-1] == ~VAR[divider][1][~SIZE[~TYPO]-1]) ? ~SYM[0] : ~SYM[0] - ~SIZE[~TYPO]'sd1;+      assign ~SYM[1] = ~VAR[dividend][0][~SIZE[~TYPO]-1] == ~VAR[divider][1][~SIZE[~TYPO]-1];+      assign ~SYM[2] = ~VAR[divider][1][~SIZE[~TYPO]-1] == 1'b1;+      assign ~SYM[4] = $signed({{~VAR[dividend][0][~SIZE[~TYPO]-1]},~VAR[dividend][0]});  // sign extension+      assign ~SYM[5] = $signed({{~VAR[divider][1][~SIZE[~TYPO]-1]} ,~VAR[divider][1]} );  // sign extension++      assign ~SYM[3] = ~SYM[1] ? ~SYM[4]+                               : (~SYM[2] ? (~SYM[4] - ~SYM[5] - ~SIZE[~TYPO]'sd1)+                                          : (~SYM[4] - ~SYM[5] + ~SIZE[~TYPO]'sd1));++      assign ~SYM[6] = ~SYM[3] / ~SYM[5];+      assign ~RESULT = $signed(~SYM[6][~SIZE[~TYPO]-1:0]);       // divInt end - BlackBox:     name: GHC.Base.modInt

@@ -1424,3 +1424,87 @@       ~FI       assign ~RESULT = $unsigned(~SYM[7]);       // ctz end+- BlackBox:+    name: GHC.Prim.quotRemInt8#+    kind: Declaration+    type: 'quotRemInt8# ::+      Int8# -> Int8# -> (#Int8#, Int8##)'+    template: |-+      // quotRemInt8 begin+      ~SIGD[~GENSYM[quot_res][0]][0];+      ~SIGD[~GENSYM[rem_res][1]][0];+      assign ~SYM[0] = ~ARG[0] / ~ARG[1];+      assign ~SYM[1] = ~ARG[0] % ~ARG[1];++      assign ~RESULT = {~SYM[0],~SYM[1]};+      // quotRemInt8 end+- BlackBox:+    name: GHC.Prim.quotRemWord8#+    kind: Declaration+    type: 'quotRemWord8# ::+      Word8# -> Word8# -> (#Word8#, Word8##)'+    template: |-+      // quotRemWord8 begin+      ~SIGD[~GENSYM[quot_res][0]][0];+      ~SIGD[~GENSYM[rem_res][1]][0];+      assign ~SYM[0] = ~ARG[0] / ~ARG[1];+      assign ~SYM[1] = ~ARG[0] % ~ARG[1];++      assign ~RESULT = {~SYM[0],~SYM[1]};+      // quotRemWord8 end+- BlackBox:+    name: GHC.Prim.quotRemInt16#+    kind: Declaration+    type: 'quotRemInt16# ::+      Int16# -> Int16# -> (#Int16#, Int16##)'+    template: |-+      // quotRemInt16 begin+      ~SIGD[~GENSYM[quot_res][0]][0];+      ~SIGD[~GENSYM[rem_res][1]][0];+      assign ~SYM[0] = ~ARG[0] / ~ARG[1];+      assign ~SYM[1] = ~ARG[0] % ~ARG[1];++      assign ~RESULT = {~SYM[0],~SYM[1]};+      // quotRemInt16 end+- BlackBox:+    name: GHC.Prim.quotRemWord16#+    kind: Declaration+    type: 'quotRemWord16# ::+      Word16# -> Word16# -> (#Word16#, Word16##)'+    template: |-+      // quotRemWord16 begin+      ~SIGD[~GENSYM[quot_res][0]][0];+      ~SIGD[~GENSYM[rem_res][1]][0];+      assign ~SYM[0] = ~ARG[0] / ~ARG[1];+      assign ~SYM[1] = ~ARG[0] % ~ARG[1];++      assign ~RESULT = {~SYM[0],~SYM[1]};+      // quotRemWord16 end+- BlackBox:+    name: GHC.Prim.quotRemInt32#+    kind: Declaration+    type: 'quotRemInt32# ::+      Int32# -> Int32# -> (#Int32#, Int32##)'+    template: |-+      // quotRemInt32 begin+      ~SIGD[~GENSYM[quot_res][0]][0];+      ~SIGD[~GENSYM[rem_res][1]][0];+      assign ~SYM[0] = ~ARG[0] / ~ARG[1];+      assign ~SYM[1] = ~ARG[0] % ~ARG[1];++      assign ~RESULT = {~SYM[0],~SYM[1]};+      // quotRemInt32 end+- BlackBox:+    name: GHC.Prim.quotRemWord32#+    kind: Declaration+    type: 'quotRemWord32# ::+      Word32# -> Word32# -> (#Word32#, Word32##)'+    template: |-+      // quotRemWord32 begin+      ~SIGD[~GENSYM[quot_res][0]][0];+      ~SIGD[~GENSYM[rem_res][1]][0];+      assign ~SYM[0] = ~ARG[0] / ~ARG[1];+      assign ~SYM[1] = ~ARG[0] % ~ARG[1];++      assign ~RESULT = {~SYM[0],~SYM[1]};+      // quotRemWord32 end

@@ -1,12 +1,12 @@ - BlackBox:     name: Clash.Explicit.BlockRam.blockRam#     kind: Declaration-    outputReg: true+    outputUsage: NonBlocking     type: |-       blockRam#         :: ( KnownDomain dom        ARG[0]            , HasCallStack  --       ARG[1]-           , Undefined a ) --       ARG[2]+           , NFDataX a )   --       ARG[2]         => Clock dom       -- clk,  ARG[3]         => Enable dom      -- en,   ARG[4]         -> Vec n a         -- init, ARG[5]@@ -52,12 +52,12 @@ - BlackBox:     name: Clash.Explicit.BlockRam.blockRamU#     kind: Declaration-    outputReg: true+    outputUsage: NonBlocking     type: |-       blockRamU#         :: ( KnownDomain dom        ARG[0]            , HasCallStack  --       ARG[1]-           , Undefined a ) --       ARG[2]+           , NFDataX a )   --       ARG[2]         => Clock dom       -- clk,  ARG[3]         -> Enable dom      -- en,   ARG[4]         -> SNat n          -- len,  ARG[5]@@ -95,12 +95,12 @@ - BlackBox:     name: Clash.Explicit.BlockRam.blockRam1#     kind: Declaration-    outputReg: true+    outputUsage: NonBlocking     type: |-       blockRam1#         :: ( KnownDomain dom        ARG[0]            , HasCallStack  --       ARG[1]-           , Undefined a ) --       ARG[2]+           , NFDataX a )   --       ARG[2]         => Clock dom       -- clk,  ARG[3]         -> Enable dom      -- en,   ARG[4]         -> SNat n          -- len,  ARG[5]@@ -142,61 +142,3 @@         ~RESULT <= ~SYM[0][~ARG[7]];       end~FI       // blockRam1 end-- BlackBox:-    name: Clash.Explicit.BlockRam.trueDualPortBlockRam#-    kind: Declaration-    type: |--      trueDualPortBlockRam# ::-        forall nAddrs domA domB a .-        ( HasCallStack           ~ARG[0]-        , KnownNat nAddrs        ~ARG[1]-        , KnownDomain domA       ~ARG[2]-        , KnownDomain domB       ~ARG[3]-        , NFDataX a              ~ARG[4]-        ) =>--        Clock domA ->                   ~ARG[5]-        Signal domA Bool ->             ~ARG[6]-        Signal domA Bool ->             ~ARG[7]-        Signal domA (Index nAddrs) ->   ~ARG[8]-        Signal domA a ->                ~ARG[9]--        Clock domB ->                   ~ARG[10]-        Signal domB Bool ->             ~ARG[11]-        Signal domB Bool ->             ~ARG[12]-        Signal domB (Index nAddrs) ->   ~ARG[13]-        Signal domB a ->                ~ARG[14]-        (Signal domA a, Signal domB a)-    template: |--      // trueDualPortBlockRam begin-      // Shared memory-      reg [~SIZE[~TYP[9]]-1:0] ~GENSYM[mem][0] [~LIT[1]-1:0];--      reg ~SIGD[~GENSYM[data_slow][1]][9];-      reg ~SIGD[~GENSYM[data_fast][2]][14];--      // Port A-      always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[5]) begin-          if(~ARG[6]) begin-              ~SYM[1] <= ~SYM[0][~IF~SIZE[~TYP[8]]~THEN~ARG[8]~ELSE0~FI];-              if(~ARG[7]) begin-                  ~SYM[1] <= ~ARG[9];-                  ~SYM[0][~IF~SIZE[~TYP[8]]~THEN~ARG[8]~ELSE0~FI] <= ~ARG[9];-              end-          end-      end--      // Port B-      always @(~IF~ACTIVEEDGE[Rising][3]~THENposedge~ELSEnegedge~FI ~ARG[10]) begin-          if(~ARG[11]) begin-              ~SYM[2] <= ~SYM[0][~IF~SIZE[~TYP[13]]~THEN~ARG[13]~ELSE0~FI];-              if(~ARG[12]) begin-                  ~SYM[2] <= ~ARG[14];-                  ~SYM[0][~IF~SIZE[~TYP[13]]~THEN~ARG[13]~ELSE0~FI] <= ~ARG[14];-              end-          end-      end--      assign ~RESULT = {~SYM[1], ~SYM[2]};--      // end trueDualPortBlockRam

@@ -1,7 +1,7 @@ - BlackBox:     name: Clash.Explicit.BlockRam.Blob.blockRamBlob#     kind: Declaration-    outputReg: true+    outputUsage: NonBlocking     type: |-       blockRamBlob#         :: KnownDomain dom           --       ARG[0]

@@ -1,7 +1,7 @@ - BlackBox:     name: Clash.Explicit.BlockRam.File.blockRamFile#     kind: Declaration-    outputReg: true+    outputUsage: NonBlocking     type: |-       blockRamFile#         :: ( KnownDomain dom         --       ARG[0]

@@ -4,7 +4,7 @@     type: |-       ddrIn# :: forall a slow fast n pFast gated synchronous.                  ( HasCallStack          -- ARG[0]-                 , Undefined a           -- ARG[1]+                 , NFDataX a             -- ARG[1]                  , KnownConfi~ fast domf -- ARG[2]                  , KnownConfi~ slow doms -- ARG[3]               => Clock slow              -- ARG[4]@@ -48,8 +48,8 @@     name: Clash.Explicit.DDR.ddrOut#     kind: Declaration     type: |--      ddrOut# :: ( HasCallStack               -- ARG[0]-                  , Undefined a                -- ARG[1]+      ddrOut# :: ( HasCallStack                -- ARG[0]+                  , NFDataX a                  -- ARG[1]                   , KnownConfi~ fast domf      -- ARG[2]                   , KnownConfi~ slow doms      -- ARG[3]                => Clock slow                   -- ARG[4]@@ -63,6 +63,7 @@       // ddrOut begin       reg ~SIGD[~GENSYM[data_Pos][1]][7];       reg ~SIGD[~GENSYM[data_Neg][2]][7];+      ~IF ~VIVADO ~THENreg ~SIGDO[~GENSYM[ddrOut][3]];~ELSE~FI       always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[4]~IF~ISSYNC[3]~THEN)~ELSE or ~IF~ISACTIVEHIGH[2]~THENposedge~ELSEnegedge~FI ~ARG[5])~FI begin : ~GENSYM[~COMPNAME_ddrOut_pos][5]         if (~IF~ISACTIVEHIGH[2]~THEN~ARG[5]~ELSE! ~ARG[5]~FI) begin           ~SYM[1] <= ~ARG[7];@@ -78,6 +79,14 @@         end       end -      assign ~RESULT = ~ARG[4] ? ~IF~ACTIVEEDGE[Rising][2]~THEN~SYM[1] : ~SYM[2]~ELSE~SYM[2] : ~SYM[1]~FI;+      ~IF ~VIVADO ~THENalways @(*) begin+        if (~ARG[4]) begin+          ~SYM[3] = ~IF~ACTIVEEDGE[Rising][2]~THEN~SYM[1]~ELSE~SYM[2]~FI;+        end else begin+          ~SYM[3] = ~IF~ACTIVEEDGE[Rising][2]~THEN~SYM[2]~ELSE~SYM[1]~FI;+        end+      end+      assign ~RESULT = ~SYM[3];~ELSE+      assign ~RESULT = ~ARG[4] ? ~IF~ACTIVEEDGE[Rising][2]~THEN~SYM[1] : ~SYM[2]~ELSE~SYM[2] : ~SYM[1]~FI;~FI        // ddrOut end

@@ -1,11 +1,11 @@ - BlackBox:     name: Clash.Explicit.ROM.rom#     kind: Declaration-    outputReg: true+    outputUsage: NonBlocking     type: |-       rom# :: ( KnownDomain dom        ARG[0]                , KnownNat n    --       ARG[1]-               , Undefined a ) --       ARG[2]+               , NFDataX a )   --       ARG[2]             => Clock dom       -- clk,  ARG[3]             -> Enable dom      -- en,   ARG[4]             -> Vec n a         -- init, ARG[5]

@@ -1,7 +1,7 @@ - BlackBox:     name: Clash.Explicit.ROM.Blob.romBlob#     kind: Declaration-    outputReg: true+    outputUsage: NonBlocking     type: |-       romBlob#         :: KnownDomain dom  --       ARG[0]

@@ -1,7 +1,7 @@ - BlackBox:     name: Clash.Explicit.ROM.File.romFile#     kind: Declaration-    outputReg: true+    outputUsage: NonBlocking     type: |-       romFile# :: ( KnownNat m             --       ARG[0]                    , KnownDomain dom      ) --       ARG[1]

@@ -53,70 +53,3 @@       // pragma translate_on       assign ~RESULT = ~ARG[7];       // assertBitVector end-- BlackBox:-    name: Clash.Explicit.Testbench.tbClockGen-    kind: Declaration-    type: |--      tbClockGen-        :: KnownDomain dom     -- ARG[0]-        => Signal dom Bool      -- ARG[1]-        -> Clock dom-    template: |--      // tbClockGen begin-      // pragma translate_off-      reg ~TYPO ~GENSYM[clk][0];-      // 1 = 0.1ps-      localparam ~GENSYM[half_period][1] = (~PERIOD[0]0 / 2);-      always begin-        // Delay of 1 mitigates race conditions (https://github.com/steveicarus/iverilog/issues/160)-        #1 ~SYM[0] = ~IF~ACTIVEEDGE[Rising][0]~THEN 0 ~ELSE 1 ~FI;-        `ifndef VERILATOR-        #~LONGESTPERIOD0 forever begin-          if (~ ~ARG[1]) begin-            $finish(0);-          end-          ~SYM[0] = ~ ~SYM[0];-          #~SYM[1];-          ~SYM[0] = ~ ~SYM[0];-          #~SYM[1];-        end-        `else-        ~SYM[0] = $c("this->~GENSYM[tb_clock_gen][2](",~SYM[1],",~IF~ACTIVEEDGE[Rising][0]~THENtrue~ELSEfalse~FI,",(~ ~ARG[1]),")");-        `endif-      end--      `ifdef VERILATOR-        `systemc_interface-        CData ~SYM[2](vluint32_t half_period, bool active_rising, bool result_rec) {-          static vluint32_t init_wait = ~LONGESTPERIOD0;-          static vluint32_t to_wait = 0;-          static CData clock = active_rising ? 0 : 1;--          if(init_wait == 0) {-            if(result_rec) {-              std::exit(0);-            }-            else {-              if(to_wait == 0) {-                to_wait = half_period - 1;-                clock = clock == 0 ? 1 : 0;-              }-              else {-                to_wait = to_wait - 1;-              }-            }-          }-          else {-            init_wait = init_wait - 1;-          }--          return clock;-        }-        `verilog-      `endif--      assign ~RESULT = ~SYM[0];-      // pragma translate_on-      // tbClockGen end-    warning: Clash.Signal.Internal.tbClockGen is not synthesizable!-    workInfo: Always

@@ -2,16 +2,18 @@     name: Clash.Prelude.ROM.asyncRom#     kind: Declaration     type: |--      asyncRom# :: KnownNat n -- ^ ARG[0]-                 => Vec n a    -- ^ ARG[1]-                 -> Int        -- ^ ARG[2]-                 -> a+      asyncRom#+        :: ( KnownNat n  -- ARG[0]+           , NFDataX a)  -- ARG[1]+        => Vec n a       -- ARG[2]+        -> Int           -- ARG[3]+        -> a     template: |-       // asyncRom begin       wire ~TYPO ~GENSYM[ROM][0] [0:~LIT[0]-1]; -      wire ~TYP[1] ~GENSYM[romflat][1];-      assign ~SYM[1] = ~CONST[1];+      wire ~TYP[2] ~GENSYM[romflat][1];+      assign ~SYM[1] = ~CONST[2];       genvar ~GENSYM[i][2];       ~GENERATE       for (~SYM[2]=0; ~SYM[2] < ~LIT[0]; ~SYM[2]=~SYM[2]+1) begin : ~GENSYM[mk_array][3]@@ -19,5 +21,5 @@       end       ~ENDGENERATE -      assign ~RESULT = ~SYM[0][~ARG[2]];+      assign ~RESULT = ~SYM[0][~ARG[3]];       // asyncRom end

@@ -1,11 +1,11 @@ - BlackBox:     name: Clash.Signal.Internal.delay#     kind: Declaration-    outputReg: true+    outputUsage: NonBlocking     type: |-       delay#         :: ( KnownDomain dom        -- ARG[0]-           , Undefined a )          -- ARG[1]+           , NFDataX a )            -- ARG[1]         => Clock dom                -- ARG[2]         -> Enable dom               -- ARG[3]         -> a                        -- ARG[4]@@ -29,7 +29,7 @@ - BlackBox:     name: Clash.Signal.Internal.asyncRegister#     kind: Declaration-    outputReg: true+    outputUsage: NonBlocking     type: |-       asyncRegister#         :: ( KnownDomain dom        -- ARG[0]@@ -58,11 +58,11 @@ - BlackBox:     name: Clash.Signal.Internal.register#     kind: Declaration-    outputReg: true+    outputUsage: NonBlocking     type: |-       register#         :: ( KnownDomain dom        -- ARG[0]-           , Undefined a )          -- ARG[1]+           , NFDataX a )            -- ARG[1]         => Clock dom                -- ARG[2]         -> Reset dom                -- ARG[3]         -> Enable dom               -- ARG[4]@@ -85,14 +85,15 @@       end       // register end - BlackBox:-    name: Clash.Signal.Internal.clockGen+    name: Clash.Signal.Internal.tbClockGen     kind: Declaration     type: |--      clockGen+      tbClockGen         :: KnownDomain dom     -- ARG[0]-        => Clock dom+        => Signal dom Bool     -- ARG[1]+        -> Clock dom     template: |--      // clockGen begin+      // tbClockGen begin       // pragma translate_off       reg ~TYPO ~GENSYM[clk][0];       // 1 = 0.1ps@@ -102,30 +103,40 @@         #1 ~SYM[0] = ~IF~ACTIVEEDGE[Rising][0]~THEN 0 ~ELSE 1 ~FI;         `ifndef VERILATOR         #~LONGESTPERIOD0 forever begin+          ~IF~ISACTIVEENABLE[1]~THEN+          if (~ ~ARG[1]) begin+            $finish(0);+          end+          ~ELSE~FI           ~SYM[0] = ~ ~SYM[0];           #~SYM[1];           ~SYM[0] = ~ ~SYM[0];           #~SYM[1];         end         `else-        ~SYM[0] = $c("this->~GENSYM[tb_clock_gen][2](",~SYM[1],",~IF~ACTIVEEDGE[Rising][0]~THENtrue~ELSEfalse~FI)");+        ~SYM[0] = $c("this->~GENSYM[tb_clock_gen][2](",~SYM[1],",~IF~ACTIVEEDGE[Rising][0]~THENtrue~ELSEfalse~FI,",(~ ~ARG[1]),")");         `endif       end        `ifdef VERILATOR         `systemc_interface-        CData ~SYM[2](vluint32_t half_period, bool active_rising) {+        CData ~SYM[2](vluint32_t half_period, bool active_rising, bool result_rec) {           static vluint32_t init_wait = ~LONGESTPERIOD0;           static vluint32_t to_wait = 0;           static CData clock = active_rising ? 0 : 1;            if(init_wait == 0) {-            if(to_wait == 0) {-              to_wait = half_period - 1;-              clock = clock == 0 ? 1 : 0;+            if(result_rec) {+              std::exit(0);             }             else {-              to_wait = to_wait - 1;+              if(to_wait == 0) {+                to_wait = half_period - 1;+                clock = clock == 0 ? 1 : 0;+              }+              else {+                to_wait = to_wait - 1;+              }             }           }           else {@@ -139,8 +150,46 @@        assign ~RESULT = ~SYM[0];       // pragma translate_on-      // clockGen end-    warning: Clash.Signal.Internal.clockGen is not synthesizable!+      // tbClockGen end+    warning: Clash.Signal.Internal.tbClockGen is not synthesizable!+    workInfo: Always+- BlackBox:+    name: Clash.Signal.Internal.tbDynamicClockGen+    kind: Declaration+    type: |-+      clockGen+        :: KnownDomain dom     -- ARG[0]+        -> Signal dom Int64    -- ARG[1]+        -> Signal dom Bool     -- ARG[2]+        => Clock dom+    template: |-+      // tbDynamicClockGen begin+      // pragma translate_off+      reg ~TYPO ~GENSYM[clk][0];+      time ~GENSYM[half_period][1];+      always begin+        // Delay of 1 mitigates race conditions (https://github.com/steveicarus/iverilog/issues/160)+        #1 ~SYM[0] = ~IF~ACTIVEEDGE[Rising][0]~THEN 0 ~ELSE 1 ~FI;+        #~LONGESTPERIOD0 forever begin+          ~IF~ISACTIVEENABLE[2]~THEN+          if (~ ~ARG[2]) begin+            $finish(0);+          end+          ~ELSE~FI+          // 1 = 0.1ps+          ~SYM[1] = (~VAR[periods][1] / 2);++          ~SYM[0] = ~ ~SYM[0];+          #(~SYM[1] * 0.01);+          ~SYM[0] = ~ ~SYM[0];+          #(~SYM[1] * 0.01);+        end+      end++      assign ~RESULT = ~SYM[0];+      // pragma translate_on+      // tbDynamicClockGen end+    warning: Clash.Signal.Internal.tbDynamicClockGen is not synthesizable!     workInfo: Always - BlackBox:     name: Clash.Signal.Internal.resetGenN

@@ -1,7 +1,7 @@ - BlackBox:     name: Clash.Sized.Internal.BitVector.replaceBit#     kind: Declaration-    outputReg: true+    outputUsage: Blocking     type: |-       replaceBit# :: KnownNat n  -- ARG[0]                    => BitVector n -- ARG[1]@@ -18,7 +18,7 @@ - BlackBox:     name: Clash.Sized.Internal.BitVector.setSlice#     kind: Declaration-    outputReg: true+    outputUsage: Blocking     type: |-       setSlice# :: SNat (m + 1 + i)                  -> BitVector (m + 1 + i) -- ARG[1]

@@ -97,7 +97,7 @@       for (~SYM[1]=0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : ~GENSYM[map][2]~IF~SIZE[~TYP[1]]~THEN         wire ~TYPEL[~TYP[1]] ~GENSYM[map_in][3];         assign ~SYM[3] = ~VAR[vec][1][~SYM[1]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]];~ELSE ~FI-        ~OUTPUTWIREREG[0] ~TYPEL[~TYPO] ~GENSYM[map_out][4];+        ~OUTPUTUSAGE[0] ~TYPEL[~TYPO] ~GENSYM[map_out][4];         ~INST 0           ~OUTPUT <= ~SYM[4]~ ~TYPEL[~TYPO]~           ~INPUT  <= ~SYM[3]~ ~TYPEL[~TYP[1]]~@@ -120,7 +120,7 @@         wire [~SIZE[~INDEXTYPE[~LIT[0]]]-1:0] ~GENSYM[map_index][3];~IF~SIZE[~TYP[2]]~THEN         wire ~TYPEL[~TYP[2]] ~GENSYM[map_in][4];         assign ~SYM[4] = ~VAR[vec][2][~SYM[1]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];~ELSE ~FI-        ~OUTPUTWIREREG[1] ~TYPEL[~TYPO] ~GENSYM[map_out][5];+        ~OUTPUTUSAGE[1] ~TYPEL[~TYPO] ~GENSYM[map_out][5];          assign ~SYM[3] = ~SIZE[~INDEXTYPE[~LIT[0]]]'d~MAXINDEX[~TYPO] - ~SYM[1][0+:~SIZE[~INDEXTYPE[~LIT[0]]]];         ~INST 1@@ -146,7 +146,7 @@         wire ~TYP[0] ~GENSYM[map_index][3];~IF~SIZE[~TYP[2]]~THEN         wire ~TYPEL[~TYP[2]] ~GENSYM[map_in][4];         assign ~SYM[4] = ~VAR[vec][2][~SYM[1]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];~ELSE ~FI-        ~OUTPUTWIREREG[1] ~TYPEL[~TYPO] ~GENSYM[map_out][5];+        ~OUTPUTUSAGE[1] ~TYPEL[~TYPO] ~GENSYM[map_out][5];          assign ~SYM[3] = ~SIZE[~TYP[0]]'d~MAXINDEX[~TYPO] - ~SYM[1][0+:~SIZE[~TYP[0]]] + ~ARG[0];         ~INST 1@@ -173,7 +173,7 @@         assign ~SYM[3] = ~VAR[vec1][1][~SYM[2]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]];~ELSE ~FI~IF~SIZE[~TYP[2]]~THEN         wire ~TYPEL[~TYP[2]] ~GENSYM[zipWith_in2][4];         assign ~SYM[4] = ~VAR[vec2][2][~SYM[2]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];~ELSE ~FI-        ~OUTPUTWIREREG[0] ~TYPEL[~TYPO] ~SYM[5];+        ~OUTPUTUSAGE[0] ~TYPEL[~TYPO] ~SYM[5];         ~INST 0           ~OUTPUT <= ~SYM[5]~ ~TYPEL[~TYPO]~           ~INPUT  <= ~SYM[3]~ ~TYPEL[~TYP[1]]~@@ -200,7 +200,7 @@         wire ~TYPEL[~TYP[2]] ~GENSYM[foldr_in1][5];         assign ~SYM[5] = ~VAR[xs][2][(~LENGTH[~TYP[2]]-1-~SYM[3])*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]];~ELSE ~FI         wire ~TYPO ~GENSYM[foldr_in2][6];-        ~OUTPUTWIREREG[0] ~TYPO ~GENSYM[foldr_out][7];+        ~OUTPUTUSAGE[0] ~TYPO ~GENSYM[foldr_out][7];          assign ~SYM[6] = ~SYM[0][~SYM[3]+1];         ~INST 0

@@ -5,12 +5,24 @@       Int -> Int'     template: |-       // divInt begin-      // divide (rounds towards zero)-      wire ~SIGD[~GENSYM[quot_res][0]][0];-      assign ~SYM[0] = ~VAR[dividend][0] / ~VAR[divider][1];+      wire ~GENSYM[resultPos][1];+      wire ~GENSYM[dividerNeg][2];+      wire signed [~SIZE[~TYPO]:0] ~GENSYM[dividend2][3];+      wire signed [~SIZE[~TYPO]:0] ~GENSYM[dividendE][4];+      wire signed [~SIZE[~TYPO]:0] ~GENSYM[dividerE][5];+      wire signed [~SIZE[~TYPO]:0] ~GENSYM[quot_res][6]; -      // round toward minus infinity-      assign ~RESULT = (~VAR[dividend][0][~SIZE[~TYPO]-1] == ~VAR[divider][1][~SIZE[~TYPO]-1]) ? ~SYM[0] : ~SYM[0] - ~SIZE[~TYPO]'sd1;+      assign ~SYM[1] = ~VAR[dividend][0][~SIZE[~TYPO]-1] == ~VAR[divider][1][~SIZE[~TYPO]-1];+      assign ~SYM[2] = ~VAR[divider][1][~SIZE[~TYPO]-1] == 1'b1;+      assign ~SYM[4] = $signed({{~VAR[dividend][0][~SIZE[~TYPO]-1]},~VAR[dividend][0]});  // sign extension+      assign ~SYM[5] = $signed({{~VAR[divider][1][~SIZE[~TYPO]-1]} ,~VAR[divider][1]} );  // sign extension++      assign ~SYM[3] = ~SYM[1] ? ~SYM[4]+                               : (~SYM[2] ? (~SYM[4] - ~SYM[5] - ~SIZE[~TYPO]'sd1)+                                          : (~SYM[4] - ~SYM[5] + ~SIZE[~TYPO]'sd1));++      assign ~SYM[6] = ~SYM[3] / ~SYM[5];+      assign ~RESULT = $signed(~SYM[6][~SIZE[~TYPO]-1:0]);       // divInt end - BlackBox:     name: GHC.Base.modInt

@@ -1472,3 +1472,87 @@       ~FI       assign ~RESULT = $unsigned(~SYM[7]);       // ctz end+- BlackBox:+    name: GHC.Prim.quotRemInt8#+    kind: Declaration+    type: 'quotRemInt8# ::+      Int8# -> Int8# -> (#Int8#, Int8##)'+    template: |-+      // quotRemInt8 begin+      wire ~SIGD[~GENSYM[quot_res][0]][0];+      wire ~SIGD[~GENSYM[rem_res][1]][0];+      assign ~SYM[0] = ~ARG[0] / ~ARG[1];+      assign ~SYM[1] = ~ARG[0] % ~ARG[1];++      assign ~RESULT = {~SYM[0],~SYM[1]};+      // quotRemInt8 end+- BlackBox:+    name: GHC.Prim.quotRemWord8#+    kind: Declaration+    type: 'quotRemWord8# ::+      Word8# -> Word8# -> (#Word8#, Word8##)'+    template: |-+      // quotRemWord8 begin+      wire ~SIGD[~GENSYM[quot_res][0]][0];+      wire ~SIGD[~GENSYM[rem_res][1]][0];+      assign ~SYM[0] = ~ARG[0] / ~ARG[1];+      assign ~SYM[1] = ~ARG[0] % ~ARG[1];++      assign ~RESULT = {~SYM[0],~SYM[1]};+      // quotRemWord8 end+- BlackBox:+    name: GHC.Prim.quotRemInt16#+    kind: Declaration+    type: 'quotRemInt16# ::+      Int16# -> Int16# -> (#Int16#, Int16##)'+    template: |-+      // quotRemInt16 begin+      wire ~SIGD[~GENSYM[quot_res][0]][0];+      wire ~SIGD[~GENSYM[rem_res][1]][0];+      assign ~SYM[0] = ~ARG[0] / ~ARG[1];+      assign ~SYM[1] = ~ARG[0] % ~ARG[1];++      assign ~RESULT = {~SYM[0],~SYM[1]};+      // quotRemInt16 end+- BlackBox:+    name: GHC.Prim.quotRemWord16#+    kind: Declaration+    type: 'quotRemWord16# ::+      Word16# -> Word16# -> (#Word16#, Word16##)'+    template: |-+      // quotRemWord16 begin+      wire ~SIGD[~GENSYM[quot_res][0]][0];+      wire ~SIGD[~GENSYM[rem_res][1]][0];+      assign ~SYM[0] = ~ARG[0] / ~ARG[1];+      assign ~SYM[1] = ~ARG[0] % ~ARG[1];++      assign ~RESULT = {~SYM[0],~SYM[1]};+      // quotRemWord16 end+- BlackBox:+    name: GHC.Prim.quotRemInt32#+    kind: Declaration+    type: 'quotRemInt32# ::+      Int32# -> Int32# -> (#Int32#, Int32##)'+    template: |-+      // quotRemInt32 begin+      wire ~SIGD[~GENSYM[quot_res][0]][0];+      wire ~SIGD[~GENSYM[rem_res][1]][0];+      assign ~SYM[0] = ~ARG[0] / ~ARG[1];+      assign ~SYM[1] = ~ARG[0] % ~ARG[1];++      assign ~RESULT = {~SYM[0],~SYM[1]};+      // quotRemInt32 end+- BlackBox:+    name: GHC.Prim.quotRemWord32#+    kind: Declaration+    type: 'quotRemWord32# ::+      Word32# -> Word32# -> (#Word32#, Word32##)'+    template: |-+      // quotRemWord32 begin+      wire ~SIGD[~GENSYM[quot_res][0]][0];+      wire ~SIGD[~GENSYM[rem_res][1]][0];+      assign ~SYM[0] = ~ARG[0] / ~ARG[1];+      assign ~SYM[1] = ~ARG[0] % ~ARG[1];++      assign ~RESULT = {~SYM[0],~SYM[1]};+      // quotRemWord32 end

@@ -1,11 +1,12 @@ - BlackBox:     name: Clash.Explicit.BlockRam.blockRam#     kind: Declaration+    outputUsage: NonBlocking     type: |-       blockRam#         :: ( KnownDomain dom        ARG[0]            , HasCallStack  --       ARG[1]-           , Undefined a ) --       ARG[2]+           , NFDataX a )   --       ARG[2]         => Clock dom       -- clk,  ARG[3]         -> Enable dom      -- en,   ARG[4]         -> Vec n a         -- init, ARG[5]@@ -56,11 +57,12 @@ - BlackBox:     name: Clash.Explicit.BlockRam.blockRamU#     kind: Declaration+    outputUsage: NonBlocking     type: |-       blockRamU#         :: ( KnownDomain dom        ARG[0]            , HasCallStack  --       ARG[1]-           , Undefined a ) --       ARG[2]+           , NFDataX a )   --       ARG[2]         => Clock dom       -- clk,  ARG[3]         -> Enable dom      -- en,   ARG[4]         -> SNat n          -- len,  ARG[5]@@ -113,11 +115,12 @@ - BlackBox:     name: Clash.Explicit.BlockRam.blockRam1#     kind: Declaration+    outputUsage: NonBlocking     type: |-       blockRam1#         :: ( KnownDomain dom        ARG[0]            , HasCallStack  --       ARG[1]-           , Undefined a ) --       ARG[2]+           , NFDataX a )   --       ARG[2]         => Clock dom       -- clk,  ARG[3]         -> Enable dom      -- en,   ARG[4]         -> SNat n          -- len,  ARG[5]@@ -168,67 +171,3 @@         end process; ~FI       end block;       --end blockRam1-- BlackBox:-    name: Clash.Explicit.BlockRam.trueDualPortBlockRam#-    kind: Declaration-    type: |--      trueDualPortBlockRam# ::-        forall nAddrs domA domB a .-        ( HasCallStack           ~ARG[0]-        , KnownNat nAddrs        ~ARG[1]-        , KnownDomain domA       ~ARG[2]-        , KnownDomain domB       ~ARG[3]-        , NFDataX a              ~ARG[4]-        ) =>--        Clock domA ->                   ~ARG[5]-        Signal domA Bool ->             ~ARG[6]-        Signal domA Bool ->             ~ARG[7]-        Signal domA (Index nAddrs) ->   ~ARG[8]-        Signal domA a ->                ~ARG[9]--        Clock domB ->                   ~ARG[10]-        Signal domB Bool ->             ~ARG[11]-        Signal domB Bool ->             ~ARG[12]-        Signal domB (Index nAddrs) ->   ~ARG[13]-        Signal domB a ->                ~ARG[14]-        (Signal domA a, Signal domB a)-    template: |--      -- trueDualPortBlockRam begin-      ~GENSYM[~RESULT_trueDualPortBlockRam][1] : block-        -- Shared memory-        type mem_type is array ( ~LIT[1]-1 downto 0 ) of ~TYP[9];-        shared variable mem : mem_type;-        signal ~GENSYM[a_dout][2] : ~TYP[9];-        signal ~GENSYM[b_dout][3] : ~TYP[14];-      begin--        -- Port A-        process(~ARG[5])-        begin-            if(rising_edge(~ARG[5])) then-                  if(~ARG[6]) then-                    if(~ARG[7]) then-                        mem(~IF~SIZE[~TYP[8]]~THENto_integer(~ARG[8])~ELSE0~FI) := ~ARG[9];-                    end if;-                    ~SYM[2] <= mem(~IF~SIZE[~TYP[8]]~THENto_integer(~ARG[8])~ELSE0~FI);-                end if;-            end if;-        end process;--        -- Port B-        process(~ARG[10])-        begin-            if(rising_edge(~ARG[10])) then-                if(~ARG[11]) then-                    if(~ARG[12]) then-                        mem(~IF~SIZE[~TYP[13]]~THENto_integer(~ARG[13])~ELSE0~FI) := ~ARG[14];-                    end if;-                    ~SYM[3] <= mem(~IF~SIZE[~TYP[13]]~THENto_integer(~ARG[13])~ELSE0~FI);-                end if;-            end if;-        end process;--        ~RESULT <= (~SYM[2], ~SYM[3]);-      end block;-      -- end trueDualPortBlockRam

@@ -1,6 +1,7 @@ - BlackBox:     name: Clash.Explicit.BlockRam.Blob.blockRamBlob#     kind: Declaration+    outputUsage: NonBlocking     type: |-       blockRamBlob#         :: KnownDomain dom           --       ARG[0]

@@ -1,6 +1,7 @@ - BlackBox:     name: Clash.Explicit.BlockRam.File.blockRamFile#     kind: Declaration+    outputUsage: NonBlocking     type: |-       blockRamFile#         :: ( KnownDomain dom        -- ARG[0]

@@ -4,7 +4,7 @@     type: |-       ddrIn# :: forall a slow fast n pFast enabled synchronous.                  ( HasCallStack           -- ARG[0]-                 , Undefined a            -- ARG[1]+                 , NFDataX a              -- ARG[1]                  , KnownConfi~ fast domf  -- ARG[2]                  , KnownConfi~ slow doms  -- ARG[3]               => Clock slow               -- ARG[4]@@ -94,8 +94,8 @@     name: Clash.Explicit.DDR.ddrOut#     kind: Declaration     type: |--      ddrOut# :: ( HasCallStack               -- ARG[0]-                  , Undefined a                -- ARG[1]+      ddrOut# :: ( HasCallStack                -- ARG[0]+                  , NFDataX a                  -- ARG[1]                   , KnownConfi~ fast domf      -- ARG[2]                   , KnownConfi~ slow doms      -- ARG[3]                => Clock slow                   -- ARG[4]

@@ -1,10 +1,11 @@ - BlackBox:     name: Clash.Explicit.ROM.rom#     kind: Declaration+    outputUsage: NonBlocking     type: |-       rom# :: ( KnownDomain dom        ARG[0]                , KnownNat n    --       ARG[1]-               , Undefined a ) --       ARG[2]+               , NFDataX a )   --       ARG[2]             => Clock dom       -- clk,  ARG[3]             -> Enable dom      -- en,   ARG[4]             -> Vec n a         -- init, ARG[5]

@@ -1,6 +1,7 @@ - BlackBox:     name: Clash.Explicit.ROM.Blob.romBlob#     kind: Declaration+    outputUsage: NonBlocking     type: |-       romBlob#         :: KnownDomain dom  --       ARG[0]

@@ -1,6 +1,7 @@ - BlackBox:     name: Clash.Explicit.ROM.File.romFile#     kind: Declaration+    outputUsage: NonBlocking     type: |-       romFile# :: ( KnownNat m           --       ARG[0]                    , KnownDomain dom      --       ARG[1]

@@ -149,41 +149,13 @@       end block;       -- assertBitVector end - BlackBox:-    name: Clash.Explicit.Testbench.tbClockGen-    comment: |--      ModelSim and Vivado seem to round time values to an integer number of picoseconds.-              Use two half periods to prevent rounding errors from affecting the full period.-    kind: Declaration-    type: |--      tbClockGen-        :: KnownDomain dom     -- ARG[0]-        => Signal dom Bool     -- ARG[1]-        -> Clock dom-    template: |--      -- tbClockGen begin-      -- pragma translate_off-      ~GENSYM[clkGen][0] : process is-        constant ~GENSYM[half_periodH][1] : time := ~PERIOD[0]000 fs / 2;-        constant ~GENSYM[half_periodL][2] : time := ~PERIOD[0]000 fs - ~SYM[1];-      begin-        ~RESULT <= ~IF~ACTIVEEDGE[Rising][0]~THEN'0'~ELSE'1'~FI;-        wait for ~LONGESTPERIOD ps;-        while ~ARG[1] loop-          ~RESULT <= not ~RESULT;-          wait for ~SYM[1];-          ~RESULT <= not ~RESULT;-          wait for ~SYM[2];-        end loop;-        wait;-      end process;-      -- pragma translate_on-      -- tbClockGen end-    warning: Clash.Signal.Internal.tbClockGen is not synthesizable!-    workInfo: Always-- BlackBox:     name: Clash.Explicit.Testbench.tbEnableGen     kind: Declaration     type: 'tbEnableGen ::       Enable dom'     template: ~RESULT <= true;     workInfo: Always+- BlackBox:+    name: Clash.Explicit.Testbench.clockToDiffClock+    kind: Expression+    template: (~ARG[1], not ~ARG[1])

@@ -2,19 +2,21 @@     name: Clash.Prelude.ROM.asyncRom#     kind: Declaration     type: |--      asyncRom# :: KnownNat n -- ^ ARG[0]-                 => Vec n a    -- ^ ARG[1]-                 -> Int        -- ^ ARG[2]-                 -> a+      asyncRom#+        :: ( KnownNat n  -- ARG[0]+           , NFDataX a)  -- ARG[1]+        => Vec n a       -- ARG[2]+        -> Int           -- ARG[3]+        -> a     template: |-       -- asyncRom begin       ~GENSYM[asyncRom][0] : block-        signal ~GENSYM[ROM][1] : ~TYP[1];+        signal ~GENSYM[ROM][1] : ~TYP[2];         signal ~GENSYM[rd][2] : integer range 0 to ~LIT[0]-1;       begin-        ~SYM[1] <= ~CONST[1];+        ~SYM[1] <= ~CONST[2]; -        ~SYM[2] <= to_integer(~VAR[rdI][2](31 downto 0))+        ~SYM[2] <= to_integer(~VAR[rdI][3](31 downto 0))         -- pragma translate_off                             mod ~LIT[0]         -- pragma translate_on

@@ -1,10 +1,11 @@ - BlackBox:     name: Clash.Signal.Internal.delay#     kind: Declaration+    outputUsage: NonBlocking     type: |-       delay#         :: ( KnownDomain dom        -- ARG[0]-           , Undefined a )          -- ARG[1]+           , NFDataX a )            -- ARG[1]         => Clock dom                -- ARG[2]         -> Enable dom               -- ARG[3]         -> a                        -- ARG[4]@@ -34,6 +35,7 @@ - BlackBox:     name: Clash.Signal.Internal.asyncRegister#     kind: Declaration+    outputUsage: NonBlocking     type: |-       asyncRegister#         :: ( KnownDomain dom        -- ARG[0]@@ -69,6 +71,7 @@ - BlackBox:     name: Clash.Signal.Internal.register#     kind: Declaration+    outputUsage: NonBlocking     type: |-       register#         :: ( KnownDomain dom        -- ARG[0]@@ -126,17 +129,19 @@       end process;~FI~FI       -- register end - BlackBox:-    name: Clash.Signal.Internal.clockGen+    name: Clash.Signal.Internal.tbClockGen     comment: |-       ModelSim and Vivado seem to round time values to an integer number of picoseconds.               Use two half periods to prevent rounding errors from affecting the full period.     kind: Declaration+    outputUsage: NonBlocking     type: |--      clockGen+      tbClockGen         :: KnownDomain dom     -- ARG[0]-        => Clock dom+        => Signal dom Bool     -- ARG[1]+        -> Clock dom     template: |--      -- clockGen begin+      -- tbClockGen begin       -- pragma translate_off       ~GENSYM[clkGen][0] : process is         constant ~GENSYM[half_periodH][1] : time := ~PERIOD[0]000 fs / 2;@@ -144,7 +149,7 @@       begin         ~RESULT <= ~IF~ACTIVEEDGE[Rising][0]~THEN'0'~ELSE'1'~FI;         wait for ~LONGESTPERIOD ps;-        loop+        ~IF~ISACTIVEENABLE[1]~THENwhile ~ARG[1] ~ELSE~FIloop           ~RESULT <= not ~RESULT;           wait for ~SYM[1];           ~RESULT <= not ~RESULT;@@ -153,10 +158,50 @@         wait;       end process;       -- pragma translate_on-      -- clockGen end-    warning: Clash.Signal.Internal.clockGen is not synthesizable!+      -- tbClockGen end+    warning: Clash.Signal.Internal.tbClockGen is not synthesizable!     workInfo: Always - BlackBox:+    name: Clash.Signal.Internal.tbDynamicClockGen+    comment: |-+      ModelSim and Vivado seem to round time values to an integer number of picoseconds.+              Use two half periods to prevent rounding errors from affecting the full period.+    kind: Declaration+    outputUsage: NonBlocking+    type: |-+      tbDynamicClockGen+        :: KnownDomain dom     -- ARG[0]+        => Signal dom Int64    -- ARG[1]+        -> Signal dom Bool     -- ARG[2]+        -> Clock dom+    template: |-+      -- tbDynamicClockGen begin+      -- pragma translate_off+      ~GENSYM[dynClkGen][0] : process is+        variable ~GENSYM[whole_period][1] : time;+        variable ~GENSYM[half_periodH][2] : time;+        variable ~GENSYM[half_periodL][3] : time;+      begin+        ~RESULT <= ~IF~ACTIVEEDGE[Rising][0]~THEN'0'~ELSE'1'~FI;+        wait for ~LONGESTPERIOD ps;++        ~IF~ISACTIVEENABLE[2]~THENwhile ~ARG[2] ~ELSE~FIloop+          ~SYM[1] := to_integer(~VAR[periods][1]) * 1 fs;+          ~SYM[2] := ~SYM[1] / 2;+          ~SYM[3] := ~SYM[1] - ~SYM[2];++          ~RESULT <= not ~RESULT;+          wait for ~SYM[2];+          ~RESULT <= not ~RESULT;+          wait for ~SYM[3];+        end loop;+        wait;+      end process;+      -- pragma translate_on+      -- tbDynamicClockGen end+    warning: Clash.Signal.Internal.tbDynamicClockGen is not synthesizable!+    workInfo: Always+- BlackBox:     name: Clash.Signal.Internal.resetGenN     kind: Declaration     type: 'resetGenN :: (KnownDomain@@ -185,6 +230,6 @@     name: Clash.Signal.Internal.unsafeToReset     kind: Declaration     type: 'unsafeToReset ::-      Signal dom Bool -> Reset dom'-    template: ~RESULT <= '1' when ~ARG[0] = true else '0';+      KnownDomain dom => Signal dom Bool -> Reset dom'+    template: ~RESULT <= '1' when ~ARG[1] = true else '0';     workInfo: Never

@@ -252,6 +252,7 @@ - BlackBox:     name: Clash.Sized.Internal.BitVector.replaceBit#     kind: Declaration+    outputUsage: NonBlocking     type: |-       replaceBit# :: KnownNat n  -- ARG[0]                    => BitVector n -- ARG[1]@@ -282,6 +283,7 @@ - BlackBox:     name: Clash.Sized.Internal.BitVector.setSlice#     kind: Declaration+    outputUsage: NonBlocking     type: |-       setSlice# :: SNat (m + 1 + i)                  => BitVector (m + 1 + i) -- ARG[1]

@@ -274,6 +274,7 @@ - BlackBox:     name: Clash.Sized.Vector.replace_int     kind: Declaration+    outputUsage: NonBlocking     type: 'replace_int ::       KnownNat n => Vec n a -> Int -> a -> Vec n a'     template: |-

@@ -1,65 +0,0 @@-- BlackBox:-    name: Clash.Xilinx.ClockGen.clockWizard-    kind: Declaration-    type: |--      clockWizard-        :: ( KnownDomain domIn confIn       -- ARG[0]-           , KnownDomain domOut confOut )   -- ARG[1]-        => SSymbol name                    -- ARG[2]-        -> Clock  pllIn                    -- ARG[3]-        -> Reset pllIn                     -- ARG[4]-        -> (Clock pllOut, Enable pllOut)-    template: |--      -- clockWizard begin-      ~GENSYM[clockWizard][0] : block-        signal ~GENSYM[pllOut][1]  : std_logic;-        signal ~GENSYM[locked][2]  : std_logic;-        signal ~GENSYM[pllLock][3] : boolean;--        component ~NAME[2]-          port (CLK_IN1  : in std_logic;-                RESET    : in std_logic;-                CLK_OUT1 : out std_logic;-                LOCKED   : out std_logic);-        end component;-      begin-        ~GENSYM[clockWizard_inst][4] : component ~NAME[2] port map (~ARG[3],~IF ~ISACTIVEHIGH[0] ~THEN ~ARG[4] ~ELSE NOT(~ARG[4]) ~FI,~SYM[1],~SYM[2]);-        ~SYM[3] <= true when ~SYM[2] = '1' else false;-        ~RESULT <= (~SYM[1],~SYM[3]);-      end block;-      -- clockWizard end-    workInfo: Always-- BlackBox:-    name: Clash.Xilinx.ClockGen.clockWizardDifferential-    kind: Declaration-    type: |--      clockWizardDifferential-        :: ( KnownDomain domIn confIn       -- ARG[0]-           , KnownDomain domOut confOut )   -- ARG[1]-        => SSymbol name                    -- ARG[2]-        -> Clock pllIn                     -- ARG[3]-        -> Clock pllIn                     -- ARG[4]-        -> Reset pllIn                     -- ARG[5]-        -> (Clock pllOut, Enable pllOut)-    template: |--      -- clockWizardDifferential begin-      ~GENSYM[clockWizardDifferential][0] : block-        signal ~GENSYM[pllOut][1]  : std_logic;-        signal ~GENSYM[locked][2]  : std_logic;-        signal ~GENSYM[pllLock][3] : boolean;--        component ~NAME[2]-          port (CLK_IN1_D_clk_n : in std_logic;-                CLK_IN1_D_clk_p : in std_logic;-                RESET           : in std_logic;-                CLK_OUT1        : out std_logic;-                LOCKED          : out std_logic);-        end component;-      begin-        ~GENSYM[clockWizardDifferential_inst][4] : component ~NAME[2]-          port map (~ARG[3],~ARG[4],~IF ~ISACTIVEHIGH[0] ~THEN ~ARG[5] ~ELSE NOT(~ARG[5]) ~FI,~SYM[1],~SYM[2]);-        ~SYM[3] <= true when ~SYM[2] = '1' else false;-        ~RESULT <= (~SYM[1],~SYM[3]);-      end block;-      -- clockWizardDifferential end-    workInfo: Always

@@ -17,15 +17,22 @@     template: |-       -- divInt begin       ~GENSYM[divInt][0] : block-        signal ~GENSYM[quot_res][1] : ~TYP[1];+        signal ~GENSYM[resultPos][1] : boolean;+        signal ~GENSYM[dividerNeg][2] : boolean;+        signal ~GENSYM[dividend2][3] : signed(~SIZE[~TYPO] downto 0);+        signal ~GENSYM[quot_res][4] : signed(~SIZE[~TYPO] downto 0);       begin-        ~SYM[1] <= ~ARG[0] / ~ARG[1]+        ~SYM[1] <= ~VAR[dividend][0](~VAR[dividend][0]'high) = ~VAR[divider][1](~VAR[divider][1]'high);+        ~SYM[2] <= ~VAR[divider][1](~VAR[divider][1]'high) = '1';+        ~SYM[3] <= resize(~VAR[dividend][0],~SIZE[~TYPO]+1)   when ~SYM[1] else+                   (resize(~VAR[dividend][0],~SIZE[~TYPO]+1) - resize(~VAR[divider][1],~SIZE[~TYPO]+1) - 1)   when ~SYM[2] else+                   (resize(~VAR[dividend][0],~SIZE[~TYPO]+1) - resize(~VAR[divider][1],~SIZE[~TYPO]+1) + 1);+        ~SYM[4] <= ~SYM[3] / ~VAR[divider][1]             -- pragma translate_off-            when (ARG[1] /= 0) else (others => 'X')+            when (~VAR[divider][1] /= 0) else (others => 'X')             -- pragma translate_on             ;-        ~RESULT <= ~SYM[1] - 1 when ((~ARG[0] = abs ~ARG[0]) /= (~ARG[1] = abs ~ARG[1])) else-                   ~SYM[1];+        ~RESULT <= signed(~SYM[4](~SIZE[~TYPO]-1 downto 0));       end block;       -- divInt end - BlackBox:

@@ -291,6 +291,14 @@       but fixed-length after synthesis. Use carefully.'     workInfo: Never - BlackBox:+    name: GHC.Num.Integer.integerToInt64#+    kind: Expression+    type: 'integerToInt64# :: Integer -> Int64#'+    template: ~ARG[0]+    warning: 'GHC.Num.Integer.integerToInt64#: Integers are dynamically sized in+      simulation, but fixed-length after synthesis. Use carefully.'+    workInfo: Never+- BlackBox:     name: GHC.Num.Integer.integerToWord64#     comment: only used by 32 bit GHC     kind: Expression@@ -301,6 +309,14 @@       simulation, but fixed-length after synthesis. Use carefully.'     workInfo: Never - BlackBox:+    name: GHC.Num.Integer.integerFromWord64#+    kind: Expression+    type: 'integerFromWord64# :: Word64# -> Integer'+    template: signed(std_logic_vector(~ARG[0]))+    warning: 'GHC.Num.Integer.integerFromWord64#: Integers are dynamically sized in+      simulation, but fixed-length after synthesis. Use carefully.'+    workInfo: Never+- BlackBox:     name: GHC.Num.Integer.integerBit#     kind: Expression     type: 'integerBit :: Word#@@ -341,17 +357,17 @@     warning: 'GHC.Num.Integer.integerAnd: Integers are dynamically sized in simulation,       but fixed-length after synthesis. Use carefully.' - BlackBox:-    name: GHC.Num.Integer.integerSigmum+    name: GHC.Num.Integer.integerSignum     kind: Declaration-    type: 'integerSigmum ::+    type: 'integerSignum ::       Integer -> Integer'     template: |2 -      -- begin integerSigmum+      -- begin integerSignum       ~RESULT <= to_signed(-1, ~SIZE[~TYPO]) when ~ARG[0] < 0         else to_signed(0, ~SIZE[~TYPO])  when ~ARG[0] = 0         else to_signed(1, ~SIZE[~TYPO]);-      -- end integerSigmum+      -- end integerSignum     warning: 'GHC.Num.Integer.integerSignum: Integers are dynamically sized in simulation,       but fixed-length after synthesis. Use carefully.' - BlackBox:@@ -403,3 +419,9 @@           ;     warning: 'GHC.Num.Integer.integerQuot: Integers are dynamically sized in simulation,       but fixed-length after synthesis. Use carefully.'+- BlackBox:+    name: GHC.Num.Integer.$wintegerFromInt64#+    kind: Expression+    type: '$wintegerFromInt64# :: Int64# -> Int#'+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never

@@ -1257,3 +1257,1003 @@           when (~ARG[1] /= 0) else (others => 'X')           -- pragma translate_on           ;+- BlackBox:+    name: GHC.Prim.int8ToInt#+    kind: Expression+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.intToInt8#+    kind: Expression+    template: ~VAR[i][0](7 downto 0)+    workInfo: Never+- BlackBox:+    name: GHC.Prim.negateInt8#+    kind: Expression+    template: -~ARG[0]+- BlackBox:+    name: GHC.Prim.timesInt8#+    kind: Expression+    template: resize(~ARG[0] * ~ARG[1],~SIZE[~TYPO])+- BlackBox:+    name: GHC.Prim.quotInt8#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] / ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.remInt8#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] rem ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.quotRemInt8#+    kind: Declaration+    template: |-+      ~RESULT <= (~ARG[0] / ~ARG[1], ~ARG[0] rem ~ARG[1])+          -- pragma translate_off+          when (~ARG[1] /= 0) else ((others => 'X'), (others => 'X'))+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.uncheckedShiftLInt8#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= shift_left(~ARG[0],~SYM[1])+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.uncheckedShiftRAInt8#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftR][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= shift_right(~ARG[0],~SYM[1])+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.uncheckedShiftRLInt8#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftRL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= ~ARG[0] srl ~SYM[1]+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.int8ToWord8#+    kind: Expression+    template: unsigned(std_logic_vector(~ARG[0]))+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqInt8#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] = ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.geInt8#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] >= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.gtInt8#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] > ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.leInt8#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] <= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.ltInt8#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] < ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.neInt8#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] /= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.word8ToWord#+    kind: Expression+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.wordToWord8#+    kind: Expression+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.timesWord8#+    kind: Expression+    template: resize(~ARG[0] * ~ARG[1],~SIZE[~TYPO])+- BlackBox:+    name: GHC.Prim.quotWord8#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] / ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.remWord8#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] rem ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.quotRemWord8#+    kind: Declaration+    template: |-+      ~RESULT <= (~ARG[0] / ~ARG[1], ~ARG[0] rem ~ARG[1])+          -- pragma translate_off+          when (~ARG[1] /= 0) else ((others => 'X'), (others => 'X'))+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.andWord8#+    kind: Expression+    template: ~ARG[0] and ~ARG[1]+- BlackBox:+    name: GHC.Prim.orWord8#+    kind: Expression+    template: ~ARG[0] or ~ARG[1]+- BlackBox:+    name: GHC.Prim.xorWord8#+    kind: Expression+    template: ~ARG[0] xor ~ARG[1]+- BlackBox:+    name: GHC.Prim.notWord8#+    kind: Expression+    template: not ~ARG[0]+- BlackBox:+    name: GHC.Prim.uncheckedShiftLWord8#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= shift_left(~ARG[0],~SYM[1])+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.uncheckedShiftRLWord8#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftRL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= ~ARG[0] srl ~SYM[1]+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.word8ToInt8#+    kind: Expression+    template: signed(std_logic_vector(~ARG[0]))+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqWord8#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] = ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.geWord8#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] >= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.gtWord8#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] > ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.leWord8#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] <= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.ltWord8#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] < ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.neWord8#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] /= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.int16ToInt#+    kind: Expression+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.intToInt16#+    kind: Expression+    template: ~VAR[i][0](15 downto 0)+    workInfo: Never+- BlackBox:+    name: GHC.Prim.negateInt16#+    kind: Expression+    template: -~ARG[0]+- BlackBox:+    name: GHC.Prim.timesInt16#+    kind: Expression+    template: resize(~ARG[0] * ~ARG[1],~SIZE[~TYPO])+- BlackBox:+    name: GHC.Prim.quotInt16#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] / ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.remInt16#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] rem ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.quotRemInt16#+    kind: Declaration+    template: |-+      ~RESULT <= (~ARG[0] / ~ARG[1], ~ARG[0] rem ~ARG[1])+          -- pragma translate_off+          when (~ARG[1] /= 0) else ((others => 'X'), (others => 'X'))+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.uncheckedShiftLInt16#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= shift_left(~ARG[0],~SYM[1])+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.uncheckedShiftRAInt16#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftR][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= shift_right(~ARG[0],~SYM[1])+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.uncheckedShiftRLInt16#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftRL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= ~ARG[0] srl ~SYM[1]+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.int16ToWord16#+    kind: Expression+    template: unsigned(std_logic_vector(~ARG[0]))+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqInt16#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] = ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.geInt16#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] >= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.gtInt16#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] > ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.leInt16#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] <= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.ltInt16#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] < ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.neInt16#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] /= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.word16ToWord#+    kind: Expression+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.wordToWord16#+    kind: Expression+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.timesWord16#+    kind: Expression+    template: resize(~ARG[0] * ~ARG[1],~SIZE[~TYPO])+- BlackBox:+    name: GHC.Prim.quotWord16#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] / ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.remWord16#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] rem ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.quotRemWord16#+    kind: Declaration+    template: |-+      ~RESULT <= (~ARG[0] / ~ARG[1], ~ARG[0] rem ~ARG[1])+          -- pragma translate_off+          when (~ARG[1] /= 0) else ((others => 'X'), (others => 'X'))+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.andWord16#+    kind: Expression+    template: ~ARG[0] and ~ARG[1]+- BlackBox:+    name: GHC.Prim.orWord16#+    kind: Expression+    template: ~ARG[0] or ~ARG[1]+- BlackBox:+    name: GHC.Prim.xorWord16#+    kind: Expression+    template: ~ARG[0] xor ~ARG[1]+- BlackBox:+    name: GHC.Prim.notWord16#+    kind: Expression+    template: not ~ARG[0]+- BlackBox:+    name: GHC.Prim.uncheckedShiftLWord16#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= shift_left(~ARG[0],~SYM[1])+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.uncheckedShiftRLWord16#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftRL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= ~ARG[0] srl ~SYM[1]+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.word16ToInt16#+    kind: Expression+    template: signed(std_logic_vector(~ARG[0]))+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqWord16#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] = ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.geWord16#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] >= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.gtWord16#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] > ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.leWord16#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] <= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.ltWord16#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] < ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.neWord16#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] /= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.int32ToInt#+    kind: Expression+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.intToInt32#+    kind: Expression+    template: ~VAR[i][0](31 downto 0)+    workInfo: Never+- BlackBox:+    name: GHC.Prim.negateInt32#+    kind: Expression+    template: -~ARG[0]+- BlackBox:+    name: GHC.Prim.timesInt32#+    kind: Expression+    template: resize(~ARG[0] * ~ARG[1],~SIZE[~TYPO])+- BlackBox:+    name: GHC.Prim.quotInt32#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] / ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.remInt32#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] rem ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.quotRemInt32#+    kind: Declaration+    template: |-+      ~RESULT <= (~ARG[0] / ~ARG[1], ~ARG[0] rem ~ARG[1])+          -- pragma translate_off+          when (~ARG[1] /= 0) else ((others => 'X'), (others => 'X'))+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.uncheckedShiftLInt32#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= shift_left(~ARG[0],~SYM[1])+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.uncheckedShiftRAInt32#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftR][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= shift_right(~ARG[0],~SYM[1])+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.uncheckedShiftRLInt32#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftRL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= ~ARG[0] srl ~SYM[1]+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.int32ToWord32#+    kind: Expression+    template: unsigned(std_logic_vector(~ARG[0]))+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqInt32#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] = ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.geInt32#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] >= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.gtInt32#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] > ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.leInt32#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] <= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.ltInt32#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] < ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.neInt32#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] /= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.word32ToWord#+    kind: Expression+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.wordToWord32#+    kind: Expression+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.timesWord32#+    kind: Expression+    template: resize(~ARG[0] * ~ARG[1],~SIZE[~TYPO])+- BlackBox:+    name: GHC.Prim.quotWord32#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] / ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.remWord32#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] rem ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.quotRemWord32#+    kind: Declaration+    template: |-+      ~RESULT <= (~ARG[0] / ~ARG[1], ~ARG[0] rem ~ARG[1])+          -- pragma translate_off+          when (~ARG[1] /= 0) else ((others => 'X'), (others => 'X'))+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.andWord32#+    kind: Expression+    template: ~ARG[0] and ~ARG[1]+- BlackBox:+    name: GHC.Prim.orWord32#+    kind: Expression+    template: ~ARG[0] or ~ARG[1]+- BlackBox:+    name: GHC.Prim.xorWord32#+    kind: Expression+    template: ~ARG[0] xor ~ARG[1]+- BlackBox:+    name: GHC.Prim.notWord32#+    kind: Expression+    template: not ~ARG[0]+- BlackBox:+    name: GHC.Prim.uncheckedShiftLWord32#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= shift_left(~ARG[0],~SYM[1])+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.uncheckedShiftRLWord32#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftRL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= ~ARG[0] srl ~SYM[1]+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.word32ToInt32#+    kind: Expression+    template: signed(std_logic_vector(~ARG[0]))+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqWord32#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] = ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.geWord32#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] >= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.gtWord32#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] > ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.leWord32#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] <= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.ltWord32#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] < ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.neWord32#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] /= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.int64ToInt#+    kind: Expression+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.intToInt64#+    kind: Expression+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.negateInt64#+    kind: Expression+    template: -~ARG[0]+- BlackBox:+    name: GHC.Prim.timesInt64#+    kind: Expression+    template: resize(~ARG[0] * ~ARG[1],~SIZE[~TYPO])+- BlackBox:+    name: GHC.Prim.quotInt64#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] / ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.remInt64#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] rem ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.quotRemInt64#+    kind: Declaration+    template: |-+      ~RESULT <= (~ARG[0] / ~ARG[1], ~ARG[0] rem ~ARG[1])+          -- pragma translate_off+          when (~ARG[1] /= 0) else ((others => 'X'), (others => 'X'))+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.uncheckedIShiftL64#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= shift_left(~ARG[0],~SYM[1])+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.uncheckedIShiftRA64#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftR][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= shift_right(~ARG[0],~SYM[1])+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.uncheckedIShiftRL64#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftRL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= ~ARG[0] srl ~SYM[1]+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.int64ToWord64#+    kind: Expression+    template: unsigned(std_logic_vector(~ARG[0]))+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqInt64#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] = ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.geInt64#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] >= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.gtInt64#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] > ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.leInt64#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] <= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.ltInt64#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] < ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.neInt64#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] /= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.word64ToWord#+    kind: Expression+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.wordToWord64#+    kind: Expression+    template: resize(~ARG[0],~SIZE[~TYPO])+    workInfo: Never+- BlackBox:+    name: GHC.Prim.timesWord64#+    kind: Expression+    template: resize(~ARG[0] * ~ARG[1],~SIZE[~TYPO])+- BlackBox:+    name: GHC.Prim.quotWord64#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] / ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.remWord64#+    kind: Declaration+    template: |-+      ~RESULT <= ~ARG[0] rem ~ARG[1]+          -- pragma translate_off+          when (~ARG[1] /= 0) else (others => 'X')+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.quotRemWord64#+    kind: Declaration+    template: |-+      ~RESULT <= (~ARG[0] / ~ARG[1], ~ARG[0] rem ~ARG[1])+          -- pragma translate_off+          when (~ARG[1] /= 0) else ((others => 'X'), (others => 'X'))+          -- pragma translate_on+          ;+- BlackBox:+    name: GHC.Prim.and64#+    kind: Expression+    template: ~ARG[0] and ~ARG[1]+- BlackBox:+    name: GHC.Prim.or64#+    kind: Expression+    template: ~ARG[0] or ~ARG[1]+- BlackBox:+    name: GHC.Prim.xor64#+    kind: Expression+    template: ~ARG[0] xor ~ARG[1]+- BlackBox:+    name: GHC.Prim.not64#+    kind: Expression+    template: not ~ARG[0]+- BlackBox:+    name: GHC.Prim.uncheckedShiftL64#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= shift_left(~ARG[0],~SYM[1])+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.uncheckedShiftRL64#+    kind: Declaration+    template: |-+      ~GENSYM[~RESULT_shiftRL][0] : block+        signal ~GENSYM[sh][1] : natural;+      begin+        ~SYM[1] <=+            -- pragma translate_off+            natural'high when (~VAR[shI][1](~SIZE[~TYP[1]]-1 downto 31) /= 0) else+            -- pragma translate_on+            to_integer(~VAR[shI][1]);+        ~RESULT <= ~ARG[0] srl ~SYM[1]+            -- pragma translate_off+            when (~ARG[1] >= 0) else (others => 'X')+            -- pragma translate_on+            ;+      end block;+- BlackBox:+    name: GHC.Prim.word64ToInt64#+    kind: Expression+    template: signed(std_logic_vector(~ARG[0]))+    workInfo: Never+- BlackBox:+    name: GHC.Prim.eqWord64#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] = ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.geWord64#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] >= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.gtWord64#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] > ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.leWord64#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] <= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.ltWord64#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] < ~ARG[1] else to_signed(0,~SIZE[~TYPO]);+- BlackBox:+    name: GHC.Prim.neWord64#+    kind: Declaration+    template: ~RESULT <= to_signed(1,~SIZE[~TYPO]) when ~ARG[0] /= ~ARG[1] else to_signed(0,~SIZE[~TYPO]);

@@ -2,6 +2,7 @@   Copyright  :  (C) 2015-2016, University of Twente,                     2017     , Myrtle Software Ltd, Google Inc.,                     2021-2022, QBayLogic B.V.+                    2022     , Google Inc.   License    :  BSD2 (see the file LICENSE)   Maintainer :  QBayLogic B.V. <devops@qbaylogic.com> -}@@ -13,6 +14,7 @@  import Data.HashMap.Strict                  (HashMap, empty) import Data.HashSet                         (HashSet)+import Control.Lens                         (Lens') import Data.Monoid                          (Ap) import Data.Text                            (Text) import qualified Data.Text.Lazy             as LT@@ -27,7 +29,7 @@  import Clash.Driver.Types (ClashOpts) import {-# SOURCE #-} Clash.Netlist.Types-  (Component, Declaration, Expr, HWType, Identifier, IdentifierSet, HasIdentifierSet)+  (Component, Declaration, Expr, HWType, Identifier, IdentifierSet, HasIdentifierSet, UsageMap) import Clash.Netlist.BlackBox.Types  import Clash.Signal.Internal                (VDomainConfiguration)@@ -87,7 +89,10 @@ emptyDomainMap :: DomainMap emptyDomainMap = empty -class HasIdentifierSet state => Backend state where+class HasUsageMap s where+  usageMap :: Lens' s UsageMap++class (HasUsageMap state, HasIdentifierSet state) => Backend state where   -- | Initial state for state monad   initBackend :: ClashOpts -> state @@ -108,7 +113,7 @@   extractTypes     :: state -> HashSet HWType    -- | Generate HDL for a Netlist component-  genHDL           :: ModName -> SrcSpan -> IdentifierSet -> Component -> Ap (State state) ((String, Doc),[(String,Doc)])+  genHDL           :: ClashOpts -> ModName -> SrcSpan -> IdentifierSet -> UsageMap -> Component -> Ap (State state) ((String, Doc),[(String,Doc)])   -- | Generate a HDL package containing type definitions for the given HWTypes   mkTyPackage      :: ModName -> [HWType] -> Ap (State state) [(String, Doc)]   -- | Convert a Netlist HWType to a target HDL type

@@ -1,7 +1,8 @@ {-|   Copyright   :  (C) 2015-2016, University of Twente,                      2017-2018, Google Inc.,-                     2021-2022, QBayLogic B.V.+                     2021-2023, QBayLogic B.V.,+                     2022     , Google Inc.   License     :  BSD2 (see the file LICENSE)   Maintainer  :  QBayLogic B.V. <devops@qbaylogic.com> @@ -48,18 +49,19 @@   (bitsToBits) import           Clash.Annotations.BitRepresentation.Util   (BitOrigin(Lit, Field), bitOrigins, bitRanges)-import           Clash.Core.Var                       (Attr'(..))+import           Clash.Annotations.SynthesisAttributes (Attr(..)) import           Clash.Debug                          (traceIf) import           Clash.Backend import           Clash.Backend.Verilog   (bits, bit_char, encodingNote, exprLit, include, noEmptyInit, uselibs)+import           Clash.Backend.Verilog.Time           (periodToString) import           Clash.Driver.Types                   (ClashOpts(..)) import           Clash.Explicit.BlockRam.Internal     (unpackNats) import           Clash.Netlist.BlackBox.Types         (HdlSyn (..)) import           Clash.Netlist.BlackBox.Util   (extractLiterals, renderBlackBox, renderFilePath) import qualified Clash.Netlist.Id                     as Id-import           Clash.Netlist.Types                  hiding (intWidth)+import           Clash.Netlist.Types                  hiding (intWidth, usages, _usages) import           Clash.Netlist.Util import           Clash.Signal.Internal                (ActiveEdge (..)) import           Clash.Util@@ -93,6 +95,7 @@     , _aggressiveXOptBB_ :: AggressiveXOptBB     , _renderEnums_ :: RenderEnums     , _domainConfigurations_ :: DomainMap+    , _usages :: UsageMap     }  makeLenses ''SystemVerilogState@@ -100,6 +103,9 @@ instance HasIdentifierSet SystemVerilogState where   identifierSet = idSeen +instance HasUsageMap SystemVerilogState where+  usageMap = usages+ instance Backend SystemVerilogState where   initBackend opts = SystemVerilogState     { _tyCache=HashSet.empty@@ -122,6 +128,7 @@     , _aggressiveXOptBB_=coerce (opt_aggressiveXOptBB opts)     , _renderEnums_=coerce (opt_renderEnums opts)     , _domainConfigurations_=emptyDomainMap+    , _usages=mempty     }   hdlKind         = const SystemVerilog   primDirs        = const $ do root <- primsRoot@@ -197,33 +204,40 @@  -- | Generate SystemVerilog for a Netlist component genSystemVerilog-  :: ModName+  :: ClashOpts+  -> ModName   -> SrcSpan   -> IdentifierSet+  -> UsageMap   -> Component   -> SystemVerilogM ((String, Doc), [(String, Doc)])-genSystemVerilog _ sp seen c = do+genSystemVerilog opts _ sp seen us c = do     -- Don't have type names conflict with module names or with previously     -- generated type names.     --     -- TODO: Collect all type names up front, to prevent relatively costly union.     -- TODO: Investigate whether type names / signal names collide in the first place-    Ap $ idSeen %= Id.union seen+    Ap $ do+      idSeen %= Id.union seen+      usages .= us+      setSrcSpan sp -    Ap $ setSrcSpan sp     v    <- verilog     incs <- Ap $ use includes     return ((TextS.unpack (Id.toText cName), v), incs)   where     cName   = componentName c     verilog = commentHeader <> line <>+              nettype <> line <>               timescale <> line <>               module_ c     commentHeader          = "/* AUTOMATICALLY GENERATED SYSTEMVERILOG-2005 SOURCE CODE."       <> line <> "** GENERATED BY CLASH " <> string (Text.pack clashVer) <> ". DO NOT MODIFY."       <> line <> "*/"-    timescale = "`timescale 100fs/100fs"+    nettype = "`default_nettype none"+    timescale = "`timescale 100fs/" <> string (Text.pack precision)+    precision = periodToString (opt_timescalePrecision opts)  -- | Generate a SystemVerilog package containing type definitions for the given HWTypes mkTyPackage_ :: TextS.Text -> [HWType] -> SystemVerilogM [(String,Doc)]@@ -316,6 +330,7 @@ normaliseType ty@(Sum _ _) = return (BitVector (typeSize ty)) normaliseType ty@(CustomSum _ _ _ _) = return (BitVector (typeSize ty)) normaliseType (Clock _) = return Bit+normaliseType (ClockN _) = return Bit normaliseType (Reset _) = return Bit normaliseType (Enable _) = return Bool normaliseType (BiDirectional dir ty) = BiDirectional dir <$> normaliseType ty@@ -380,6 +395,7 @@       Product {} -> (ns, verilogType t)       Vector {}  -> error $ $(curLoc) ++ "impossible"       Clock {}   -> (ns, verilogType t)+      ClockN {}  -> (ns, verilogType t)       Reset {}   -> (ns, "logic")       Enable {}  -> (ns, "logic")       Bool       -> (ns, "logic")@@ -522,13 +538,21 @@   modEnding  = "endmodule"    inPorts  = sequence [ sigPort (Nothing,isBiSignalIn ty) (i,ty) Nothing | (i,ty)  <- inputs c  ]-  outPorts = sequence [ sigPort (Just wr,False) p iEM | (wr, p, iEM) <- outputs c ]+  outPorts = sequence [ sigPort (Just u,False) p iEM | (u, p, iEM) <- outputs c ] +  -- NOTE [net types and data types]+  --+  -- SystemVerilog makes a distinction between the type of a net and the data+  -- type of a signal. For output ports / inout ports this is fine, as there+  -- is only one possible type. For input ports when using `default_nettype none+  -- we have to specify the net type as wire explicitly (or vendor tools will+  -- claim the net from the port declaration is implicitly defined).+   wr2ty (Nothing,isBidirectional)     | isBidirectional-    = "inout"+    = "inout" -- no net type here, it gets added by verilogType.     | otherwise-    = "input"+    = "input wire" -- See NOTE [net types and data types]   wr2ty (Just _,_)     = "output" @@ -574,6 +598,7 @@     RTree {}      -> pvrType     Signed n      -> logicOrWire <+> "signed" <+> brackets (int (n-1) <> colon <> int 0)     Clock _       -> "logic"+    ClockN _      -> "logic"     Reset _       -> "logic"     Enable _      -> "logic"     Bit           -> "logic"@@ -623,6 +648,7 @@  tyName t@(SP _ _) = "logic_vector_" <> int (typeSize t) tyName (Clock _)  = "logic"+tyName (ClockN _) = "logic" tyName (Reset _)  = "logic" tyName (Enable _) = "logic" tyName t =  error $ $(curLoc) ++ "tyName: " ++ show t@@ -665,35 +691,34 @@       _  -> punctuate' semi (A.pure dsDoc)  decl :: Declaration -> SystemVerilogM (Maybe Doc)-decl (NetDecl' noteM _ id_ tyE iEM) =+decl (NetDecl' noteM id_ tyE iEM) =   Just A.<$> maybe id addNote noteM (addAttrs attrs (typ tyE))   where-    typ (Left  ty) = stringS ty <+> pretty id_ <> iE-    typ (Right ty) = sigDecl (pretty id_) ty <> iE+    typ ty = sigDecl (pretty id_) ty <> iE     addNote n = mappend ("//" <+> stringS n <> line)-    attrs = fromMaybe [] (hwTypeAttrs A.<$> either (const Nothing) Just tyE)+    attrs = fromMaybe [] (hwTypeAttrs A.<$> Just tyE)     iE = maybe emptyDoc (noEmptyInit . expr_ False) iEM  decl _ = return Nothing  -- | Convert single attribute to systemverilog syntax-renderAttr :: Attr' -> Text.Text-renderAttr (StringAttr'  key value) = Text.pack $ concat [key, " = ", show value]-renderAttr (IntegerAttr' key value) = Text.pack $ concat [key, " = ", show value]-renderAttr (BoolAttr'    key True ) = Text.pack $ concat [key, " = ", "1"]-renderAttr (BoolAttr'    key False) = Text.pack $ concat [key, " = ", "0"]-renderAttr (Attr'        key      ) = Text.pack $ key+renderAttr :: Attr TextS.Text -> TextS.Text+renderAttr (StringAttr  key value) = TextS.concat [key, " = ", TextS.pack (show value)]+renderAttr (IntegerAttr key value) = TextS.concat [key, " = ", TextS.pack (show value)]+renderAttr (BoolAttr    key True ) = TextS.concat [key, " = ", "1"]+renderAttr (BoolAttr    key False) = TextS.concat [key, " = ", "0"]+renderAttr (Attr        key      ) = key  -- | Add attribute notation to given declaration addAttrs-  :: [Attr']+  :: [Attr TextS.Text]   -> SystemVerilogM Doc   -> SystemVerilogM Doc addAttrs []     t = t addAttrs attrs' t =   "(*" <+> attrs'' <+> "*)" <+> t     where-      attrs'' = string $ Text.intercalate ", " (map renderAttr attrs')+      attrs'' = stringS $ TextS.intercalate ", " (map renderAttr attrs')  insts :: [Declaration] -> SystemVerilogM Doc insts [] = emptyDoc@@ -777,7 +802,9 @@ inst_ :: Declaration -> SystemVerilogM (Maybe Doc) inst_ (TickDecl {}) = return Nothing -inst_ (Assignment id_ e) = fmap Just $+inst_ (CompDecl {}) = return Nothing++inst_ (Assignment id_ Cont e) = fmap Just $   "assign" <+> pretty id_ <+> equals <+> align (expr_ False e <> semi)  inst_ (CondAssignment id_ ty scrut _ [(Just (BoolLit b), l),(_,r)]) = fmap Just $ do@@ -868,6 +895,9 @@ inst_ (ConditionalDecl cond ds) = Just <$>   "`ifdef" <+> pretty cond <> line <> indent 2 (insts ds) <> line <> "`endif" +inst_ d =+  error ("inst_: " ++ show d)+ -- | Render a data constructor application for data constructors having a -- custom bit representation. customReprDataCon@@ -952,8 +982,9 @@           "end") <:> conds es'  seq_ (SeqDecl sd) = case sd of-  Assignment id_ e ->-    pretty id_ <+> equals <+> expr_ False e <> semi+  Assignment id_ (Proc b) e ->+    let sym = case b of { Blocking -> equals; NonBlocking -> "<=" }+     in pretty id_ <+> sym <+> expr_ False e <> semi    BlackBoxD {} ->     fromMaybe <$> emptyDoc <*> inst_ sd@@ -1116,10 +1147,10 @@  expr_ _ (DataCon ty@(Vector 0 _) _ _) = verilogTypeErrValue ty -expr_ _ (DataCon (Vector 1 elTy) _ [e]) = "'" <> braces (toSLV elTy e)+expr_ _ (DataCon (Vector 1 elTy) _ [e]) = "'" <> braces (int 0 <> colon <+> toSLV elTy e)  expr_ _ e@(DataCon ty@(Vector _ elTy) _ [e1,e2]) = case vectorChain e of-  Just es -> "'" <> listBraces (mapM (toSLV elTy) es)+  Just es -> "'" <> listBraces (zipWithM (\i e3 -> int i <> colon <+> toSLV elTy e3) [0..] es)   Nothing -> verilogTypeMark ty <> "_cons" <> parens (expr_ False e1 <> comma <+> expr_ False e2)  expr_ _ (DataCon (MemBlob n m) _ [n0, m0, _, runs, _, ends])@@ -1190,9 +1221,9 @@ expr_ _ (BlackBoxE pNm _ _ _ _ bbCtx _)   | pNm == "Clash.Sized.Internal.BitVector.fromInteger##"   , [Literal _ m, Literal _ i] <- extractLiterals bbCtx-  = let NumLit m' = m-        NumLit i' = i-    in exprLitSV (Just (Bit,1)) (BitLit $ toBit m' i')+  , NumLit m' <- m+  , NumLit i' <- i+  = exprLitSV (Just (Bit,1)) (BitLit $ toBit m' i')  expr_ _ (BlackBoxE pNm _ _ _ _ bbCtx _)   | pNm == "Clash.Sized.Internal.Index.fromInteger#"

@@ -1,7 +1,8 @@ {-|   Copyright   :  (C) 2015-2016, University of Twente,                      2017-2018, Google Inc.,-                     2021-2022, QBayLogic B.V.+                     2021-2023, QBayLogic B.V.+                     2022     , Google Inc.   License     :  BSD2 (see the file LICENSE)   Maintainer  :  QBayLogic B.V. <devops@qbaylogic.com> @@ -20,7 +21,9 @@ module Clash.Backend.VHDL (VHDLState) where  import           Control.Arrow                        (second)+#if !MIN_VERSION_base(4,18,0) import           Control.Applicative                  (liftA2)+#endif import           Control.Lens                         hiding (Indexed, Empty) import           Control.Monad                        (forM,join,zipWithM) import           Control.Monad.State                  (State, StateT)@@ -35,7 +38,7 @@ import           Data.HashSet                         (HashSet) import qualified Data.HashSet                         as HashSet import           Data.List-  (mapAccumL, nub, nubBy, intersperse, group, sort)+  (mapAccumL, nub, nubBy, partition, intersperse, group, sort) import           Data.List.Extra                      ((<:>), equalLength, zipEqual) import           Data.Maybe                           (catMaybes,mapMaybe) import           Data.Monoid                          (Ap(Ap))@@ -62,8 +65,8 @@   (bitsToBits) import           Clash.Annotations.BitRepresentation.Util   (BitOrigin(Lit, Field), bitOrigins, bitRanges)+import           Clash.Annotations.SynthesisAttributes (Attr(..)) import           Clash.Backend-import           Clash.Core.Var                       (Attr'(..),attrName) import           Clash.Debug                          (traceIf) import           Clash.Driver.Types                   (ClashOpts(..)) import           Clash.Explicit.BlockRam.Internal     (unpackNats)@@ -71,7 +74,7 @@ import           Clash.Netlist.BlackBox.Util   (extractLiterals, renderBlackBox, renderFilePath) import qualified Clash.Netlist.Id                     as Id-import           Clash.Netlist.Types                  hiding (intWidth)+import           Clash.Netlist.Types                  hiding (intWidth, usages, _usages) import           Clash.Netlist.Util import           Clash.Util   (SrcSpan, noSrcSpan, clogBase, curLoc, makeCached, indexNote)@@ -115,6 +118,7 @@   , _aggressiveXOptBB_ :: AggressiveXOptBB   , _renderEnums_ :: RenderEnums   , _domainConfigurations_ :: DomainMap+  , _usages :: UsageMap   }  makeLenses ''VHDLState@@ -122,6 +126,9 @@ instance HasIdentifierSet VHDLState where   identifierSet = idSeen +instance HasUsageMap VHDLState where+  usageMap = usages+ instance Backend VHDLState where   initBackend opts = VHDLState     { _tyCache=mempty@@ -144,6 +151,7 @@     , _aggressiveXOptBB_=coerce (opt_aggressiveXOptBB opts)     , _renderEnums_=coerce (opt_renderEnums opts)     , _domainConfigurations_=emptyDomainMap+    , _usages=mempty     }   hdlKind         = const VHDL   primDirs        = const $ do root <- primsRoot@@ -169,6 +177,7 @@       if enums then pure UserType else pure SynonymType      Clock {} -> pure SynonymType+    ClockN {} -> pure SynonymType     Reset {} -> pure SynonymType     Enable {} -> pure SynonymType     Index {} -> pure SynonymType@@ -242,20 +251,28 @@   blockDecl nm ds = do     decs <- decls ds     let attrs = [ (id_, attr)-                | NetDecl' _ _ id_ (Right hwtype) _ <- ds+                | NetDecl' _ id_ hwtype _ <- ds                 , attr <- hwTypeAttrs hwtype]     if isEmpty decs-       then insts ds+       then insts ids        else nest 2               (pretty nm <+> colon <+> "block" <> line <>                pure decs <>-               if null attrs+               (if null attrs                 then emptyDoc-                else line <> line <> renderAttrs (TextS.pack "signal") attrs) <> line <>-            nest 2-              ("begin" <> line <>-                insts ds) <> line <>+                else line <> line <> renderAttrs (TextS.pack "signal") attrs) <>+               if null cds+                then emptyDoc+                else line <> line <> insts cds) <> line <> "begin" <>+            nest 2 (line <> insts ids)+            <> line <>             "end block" <> semi+   where+     (cds, ids) = partition isCompDecl ds++     isCompDecl (CompDecl {}) = True+     isCompDecl _             = False+   addIncludes inc = includes %= (inc++)   addLibraries libs = libraries %= (libs ++)   addImports imps = packages %= (imps ++)@@ -282,7 +299,7 @@  -- | Generate unique (partial) names for product fields. Example: ----- >>> productFieldNames [Unsigned 6, Unsigned 6, Bit, Bool]+-- > productFieldNames Nothing [Unsigned 6, Unsigned 6, Bit, Bool] -- ["unsigned6_0", "unsigned6_1", "bit", "boolean"] productFieldNames   :: HasCallStack@@ -296,7 +313,9 @@   hFields <- zipWithM hName labels1 fields    let grouped = group $ sort $ hFields-      counted = HashMapS.fromList (map (\(g:gs) -> (g, succ (length gs))) grouped)+      countGroup [] = error "productFIeldNames.countGroup: group of zero elements"+      countGroup (g:gs) = (g, succ (length gs))+      counted = HashMapS.fromList (map countGroup grouped)       names   = snd $ mapAccumL (name' counted) HashMapS.empty hFields    return names@@ -373,20 +392,24 @@  -- | Generate VHDL for a Netlist component genVHDL-  :: ModName+  :: ClashOpts+  -> ModName   -> SrcSpan   -> IdentifierSet+  -> UsageMap   -> Component   -> VHDLM ((String, Doc), [(String, Doc)])-genVHDL nm sp seen c = do+genVHDL _ nm sp seen us c = do     -- Don't have type names conflict with module names or with previously     -- generated type names.     --     -- TODO: Collect all type names up front, to prevent relatively costly union.     -- TODO: Investigate whether type names / signal names collide in the first place-    Ap $ idSeen %= Id.union seen+    Ap $ do+      idSeen %= Id.union seen+      usages .= us+      setSrcSpan sp -    Ap $ setSrcSpan sp     v <- vhdl     i <- Ap $ use includes     Ap $ libraries .= []@@ -579,6 +602,7 @@      -- Type aliases:     Clock _           -> typAliasDec hwty+    ClockN _          -> typAliasDec hwty     Reset _           -> typAliasDec hwty     Enable _          -> typAliasDec hwty     Index _           -> typAliasDec hwty@@ -721,8 +745,9 @@                             parens ("p." <> tyName t <> selectProductField labels elTys i))      argLengths = map typeSize elTys-    starts     = 0 : snd (mapAccumL ((join (,) .) . (+)) 0 argLengths)-    ends       = map (subtract 1) (tail starts)+    starts1    = snd (mapAccumL ((join (,) .) . (+)) 0 argLengths)+    starts     = 0 : starts1+    ends       = map (subtract 1) starts1      elTyFromSLV = forM (zip starts ends)                        (\(s,e) -> "fromSLV" <>@@ -940,7 +965,7 @@     rattrs      = renderAttrs (TextS.pack "signal") attrs     attrs       = inputAttrs ++ outputAttrs     inputAttrs  = [(id_, attr) | (id_, hwtype) <- inputs c, attr <- hwTypeAttrs hwtype]-    outputAttrs = [(id_, attr) | (_wireOrReg, (id_, hwtype), _) <- outputs c, attr <- hwTypeAttrs hwtype]+    outputAttrs = [(id_, attr) | (_, (id_, hwtype), _) <- outputs c, attr <- hwTypeAttrs hwtype]   architecture :: Component -> VHDLM Doc@@ -961,46 +986,52 @@   }  where    netdecls    = filter isNetDecl (declarations c)-   declAttrs   = [(id_, attr) | NetDecl' _ _ id_ (Right hwtype) _ <- netdecls, attr <- hwTypeAttrs hwtype]+   declAttrs   = [(id_, attr) | NetDecl' _ id_ hwtype _ <- netdecls, attr <- hwTypeAttrs hwtype]    inputAttrs  = [(id_, attr) | (id_, hwtype) <- inputs c, attr <- hwTypeAttrs hwtype]-   outputAttrs = [(id_, attr) | (_wireOrReg, (id_, hwtype), _) <- outputs c, attr <- hwTypeAttrs hwtype]+   outputAttrs = [(id_, attr) | (_, (id_, hwtype), _) <- outputs c, attr <- hwTypeAttrs hwtype]     isNetDecl :: Declaration -> Bool-   isNetDecl (NetDecl' _ _ _ (Right _) _) = True-   isNetDecl _                            = False+   isNetDecl NetDecl'{} = True+   isNetDecl _          = False -attrType-  :: t ~ HashMap T.Text T.Text-  => t-  -> Attr'-  -> t+attrType ::+  HashMap TextS.Text TextS.Text ->+  Attr TextS.Text ->+  HashMap TextS.Text TextS.Text attrType types attr =   case HashMap.lookup name' types of     Nothing    -> HashMap.insert name' type' types     Just type'' | type'' == type' -> types                 | otherwise -> error $-                      $(curLoc) ++ unwords [ T.unpack name', "already assigned"-                                           , T.unpack type'', "while we tried to"-                                           , "add", T.unpack type' ]+                      $(curLoc) ++ unwords [ TextS.unpack name', "already assigned"+                                           , TextS.unpack type'', "while we tried to"+                                           , "add", TextS.unpack type' ]  where-  name' = T.pack $ attrName attr-  type' = T.pack $ case attr of-            BoolAttr' _ _    -> "boolean"-            IntegerAttr' _ _ -> "integer"-            StringAttr' _ _  -> "string"-            Attr' _          -> "bool"+  name' = attrName attr+  type' = case attr of+            BoolAttr _ _    -> "boolean"+            IntegerAttr _ _ -> "integer"+            StringAttr _ _  -> "string"+            Attr _          -> "boolean" +attrName :: Attr a -> a+attrName = \case+  BoolAttr a _ -> a+  IntegerAttr a _ -> a+  StringAttr a _ -> a+  Attr a -> a+ -- | Create 'attrname -> type' mapping for given attributes. Will err if multiple -- types are assigned to the same name.-attrTypes :: [Attr'] -> HashMap T.Text T.Text+attrTypes :: [Attr TextS.Text] -> HashMap TextS.Text TextS.Text attrTypes = foldl attrType HashMap.empty  -- | Create a 'attrname -> (type, [(signalname, value)]). Will err if multiple -- types are assigned to the same name. attrMap   :: forall t-   . t ~ HashMap T.Text (T.Text, [(TextS.Text, T.Text)])-  => [(Identifier, Attr')]+   . t ~ HashMap TextS.Text (TextS.Text, [(TextS.Text, TextS.Text)])+  => [(Identifier, Attr TextS.Text)]   -> t attrMap attrs0 = foldl go empty' attrs1  where@@ -1010,56 +1041,57 @@            [(k, (types HashMap.! k, [])) | k <- HashMap.keys types]   types = attrTypes (map snd attrs1) -  go :: t -> (TextS.Text, Attr') -> t-  go map' attr = HashMap.adjust-                   (go' attr)-                   (T.pack $ attrName $ snd attr)-                   map'+  go :: t -> (TextS.Text, Attr TextS.Text) -> t+  go map' attr = HashMap.adjust (go' attr) (attrName $ snd attr) map'    go'-    :: (TextS.Text, Attr')-    -> (T.Text, [(TextS.Text, T.Text)])-    -> (T.Text, [(TextS.Text, T.Text)])+    :: (TextS.Text, Attr TextS.Text)+    -> (TextS.Text, [(TextS.Text, TextS.Text)])+    -> (TextS.Text, [(TextS.Text, TextS.Text)])   go' (signalName, attr) (typ, elems) =     (typ, (signalName, renderAttr attr) : elems)  renderAttrs   :: TextS.Text-  -> [(Identifier, Attr')]+  -> [(Identifier, Attr TextS.Text)]   -> VHDLM Doc renderAttrs what (attrMap -> attrs) =   vcat $ sequence $ intersperse " " $ map renderAttrGroup (HashMap.toList attrs)  where   renderAttrGroup-    :: (T.Text, (T.Text, [(TextS.Text, T.Text)]))+    :: (TextS.Text, (TextS.Text, [(TextS.Text, TextS.Text)]))     -> VHDLM Doc   renderAttrGroup (attrname, (typ, elems)) =-    ("attribute" <+> string attrname <+> colon <+> string typ <> semi)+    ("attribute" <+> stringS attrname <+> colon <+> stringS typ <> semi)     <> line <>     (vcat $ sequence $ map (renderAttrDecl attrname) elems)    renderAttrDecl-    :: T.Text-    -> (TextS.Text, T.Text)+    :: TextS.Text+    -> (TextS.Text, TextS.Text)     -> VHDLM Doc   renderAttrDecl attrname (signalName, value) =         "attribute"-    <+> string attrname+    <+> stringS attrname     <+> "of"     <+> stringS signalName -- or component name     <+> colon     <+> stringS what <+> "is" -- "signal is" or "component is"-    <+> string value+    <+> stringS value     <> semi  -- | Convert single attribute to VHDL syntax-renderAttr :: Attr' -> T.Text-renderAttr (StringAttr'  _key value) = T.replace "\\\"" "\"\"" $ T.pack $ show value-renderAttr (IntegerAttr' _key value) = T.pack $ show value-renderAttr (BoolAttr'    _key True ) = T.pack $ "true"-renderAttr (BoolAttr'    _key False) = T.pack $ "false"-renderAttr (Attr'        _key      ) = T.pack $ "true"+renderAttr :: Attr TextS.Text -> TextS.Text+renderAttr (StringAttr  _key value) = wrap '"' $ TextS.replace "\"" "\"\"" value+renderAttr (IntegerAttr _key value) = TextS.pack (show value)+renderAttr (BoolAttr    _key True ) = "true"+renderAttr (BoolAttr    _key False) = "false"+renderAttr (Attr        _key      ) = "true" +-- | Prepend and append a character to a string+wrap :: Char -> TextS.Text -> TextS.Text+wrap c = cons c . (`snoc` c)+ sigDecl :: VHDLM Doc -> HWType -> VHDLM Doc sigDecl d t = d <+> colon <+> sizedQualTyName t @@ -1173,6 +1205,9 @@     Clock nm0 ->       let nm1 = "clk_" `TextS.append` nm0 in       Ap $ makeCached (t, False) nameCache (userTyName "clk" nm1 t)+    ClockN nm0 ->+      let nm1 = "clk_n_" `TextS.append` nm0 in+      Ap $ makeCached (t, False) nameCache (userTyName "clk" nm1 t)     Reset nm0 ->       let nm1 = "rst_" `TextS.append` nm0 in       Ap $ makeCached (t, False) nameCache (userTyName "rst" nm1 t)@@ -1225,6 +1260,7 @@    -- Simple types, for which a subtype (without qualifiers) will be made in VHDL:   Clock _           -> Bit+  ClockN _          -> Bit   Reset _           -> Bit   Enable _          -> Bool   Index _           -> Unsigned (typeSize hwty)@@ -1248,6 +1284,7 @@   Integer           -> hwty   Bit               -> hwty   Clock _           -> hwty+  ClockN _          -> hwty   Reset _           -> hwty   Enable _          -> hwty   Index _           -> hwty@@ -1275,8 +1312,8 @@       (map (second filterTransparent) constrs)    -- Transparent types:-  Annotated _ elTy -> elTy-  BiDirectional _ elTy -> elTy+  Annotated _ elTy -> filterTransparent elTy+  BiDirectional _ elTy -> filterTransparent elTy    Void {} -> hwty   KnownDomain {} -> hwty@@ -1326,6 +1363,7 @@   else     qualTyName t <> "'" <> parens (int 0 <+> "to" <+> int (typeSize t - 1) <+> rarrow <+> singularErrValue) sizedQualTyNameErrValue (Clock _)  = singularErrValue+sizedQualTyNameErrValue (ClockN _) = singularErrValue sizedQualTyNameErrValue (Reset _)  = singularErrValue sizedQualTyNameErrValue (Enable _) = singularErrValue sizedQualTyNameErrValue (Void {})  =@@ -1360,8 +1398,8 @@       _  -> vcat (pure dsDoc)  decl :: Int ->  Declaration -> VHDLM (Maybe (Doc,Int))-decl l (NetDecl' noteM _ id_ ty iEM) = Just <$> (,fromIntegral (TextS.length (Id.toText id_))) <$>-  maybe id addNote noteM ("signal" <+> fill l (pretty id_) <+> colon <+> either pretty sizedQualTyName ty <> iE <> semi)+decl l (NetDecl' noteM id_ ty iEM) = Just <$> (,fromIntegral (TextS.length (Id.toText id_))) <$>+  maybe id addNote noteM ("signal" <+> fill l (pretty id_) <+> colon <+> sizedQualTyName ty <> iE <> semi)   where     addNote n = mappend ("--" <+> pretty n <> line)     iE = maybe emptyDoc (noEmptyInit . expr_ False) iEM@@ -1384,7 +1422,9 @@     portDir In  = "in"     portDir Out = "out" -    attrs' = if null attrs then emptyDoc else renderAttrs (TextS.pack "component") [(nm, a) | a <- attrs]+    attrs'+      | null attrs = emptyDoc+      | otherwise = renderAttrs (TextS.pack "component") [(nm, a) | a <- attrs]  decl _ _ = return Nothing @@ -1479,9 +1519,16 @@  -- | Turn a Netlist Declaration to a VHDL concurrent block inst_ :: Declaration -> VHDLM (Maybe Doc)-inst_ (Assignment id_ e) = fmap Just $+inst_ (Assignment id_ Cont e) = fmap Just $   pretty id_ <+> larrow <+> align (expr_ False e) <> semi +inst_ (CompDecl nm ps0) =+  fmap Just $ "component" <+> pretty nm <+>+    ("port" <> line <> indent 2 (tupledSemi ps <> semi))+    <> line <> "end component" <> semi+  where ps = traverse (\(t,pd,ty) -> pretty t <+> ":" <+> ppd pd <+> sizedQualTyName ty) ps0+        ppd = \case { In -> "in"; Out -> "out"}+ inst_ (CondAssignment id_ _ scrut _ [(Just (BoolLit b), l),(_,r)]) = fmap Just $   pretty id_ <+> larrow            <+> align (vsep (sequence [expr_ False t <+> "when" <+>@@ -1706,16 +1753,16 @@ expr_ _ (BlackBoxE pNm _ _ _ _ bbCtx _)   | pNm == "Clash.Sized.Internal.BitVector.fromInteger#"   , [Literal _ (NumLit n), Literal _ m, Literal _ i] <- extractLiterals bbCtx-  = let NumLit m' = m-        NumLit i' = i-    in exprLit (Just (BitVector (fromInteger n),fromInteger n)) (BitVecLit m' i')+  , NumLit m' <- m+  , NumLit i' <- i+  = exprLit (Just (BitVector (fromInteger n),fromInteger n)) (BitVecLit m' i')  expr_ _ (BlackBoxE pNm _ _ _ _ bbCtx _)   | pNm == "Clash.Sized.Internal.BitVector.fromInteger##"   , [Literal _ m, Literal _ i] <- extractLiterals bbCtx-  = let NumLit m' = m-        NumLit i' = i-    in exprLit (Just (Bit,1)) (BitLit $ toBit m' i')+  , NumLit m' <- m+  , NumLit i' <- i+  = exprLit (Just (Bit,1)) (BitLit $ toBit m' i')  expr_ _ (BlackBoxE pNm _ _ _ _ bbCtx _)   | pNm == "Clash.Sized.Internal.Index.fromInteger#"@@ -1890,9 +1937,9 @@ bits = dquotes . hcat . mapM bit_char  toHex :: Int -> Integer -> String-toHex sz i =-  let Just d = clogBase 16 (2^sz)-  in  printf ("%0" ++ show d ++ "X") (abs i)+toHex sz i = case clogBase 16 (2^sz) of+  Just d -> printf ("%0" ++ show d ++ "X") (abs i)+  _ -> error "toHex: impossible"  hex :: String -> VHDLM Doc hex s = char 'x' <> dquotes (pretty (T.pack s))@@ -1905,7 +1952,7 @@   case udf of     Nothing -> char '-'     Just Nothing -> char '0'-    Just (Just i) -> "'" <> int i <> "'"+    Just (Just i) -> int i bit_char Z = char 'Z'  toSLV :: HasCallStack => HWType -> Expr -> VHDLM Doc@@ -1918,6 +1965,9 @@ toSLV (Clock {})    e = do   nm <- Ap $ use modNm   pretty nm <> "_types.toSLV" <> parens (expr_ False e)+toSLV (ClockN {})   e = do+  nm <- Ap $ use modNm+  pretty nm <> "_types.toSLV" <> parens (expr_ False e) toSLV (Reset {})    e = do   nm <- Ap $ use modNm   pretty (TextS.toLower nm) <> "_types.toSLV" <> parens (expr_ False e)@@ -2004,6 +2054,7 @@  encodingNote :: HWType -> VHDLM Doc encodingNote (Clock _)  = "-- clock" <> line+encodingNote (ClockN _) = "-- clock (neg phase)" <> line encodingNote (Reset _)  = "-- reset" <> line encodingNote (Enable _) = "-- enable" <> line encodingNote (Annotated _ t) = encodingNote t

@@ -1,7 +1,8 @@ {-|   Copyright   :  (C) 2015-2016, University of Twente,                      2017-2018, Google Inc.,-                     2021-2022, QBayLogic B.V.+                     2021-2023, QBayLogic B.V.+                     2022     , Google Inc.   License     :  BSD2 (see the file LICENSE)   Maintainer  :  QBayLogic B.V. <devops@qbaylogic.com> @@ -64,8 +65,9 @@   (ConstrRepr'(..), DataRepr'(..), ConstrRepr'(..)) import           Clash.Annotations.BitRepresentation.Util   (BitOrigin(Lit, Field), bitOrigins, bitRanges)-import           Clash.Core.Var                       (Attr'(..))+import           Clash.Annotations.SynthesisAttributes (Attr(..)) import           Clash.Backend+import           Clash.Backend.Verilog.Time           (periodToString) import           Clash.Debug                          (traceIf) import           Clash.Driver.Types                   (ClashOpts(..)) import           Clash.Explicit.BlockRam.Internal     (unpackNats)@@ -73,7 +75,7 @@ import           Clash.Netlist.BlackBox.Util   (extractLiterals, renderBlackBox, renderFilePath) import qualified Clash.Netlist.Id                     as Id-import           Clash.Netlist.Types                  hiding (intWidth)+import           Clash.Netlist.Types as N             hiding (intWidth, usages, _usages) import           Clash.Netlist.Util import           Clash.Signal.Internal                (ActiveEdge (..)) import           Clash.Util@@ -101,6 +103,7 @@     , _undefValue :: Maybe (Maybe Int)     , _aggressiveXOptBB_ :: AggressiveXOptBB     , _domainConfigurations_ :: DomainMap+    , _usages :: UsageMap     }  makeLenses ''VerilogState@@ -108,6 +111,9 @@ instance HasIdentifierSet VerilogState where   identifierSet = idSeen +instance HasUsageMap VerilogState where+  usageMap = usages+ instance Backend VerilogState where   initBackend opts = VerilogState     { _genDepth=0@@ -125,6 +131,7 @@     , _undefValue=opt_forceUndefined opts     , _aggressiveXOptBB_=coerce (opt_aggressiveXOptBB opts)     , _domainConfigurations_=emptyDomainMap+    , _usages=mempty     }   hdlKind         = const Verilog   primDirs        = const $ do root <- primsRoot@@ -136,7 +143,7 @@   name            = const "verilog"   extension       = const ".v" -  genHDL          = const genVerilog+  genHDL          = genVerilog   mkTyPackage _ _ = return []   hdlType _       = verilogType   hdlHWTypeKind _ = pure PrimitiveType -- Everything is a bitvector!@@ -197,20 +204,25 @@  -- | Generate Verilog for a Netlist component genVerilog-  :: SrcSpan+  :: ClashOpts+  -> ModName+  -> SrcSpan   -> IdentifierSet+  -> UsageMap   -> Component   -> VerilogM ((String, Doc), [(String, Doc)])-genVerilog sp seen c = do+genVerilog opts  _ sp seen usage c = do     -- Don't have type names conflict with module names or with previously     -- generated type names.     --     -- TODO: Collect all type names up front, to prevent relatively costly union.     -- TODO: Investigate whether type names / signal names collide in the first place-    Ap $ idSeen %= Id.union seen+    Ap $ do+      idSeen %= Id.union seen+      usages .= usage+      setSrcSpan sp -    Ap (setSrcSpan sp)-    v    <- commentHeader <> line <> timescale <> line <> module_ c+    v    <- commentHeader <> line <> nettype <> line <> timescale <> line <> module_ c     incs <- Ap $ use includes     return ((TextS.unpack (Id.toText cName), v), incs)   where@@ -219,25 +231,76 @@          = "/* AUTOMATICALLY GENERATED VERILOG-2001 SOURCE CODE."       <> line <> "** GENERATED BY CLASH " <> string (Text.pack clashVer) <> ". DO NOT MODIFY."       <> line <> "*/"-    timescale = "`timescale 100fs/100fs"+    nettype = "`default_nettype none"+    timescale = "`timescale 100fs/" <> string (Text.pack precision)+    precision = periodToString (opt_timescalePrecision opts)  sigPort-  :: Maybe WireOrReg+  :: VerilogM Doc+  -> Maybe N.Usage   -> Identifier   -> HWType   -> Maybe Expr   -> VerilogM Doc-sigPort wor (Id.toText -> pName) hwType iEM =+sigPort def mu (Id.toText -> pName) hwType iEM = do     addAttrs (hwTypeAttrs hwType)       (portType <+> verilogType hwType <+> stringS pName <> iE <> encodingNote hwType)   where-    portType = case wor of-                 Nothing   -> if isBiSignalIn hwType then "inout" else "input"-                 Just Wire -> "output" <+> "wire"-                 Just Reg  -> "output" <+> "reg"+    portType =+      -- See NOTE [net and variable ports]+      case mu of+        Just Cont ->+          "output wire" +        Just Proc{} ->+          "output reg"++        Nothing ->+          if isBiSignalIn hwType then "inout wire" else def <+> "wire"+     iE = maybe emptyDoc (noEmptyInit . expr_ False) iEM +{-+NOTE [net and variable ports]+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~+In Verilog, ports are typically seen written with the default implicit net type+of wire, i.e.++  input foo,+  output bar,++which is really a shorthand for++  input wire foo,+  output wire bar,++When we use `default_nettype none however, this is no longer allowed as all+nets must be explicitly given their type. When generating code we must include+the additional word wire (the net type).++What is the benefit of this? When we have a default net type, any variable+generated which is not declared is given an implicit declaration of this+default type. This can obscure clash errors, i.e. if Clash generated++  wire foo;+  fo <= ...;++Then simulators would act as though this was written:++  wire foo;+  wire fo;+  fo <= ...;++Which should never be the desired behaviour for code generated by Clash.++One final point, Verilog allows output to also be a variable type, i.e.++  output reg foo;++If a port is an input or an inout then it can only be a net and not a variable+according to the standard, so input reg and inout reg are impossible.+-}+ module_ :: Component -> VerilogM Doc module_ c =   modVerilog <* Ap (imports .= HashSet.empty >> libraries .= HashSet.empty)@@ -256,8 +319,11 @@     modBody    = indent 2 (decls (declarations c)) <> line <> line <> indent 2 (insts (declarations c))     modEnding  = "endmodule" -    inPorts  = sequence [ sigPort Nothing id_ hwType Nothing | (id_, hwType) <- inputs c  ]-    outPorts = sequence [ sigPort (Just wireOrReg) id_ hwType iEM | (wireOrReg, (id_, hwType), iEM) <- outputs c ]+    inPorts  = sequence [ sigPort "input" Nothing id_ hwType Nothing | (id_, hwType) <- inputs c  ]+    outPorts = do+      us <- use usages+      let useOf i u = lookupUsage i us <> Just u+      sequence [ sigPort "output" (useOf id_ u) id_ hwType iEM | (u,(id_, hwType), iEM) <- outputs c ]      -- slightly more readable than 'tupled', makes the output Haskell-y-er     commafy v = (comma <> space) <> pure v@@ -291,21 +357,23 @@   indent 2 (string "`uselib" <+> (hsep (mapM (\l -> ("lib=" <> string l)) xs)))   <> line <> line -wireRegFileDoc :: WireOrReg -> (Either a HWType) -> VerilogM Doc-wireRegFileDoc _    (Right FileType) = "integer"-wireRegFileDoc Wire _                = "wire"-wireRegFileDoc Reg  _                = "reg"+usageFileDoc :: Maybe N.Usage -> HWType -> VerilogM Doc+usageFileDoc _             FileType  = "integer"+usageFileDoc (Just Proc{}) _         = "reg"+usageFileDoc _             _         = "wire"  verilogType :: HWType -> VerilogM Doc verilogType t = case t of   Signed n -> "signed" <+> brackets (int (n-1) <> colon <> int 0)   Clock {} -> emptyDoc+  ClockN {} -> emptyDoc   Reset {} -> emptyDoc   Enable {} -> emptyDoc   Bit      -> emptyDoc   Bool     -> emptyDoc   FileType -> emptyDoc   Annotated _ ty -> verilogType ty+  BiDirectional _ ty -> verilogType ty   _        -> brackets (int (typeSize t -1) <> colon <> int 0)  sigDecl :: VerilogM Doc -> HWType -> VerilogM Doc@@ -342,31 +410,32 @@  -- | Add attribute notation to given declaration addAttrs-  :: [Attr']+  :: [Attr TextS.Text]   -> VerilogM Doc   -> VerilogM Doc addAttrs []     t = t addAttrs attrs' t =   "(*" <+> attrs'' <+> "*)" <+> t  where-  attrs'' = string $ Text.intercalate ", " (map renderAttr attrs')+  attrs'' = stringS $ TextS.intercalate ", " (map renderAttr attrs')  -- | Convert single attribute to verilog syntax-renderAttr :: Attr' -> Text.Text-renderAttr (StringAttr'  key value) = pack $ concat [key, " = ", show value]-renderAttr (IntegerAttr' key value) = pack $ concat [key, " = ", show value]-renderAttr (BoolAttr'    key True ) = pack $ concat [key, " = ", "1"]-renderAttr (BoolAttr'    key False) = pack $ concat [key, " = ", "0"]-renderAttr (Attr'        key      ) = pack $ key+renderAttr :: Attr TextS.Text -> TextS.Text+renderAttr (StringAttr  key value) = TextS.concat [key, " = ", TextS.pack (show value)]+renderAttr (IntegerAttr key value) = TextS.concat [key, " = ", TextS.pack (show value)]+renderAttr (BoolAttr    key True ) = TextS.concat [key, " = ", "1"]+renderAttr (BoolAttr    key False) = TextS.concat [key, " = ", "0"]+renderAttr (Attr        key      ) = key  decl :: Declaration -> VerilogM (Maybe Doc)-decl (NetDecl' noteM wr id_ tyE iEM) =-  Just A.<$> maybe id addNote noteM (addAttrs attrs (wireRegFileDoc wr tyE <+> tyDec tyE))+decl (NetDecl' noteM id_ tyE iEM) = do+  us <- use usages+  let u = lookupUsage id_ us+  Just A.<$> maybe id addNote noteM (addAttrs attrs (usageFileDoc u tyE <+> tyDec tyE))   where-    tyDec (Left  ty) = stringS ty <+> pretty id_ <> iE-    tyDec (Right ty) = sigDecl (pretty id_) ty <> iE+    tyDec ty = sigDecl (pretty id_) ty <> iE     addNote n = mappend ("//" <+> stringS n <> line)-    attrs = fromMaybe [] (hwTypeAttrs A.<$> either (const Nothing) Just tyE)+    attrs = fromMaybe [] (hwTypeAttrs A.<$> Just tyE)     iE    = maybe emptyDoc (noEmptyInit . expr_ False) iEM  decl _ = return Nothing@@ -471,7 +540,8 @@ -- | Turn a Netlist Declaration to a Verilog concurrent block inst_ :: Declaration -> VerilogM (Maybe Doc) inst_ (TickDecl {}) = return Nothing-inst_ (Assignment id_ e) = fmap Just $+inst_ (CompDecl {}) = return Nothing+inst_ (Assignment id_ Cont e) = fmap Just $   "assign" <+> pretty id_ <+> equals <+> expr_ False e <> semi  inst_ (CondAssignment id_ _ scrut _ [(Just (BoolLit b), l),(_,r)]) = fmap Just $@@ -535,6 +605,9 @@ inst_ (ConditionalDecl cond ds) = Just <$>   "`ifdef" <+> pretty cond <> line <> indent 2 (insts ds) <> line <> "`endif" +inst_ d =+  error ("inst_: " ++ show d)+ seq_ :: Seq -> VerilogM Doc seq_ (AlwaysClocked edge clk ds) =   "always @" <>@@ -575,8 +648,9 @@       "end") <:> conds es'  seq_ (SeqDecl sd) = case sd of-  Assignment id_ e ->-    pretty id_ <+> equals <+> expr_ False e <> semi+  Assignment id_ (Proc b) e ->+    let op = case b of { Blocking -> equals; NonBlocking -> "<=" }+     in pretty id_ <+> op <+> expr_ False e <> semi    BlackBoxD {} ->     fromMaybe <$> emptyDoc <*> inst_ sd@@ -1060,16 +1134,16 @@ expr_ _ (BlackBoxE pNm _ _ _ _ bbCtx _)   | pNm == "Clash.Sized.Internal.BitVector.fromInteger#"   , [Literal _ (NumLit n), Literal _ m, Literal _ i] <- extractLiterals bbCtx-  = let NumLit m' = m-        NumLit i' = i-    in exprLitV (Just (BitVector (fromInteger n),fromInteger n)) (BitVecLit m' i')+  , NumLit m' <- m+  , NumLit i' <- i+  = exprLitV (Just (BitVector (fromInteger n),fromInteger n)) (BitVecLit m' i')  expr_ _ (BlackBoxE pNm _ _ _ _ bbCtx _)   | pNm == "Clash.Sized.Internal.BitVector.fromInteger##"   , [Literal _ m, Literal _ i] <- extractLiterals bbCtx-  = let NumLit m' = m-        NumLit i' = i-    in exprLitV (Just (Bit,1)) (BitLit $ toBit m' i')+  , NumLit m' <- m+  , NumLit i' <- i+  = exprLitV (Just (Bit,1)) (BitLit $ toBit m' i')  expr_ _ (BlackBoxE pNm _ _ _ _ bbCtx _)   | pNm == "Clash.Sized.Internal.Index.fromInteger#"@@ -1192,10 +1266,9 @@   udf <- Ap (use k)   case (udf,b) of     (Just Nothing,U)  -> char '0'-    (Just (Just i),U) -> "'" <> int i <> "'"+    (Just (Just i),U) -> int i     _                 -> char (bit_char' b) - dcToExpr :: HWType -> Int -> Expr dcToExpr ty i = Literal (Just (ty,conSize ty)) (NumLit (toInteger i)) @@ -1211,6 +1284,7 @@  encodingNote :: Applicative m => HWType -> m Doc encodingNote (Clock _) = string " // clock"+encodingNote (ClockN _) = string " // clock (neg phase)" encodingNote (Reset _) = string " // reset" encodingNote (Enable _) = string " // enable" encodingNote (Annotated _ t) = encodingNote t

@@ -0,0 +1,127 @@+{-|+Copyright  :  (C) 2022,      Google Inc.,+License    :  BSD2 (see the file LICENSE)+Maintainer :  QBayLogic B.V. <devops@qbaylogic.com>++Utilities and definitions to deal with Verilog's time unit. These definitions+are here mostly to deal with varying @`timescale@ defintions, see:++  https://www.chipverify.com/verilog/verilog-timescale++-}++{-# LANGUAGE DeriveAnyClass #-}+{-# LANGUAGE DeriveGeneric #-}+{-# LANGUAGE NamedFieldPuns #-}+{-# LANGUAGE TypeFamilies #-}++module Clash.Backend.Verilog.Time where++import Clash.Class.HasDomain.HasSingleDomain+  (TryDomain, TryDomainResult(NotFound))++import Control.DeepSeq (NFData)+import Data.Char (toLower, isDigit)+import Data.Hashable (Hashable)+import Data.List (find)+import Data.Word (Word64)+import GHC.Generics (Generic)+import Text.Read (readMaybe)++-- | Verilog time units+data Unit = Fs | Ps | Ns | Us | Ms | S+  deriving (Show, Enum, Bounded, Eq, Ord, Generic, Hashable, NFData)++type instance TryDomain t Unit = 'NotFound++-- | Verilog time period. A combination of a length and a unit.+data Period = Period Word64 Unit+  deriving (Show, Generic, Hashable, Eq, NFData)++-- | Verilog timescale. Influences simulation precision.+data Scale = Scale+  { -- | Time step in wait statements, e.g. `#1`.+    step :: Period++    -- | Simulator precision - all units will get rounded to this period.+  , precision :: Period+  }+  deriving (Show, Generic, Hashable, Eq, NFData)++-- | Pretty print 'Scale' to Verilog `timescale+--+-- >>> scaleToString (Scale (Period 100 Ps) (Period 10 Fs))+-- "`timescale 100ps/10fs"+--+scaleToString :: Scale -> String+scaleToString (Scale{step, precision}) =+  "`timescale " <> periodToString step <> "/" <> periodToString precision++-- | Convert 'Unit' to Verilog time unit+--+-- >>> periodToString (Period 100 Fs)+-- "100fs"+--+periodToString :: Period -> String+periodToString (Period len unit) = show len <> unitToString unit++-- | Convert 'Unit' to Verilog time unit+--+-- >>> unitToString Ms+-- "ms"+--+unitToString :: Unit -> String+unitToString = map toLower . show++-- | Parse string representing a Verilog time unit to 'Unit'.+--+-- >>> parseUnit "ms"+-- Just Ms+-- >>> parseUnit "xs"+-- Nothing+--+parseUnit :: String -> Maybe Unit+parseUnit s = find tryUnit [minBound..]+ where+  tryUnit :: Unit -> Bool+  tryUnit u = unitToString u == s++-- | Parse a Verilog+--+-- >>> parsePeriod "100ms"+-- Just (Period 100 Ms)+-- >>> parsePeriod "100xs"+-- Nothing+-- >>> parsePeriod "100"+-- Nothing+-- >>> parsePeriod "ms"+-- Nothing+--+parsePeriod :: String -> Maybe Period+parsePeriod s =+  case span isDigit s of+    (len0, unit0) -> do+      len1 <- readMaybe len0+      unit1 <- parseUnit unit0+      pure (Period len1 unit1)++-- | Convert a period to a specific time unit. Will always output a minimum+-- of 1, even if the given 'Period' is already of the right 'Unit'.+--+-- >>> convertUnit Ps (Period 100 Ps)+-- 100+-- >>> convertUnit Fs (Period 100 Ps)+-- 100000+-- >>> convertUnit Ns (Period 100 Ps)+-- 1+-- >>> convertUnit Ms (Period 0 Ms)+-- 1+--+convertUnit :: Unit -> Period -> Word64+convertUnit targetUnit = go+ where+  go (Period len unit) =+    case compare unit targetUnit of+      LT -> go (Period (len `div` 1000) (succ unit))+      EQ -> max 1 len+      GT -> go (Period (len * 1000) (pred unit))

@@ -38,6 +38,7 @@ whnf'   :: Evaluator   -> BindingMap+  -> VarEnv Term   -> TyConMap   -> PrimHeap   -> Supply@@ -45,12 +46,12 @@   -> Bool   -> Term   -> (PrimHeap, PureHeap, Term)-whnf' eval bm tcm ph ids is isSubj e =+whnf' eval bm lh tcm ph ids is isSubj e =   toResult $ whnf eval tcm isSubj m  where   toResult x = (mHeapPrim x, mHeapLocal x, mTerm x) -  m  = Machine ph gh emptyVarEnv [] ids is e+  m  = Machine ph gh lh [] ids is e   gh = mapVarEnv bindingTerm bm  -- | Evaluate to WHNF given an existing Heap and Stack@@ -314,9 +315,19 @@ forcePrims :: Machine -> Bool forcePrims = go . mStack  where+  -- When do we need to force the compile-time evaluation of a primitive?+  --+  -- 1. When they are the subject of a case-expression   go (Scrutinise{}:_) = True+  -- 2. When they are in the argument position of another primitive:+  --    primitives are assumed to be strict in their arguments   go (PrimApply{}:_)  = True+  -- We look through ticks   go (Tickish{}:xs)   = go xs+  -- We are in a context where we dereferenced a heap-binding, hence the+  -- update fram on the stack. So now we need to check whether that variable+  -- reference was in a position where the result must be evaluated to WHNF+  go (Update{}:xs)    = go xs   go _                = False  primCount :: Machine -> Int

@@ -22,8 +22,6 @@   , piResultTys   ) where -import qualified Data.Text as Text (isInfixOf)- #if MIN_VERSION_prettyprinter(1,7,0) import Prettyprinter (line) #else@@ -35,17 +33,16 @@ import Clash.Core.DataCon (DataCon(dcType)) import Clash.Core.HasFreeVars import Clash.Core.Literal (Literal(..))-import Clash.Core.Name (Name(nameOcc)) import Clash.Core.Pretty import Clash.Core.Subst import Clash.Core.Term (Term(..), IsMultiPrim(..), PrimInfo(..), collectArgs)-import Clash.Core.TyCon (TyCon(tyConKind), TyConMap)+import Clash.Core.TyCon (TyCon(tyConKind), TyConMap, isTupleTyConLike) import Clash.Core.Type import Clash.Core.TysPrim import Clash.Core.Var (Var(varType)) import Clash.Core.VarEnv+import qualified Clash.Data.UniqMap as UniqMap import Clash.Debug (debugIsOn)-import Clash.Unique (lookupUniqMap') import Clash.Util (curLoc, pprPanic) import qualified Clash.Util.Interpolate as I @@ -70,6 +67,14 @@     CharLiteral _ -> charPrimTy     Int64Literal _ -> int64PrimTy     Word64Literal _ -> word64PrimTy+#if MIN_VERSION_ghc(8,8,0)+    Int8Literal _ -> int8PrimTy+    Int16Literal _ -> int16PrimTy+    Int32Literal _ -> int32PrimTy+    Word8Literal _ -> word8PrimTy+    Word16Literal _ -> word16PrimTy+    Word32Literal _ -> word32PrimTy+#endif     NaturalLiteral _ -> naturalPrimTy     ByteArrayLiteral _ -> byteArrayPrimTy @@ -82,7 +87,7 @@       MultiResult         | let (primArgs, primResTy) = splitFunForallTy (primType pr)         , TyConApp tupTcNm tupArgs <- tyView primResTy-        , Text.isInfixOf "GHC.Tuple.(" (nameOcc tupTcNm)+        , isTupleTyConLike tupTcNm         -> mkPolyFunTy primResTy (primArgs <> fmap Right tupArgs)          | otherwise@@ -111,7 +116,7 @@         liftedTypeKind        TyConApp tc args ->-        piResultTys tcm (tyConKind (lookupUniqMap' tcm tc)) args+        piResultTys tcm (tyConKind (UniqMap.find tc tcm)) args        OtherType{} ->         case ty of@@ -120,6 +125,7 @@           ForAllTy _ a -> inferCoreTypeOf tcm a           LitTy NumTy{} -> typeNatKind           LitTy SymTy{} -> typeSymbolKind+          LitTy CharTy{} -> charPrimTy           AnnType _ a -> inferCoreTypeOf tcm a           AppTy a b -> go a [b]            where

@@ -9,6 +9,7 @@   Term Literal -} +{-# LANGUAGE CPP #-} {-# LANGUAGE DeriveAnyClass #-} {-# LANGUAGE FlexibleInstances #-} {-# LANGUAGE MultiParamTypeClasses #-}@@ -50,6 +51,14 @@   | WordLiteral     !Integer   | Int64Literal    !Integer   | Word64Literal   !Integer+#if MIN_VERSION_ghc(8,8,0)+  | Int8Literal     !Integer+  | Int16Literal    !Integer+  | Int32Literal    !Integer+  | Word8Literal    !Integer+  | Word16Literal   !Integer+  | Word32Literal   !Integer+#endif   | StringLiteral   !String   | FloatLiteral    !Word32   | DoubleLiteral   !Word64

@@ -9,7 +9,6 @@ -}  {-# LANGUAGE LambdaCase #-}-{-# LANGUAGE OverloadedStrings #-}  module Clash.Core.PartialEval.AsTerm   ( AsTerm(..)

@@ -12,9 +12,7 @@ -}  {-# LANGUAGE LambdaCase #-}-{-# LANGUAGE OverloadedStrings #-} {-# LANGUAGE RankNTypes #-}-{-# LANGUAGE TemplateHaskell #-}  module Clash.Core.PartialEval.NormalForm   ( Arg

@@ -13,7 +13,6 @@ {-# LANGUAGE LambdaCase #-} {-# LANGUAGE OverloadedStrings #-} {-# LANGUAGE QuasiQuotes #-}-{-# LANGUAGE TemplateHaskell #-}  {-# OPTIONS_GHC -fno-warn-orphans #-} @@ -224,11 +223,24 @@ dcolon, rarrow, lam, tylam, at, cast, coerce, let_, letrec, in_, case_, of_, forall_,   data_,newtype_,type_,family_,instance_   :: ClashDoc-[dcolon, rarrow, lam, tylam, at, cast, coerce, let_, letrec, in_, case_, of_, forall_,-  data_,newtype_,type_,family_,instance_]-  = annotate (AnnSyntax Keyword) <$>-    ["::", "->", "λ", "Λ", "@", "▷", "~", "let", "letrec", "in", "case", "of", "forall",-     "data","newtype","type","family","instance"]+dcolon = annotate (AnnSyntax Keyword) "::"+rarrow = annotate (AnnSyntax Keyword) "->"+lam = annotate (AnnSyntax Keyword)  "λ"+tylam = annotate (AnnSyntax Keyword) "Λ"+at = annotate (AnnSyntax Keyword)  "@"+cast = annotate (AnnSyntax Keyword) "▷"+coerce = annotate (AnnSyntax Keyword) "~"+let_ = annotate (AnnSyntax Keyword) "let"+letrec = annotate (AnnSyntax Keyword) "letrec"+in_ = annotate (AnnSyntax Keyword) "in"+case_ = annotate (AnnSyntax Keyword) "case"+of_ = annotate (AnnSyntax Keyword) "of"+forall_ = annotate (AnnSyntax Keyword) "forall"+data_ = annotate (AnnSyntax Keyword) "data"+newtype_ = annotate (AnnSyntax Keyword) "newtype"+type_ = annotate (AnnSyntax Keyword) "type"+family_ = annotate (AnnSyntax Keyword) "family"+instance_ = annotate (AnnSyntax Keyword) "instance"  instance PrettyPrec Text where   pprPrec _ = pure . pretty@@ -291,6 +303,7 @@ instance Pretty LitTy where   pretty (NumTy i) = pretty i   pretty (SymTy s) = dquotes $ pretty s+  pretty (CharTy c) = squotes $ pretty c  instance PrettyPrec LitTy where   pprPrec _ = return . annotate (AnnSyntax LitS) . pretty@@ -352,17 +365,19 @@  instance PrettyPrec Literal where   pprPrec _ l = return $ annotate (AnnSyntax LitS) $ case l of-    IntegerLiteral i-      | i < 0          -> parens (pretty i)-      | otherwise      -> pretty i-    IntLiteral i-      | i < 0          -> parens (pretty i <> "#")-      | otherwise      -> pretty i <> "#"-    Int64Literal i-      | i < 0          -> parens (pretty i <> "#")-      | otherwise      -> pretty i <> "#"+    IntegerLiteral i   -> parensIf (i < 0) (pretty i)+    IntLiteral i       -> parensIf (i < 0) (pretty i <> "#")+    Int64Literal i     -> parensIf (i < 0) (pretty i <> "#64")     WordLiteral w      -> pretty w <> "##"-    Word64Literal w    -> pretty w <> "##"+    Word64Literal w    -> pretty w <> "##64"+#if MIN_VERSION_ghc(8,8,0)+    Int8Literal i      -> parensIf (i < 0) (pretty i <> "#8")+    Int16Literal i     -> parensIf (i < 0) (pretty i <> "#16")+    Int32Literal i     -> parensIf (i < 0) (pretty i <> "#32")+    Word8Literal w     -> pretty w <> "##8"+    Word16Literal w    -> pretty w <> "##16"+    Word32Literal w    -> pretty w <> "##32"+#endif     FloatLiteral w     -> pretty (wordToFloat w) <> "#"     DoubleLiteral w    -> pretty (wordToDouble w) <> "##"     CharLiteral c      -> pretty c <> "#"@@ -440,7 +455,7 @@ pprPrecLetrec :: Monad m => Rational -> Bool -> [(Id, Term)] -> Term -> m ClashDoc pprPrecLetrec prec isRec xes body = do   let bndrs = fst <$> xes-  body' <- annotate (AnnContext $ LetBody bndrs) <$> pprPrec noPrec body+  body' <- annotate (AnnContext $ LetBody xes) <$> pprPrec noPrec body   xes'  <- mapM (\(x,e) -> do                   x' <- pprBndr LetBind x                   e' <- pprPrec noPrec e

@@ -86,8 +86,8 @@ import           Clash.Core.Type           (Type (..)) import           Clash.Core.VarEnv import           Clash.Core.Var            (Id, Var (..), TyVar, isGlobalId)+import qualified Clash.Data.UniqMap as UniqMap import           Clash.Debug               (debugIsOn)-import           Clash.Unique import           Clash.Util import           Clash.Pretty @@ -457,7 +457,7 @@        "needsInScope" <+> clashPretty needsInScope)   a  where-  needsInScope = foldrWithUnique (\k _ s -> delVarSetByKey k s)+  needsInScope = UniqMap.foldrWithUnique (\k _ s -> delVarSetByKey k s)                    (freeVarsOf tys)                    tenv   tysFVsInSope = needsInScope `varSetInScope` inScope@@ -968,10 +968,6 @@     Case {}    -> 11     Tick {}    -> 12 -thenCompare :: Ordering -> Ordering -> Ordering-thenCompare EQ rel = rel-thenCompare rel _  = rel- -- | Structural equality on 'Term' eqTerm :: Term -> Term -> Bool eqTerm = go@@ -1040,5 +1036,3 @@  instance Ord Term where   compare = acmpTerm--deriving instance Ord TickInfo

@@ -19,3 +19,4 @@   -> Bool  instance Eq Type+instance Ord Type

@@ -70,19 +70,19 @@ import Data.Text                               (Text) import GHC.Generics #if MIN_VERSION_ghc(9,0,0)-import GHC.Types.SrcLoc                        (SrcSpan)+import GHC.Types.SrcLoc                        (SrcSpan, leftmost_smallest) #else-import SrcLoc                                  (SrcSpan)+import SrcLoc                                  (SrcSpan, leftmost_smallest) #endif  -- Internal Modules import Clash.Core.DataCon                      (DataCon) import Clash.Core.Literal                      (Literal) import Clash.Core.Name                         (Name (..))-import {-# SOURCE #-} Clash.Core.Subst         () -- instance Eq Type+import {-# SOURCE #-} Clash.Core.Subst         () -- instance Eq/Ord Type import {-# SOURCE #-} Clash.Core.Type          (Type) import Clash.Core.Var                          (Var, Id, TyVar)-import Clash.Util                              (curLoc)+import Clash.Util                              (curLoc, thenCompare)  -- | Term representation in the CoreHW language: System F + LetRec + Case data Term@@ -124,6 +124,18 @@   -- do not try to share expressions between multiple branches.   deriving (Eq, Show, Generic, NFData, Binary) +instance Ord TickInfo where+  compare (SrcSpan s1) (SrcSpan s2) = leftmost_smallest s1 s2+  compare (NameMod m1 t1) (NameMod m2 t2) =+    compare m1 m2 `thenCompare` compare t1 t2+  compare t1 t2 = compare (getRank t1) (getRank t2)+    where+      getRank :: TickInfo -> Word+      getRank SrcSpan{} = 0+      getRank NameMod{} = 1+      getRank DeDup     = 2+      getRank NoDeDup   = 3+ -- | Tag to indicate which instance/register name modifier was used data NameMod   = PrefixName@@ -254,7 +266,7 @@   -- ^ Function position of a type application   | LetBinding Id [Id]   -- ^ RHS of a Let-binder with the sibling LHS'-  | LetBody [Id]+  | LetBody [LetBinding]   -- ^ Body of a Let-binding with the bound LHS'   | LamBody Id   -- ^ Body of a lambda-term with the abstracted variable@@ -291,7 +303,7 @@     -- NB: we do not see inside the argument here     (TyAppC,          TyAppC)            -> True     (LetBinding i is, LetBinding i' is') -> i == i' && is == is'-    (LetBody is,      LetBody is')       -> is == is'+    (LetBody is,      LetBody is')       -> map fst is == map fst is'     (LamBody i,       LamBody i')        -> i == i'     (TyLamBody tv,    TyLamBody tv')     -> tv == tv'     (CaseAlt p,       CaseAlt p')        -> p == p'

@@ -6,16 +6,14 @@ module Clash.Core.TermInfo where  import Data.Maybe (fromMaybe)-import Data.Text (isInfixOf) import GHC.Stack (HasCallStack)  import Clash.Core.HasType-import Clash.Core.Name import Clash.Core.Term-import Clash.Core.TyCon (tyConDataCons, TyConMap)+import Clash.Core.TyCon (tyConDataCons, isTupleTyConLike, TyConMap) import Clash.Core.Type import Clash.Core.Var-import Clash.Unique (lookupUniqMap)+import qualified Clash.Data.UniqMap as UniqMap import Clash.Util.Interpolate as I  termSize :: Term -> Word@@ -70,8 +68,8 @@   | (_primArgs, primResTy) <- splitFunForallTy (primType primInfo)   , TyConApp tupTcNm tupEls <- tyView primResTy     -- XXX: Hardcoded for tuples-  , "GHC.Tuple.(," `isInfixOf` nameOcc tupTcNm-  , Just tupTc <- lookupUniqMap tupTcNm tcm+  , isTupleTyConLike tupTcNm+  , Just tupTc <- UniqMap.lookup tupTcNm tcm   , [tupDc] <- tyConDataCons tupTc   = Just $ MultiPrimInfo     { mpi_primInfo = primInfo

@@ -1,21 +1,29 @@ {-| Copyright   :  (C) 2019, Myrtle Software Ltd,                    2021, QBayLogic B.V.+                   2022, Google Inc. License     :  BSD2 (see the file LICENSE) Maintainer  :  QBayLogic B.V. <devops@qbaylogic.com>  Tools to convert a 'Term' into its "real" representation -}++{-# LANGUAGE CPP #-} {-# LANGUAGE FlexibleInstances #-}+{-# LANGUAGE LambdaCase #-} {-# LANGUAGE QuasiQuotes #-} {-# LANGUAGE TemplateHaskell #-}+{-# LANGUAGE NamedFieldPuns #-}  --{-# OPTIONS_GHC -ddump-splices #-}  module Clash.Core.TermLiteral   ( TermLiteral+  , showsTypePrec+  , showType   , termToData   , termToDataError+  , deriveTermLiteral   ) where  import           Data.Bifunctor                  (bimap)@@ -23,20 +31,39 @@ import           Data.Proxy                      (Proxy(..)) import           Data.Text                       (Text) import qualified Data.Text                       as Text+import           Data.Text.Extra                 (showt)+#if MIN_VERSION_ghc(9,4,0)+import qualified Data.Text.Internal              as Text+import qualified Data.Text.Array                 as Text+import qualified Data.Primitive.ByteArray        as BA+#endif import           Data.Typeable                   (Typeable, typeRep) import           GHC.Natural import           GHC.Stack+import           GHC.TypeNats (KnownNat)+import           Text.Show.Pretty                (ppShow) -import           Clash.Core.Term                 (Term(Literal), collectArgs)+import           Clash.Annotations.SynthesisAttributes (Attr)+import           Clash.Core.DataCon              (DataCon(..)) import           Clash.Core.Literal+import           Clash.Core.Name                 (Name(..)) import           Clash.Core.Pretty               (showPpr)+import           Clash.Core.Term                 (Term(Literal, Data), collectArgs)+import           Clash.Promoted.Nat+import           Clash.Promoted.Nat.Unsafe+import           Clash.Sized.Index               (Index)+import           Clash.Sized.Vector              (Vec (Nil, Cons), fromList) import qualified Clash.Util.Interpolate          as I import qualified Clash.Verification.Internal     as Cv  import           Clash.Core.TermLiteral.TH --- | Tools to deal with literals encoded as a "Term".-class Typeable a => TermLiteral a where+-- | Pretty print type @a@+showType :: TermLiteral a => Proxy a -> String+showType proxy = showsTypePrec 0 proxy ""++-- | Tools to deal with literals encoded as a 'Term'.+class TermLiteral a where   -- | Convert 'Term' to the constant it represents. Will return an error if   -- (one of the subterms) fail to translate.   termToData@@ -47,6 +74,23 @@     -- ^ 'Left' indicates a failure, containing the (sub)term that failed to     -- translate. 'Right' indicates a success. +  -- | Pretty print the type of a term (for error messages). Its default implementation+  -- uses 'Typeable' to print the type. Note that this method is there to allow+  -- an instance for 'SNat' to exist (and other GADTs imposing+  -- t'GHC.TypeNats.KnownNat'). Without it, GHC would ask for a @KnownNat@+  -- constraint on the instance, which would defeat the purpose of it.+  showsTypePrec ::+    -- | The operator precedence of the enclosing context (a number from @0@ to+    -- @11@). Function application has precedence @10@. Used to determine whether+    -- the result should be wrapped in parentheses.+    Int ->+    -- | Proxy for a term whose type needs to be pretty printed+    Proxy a ->+    ShowS++  default showsTypePrec :: Typeable a => Int -> Proxy a -> ShowS+  showsTypePrec n _ = showsPrec n (typeRep (Proxy @a))+ instance TermLiteral Term where   termToData = pure @@ -55,8 +99,23 @@   termToData t = Left t  instance TermLiteral Text where-  termToData t = Text.pack <$> termToData t+  termToData (collectArgs -> (_, [Left (Literal (StringLiteral s))])) =+    Right (Text.pack s)+#if MIN_VERSION_ghc(9,4,0)+  termToData (collectArgs -> (_, [ Left (Literal (ByteArrayLiteral (BA.ByteArray ba)))+                                 , Left (Literal (IntLiteral off))+                                 , Left (Literal (IntLiteral len))])) =+    Right (Text.Text (Text.ByteArray ba) (fromInteger off) (fromInteger len))+#endif+  termToData t = Left t +instance KnownNat n => TermLiteral (Index n) where+  termToData t@(collectArgs -> (_, [_, _, Left (Literal (IntegerLiteral n))]))+    | n < 0 = Left t+    | n >= natToNum @n = Left t+    | otherwise = Right (fromInteger n)+  termToData t = Left t+ instance TermLiteral Int where   termToData (collectArgs -> (_, [Left (Literal (IntLiteral n))])) =     Right (fromInteger n)@@ -68,6 +127,7 @@   termToData t = Left t  instance TermLiteral Integer where+  termToData (Literal (IntegerLiteral n)) = Right n   termToData (collectArgs -> (_, [Left (Literal (IntegerLiteral n))])) = Right n   termToData t = Left t @@ -76,10 +136,31 @@   termToData t = Left t  instance TermLiteral Natural where+  termToData t@(Literal (NaturalLiteral n))+    | n < 0 = Left t+    | otherwise = Right (fromIntegral n)   termToData (collectArgs -> (_, [Left (Literal (NaturalLiteral n))])) =     Right (fromInteger n)   termToData t = Left t +-- | Unsafe warning: If you use this instance in a monomorphic context (e.g.,+-- @TermLiteral (SNat 5)@), you need to make very sure that the term corresponds+-- to the literal. If you don't, there will be a mismatch between type level+-- variables and the proof carried in 'SNat's 'KnownNat'. Typical usage of this+-- instance will therefore leave the /n/ polymorphic.+--+instance TermLiteral (SNat n) where+  termToData = \case+    Literal (NaturalLiteral n) -> Right (unsafeSNat n)+    t                          -> Left t++  showsTypePrec n _+    -- We don't know the literal /n/ at this point. However, we can't simply put+    -- and /n/ here either, as it might collide with other type variables. To+    -- prevent confusion, we put an underscore. This is obviously "wrong", but+    -- good enough for error messages - the main purpose of this function.+    = showParen (n > 10) $ showString "SNat _"+ instance (TermLiteral a, TermLiteral b) => TermLiteral (a, b) where   termToData (collectArgs -> (_, lefts -> [a, b])) = do     a' <- termToData a@@ -87,38 +168,81 @@     pure (a', b')   termToData t = Left t -instance TermLiteral a => TermLiteral (Maybe a) where-  termToData = $(deriveTermToData ''Maybe)--instance TermLiteral Bool where-  termToData = $(deriveTermToData ''Bool)+  showsTypePrec _ _ =+    -- XXX: We pass in 11 here, but should really be passing in 0. We never want+    --      any parentheses for fields in tuples. However, Typeable's show+    --      implementation does put parentheses around tuple fields - so we+    --      replicate that behavior here for ease of testing.+      showChar '('+    . showsTypePrec 11 (Proxy @a)+    . showString ","+    . showsTypePrec 11 (Proxy @b)+    . showChar ')' -instance TermLiteral Cv.RenderAs where-  termToData = $(deriveTermToData ''Cv.RenderAs)+instance (TermLiteral a, KnownNat n) => TermLiteral (Vec n a) where+  termToData term = do+    res <- fromList <$> go term+    -- Check whether length of list constructed in 'go' corresponds to the+    -- @KnownNat n@ we've been given+    case res of+      Nothing -> Left term+      Just v -> Right v+   where+    -- Construct a list from given term+    go t@(collectArgs -> (constr, args)) =+      case constr of+        Data (MkData{dcName=Name{nameOcc}})+          | nameOcc == showt 'Nil -> Right []+          | nameOcc == showt 'Cons ->+            case lefts args of+              [_gadtProof, c0, cs0] -> do+                c1 <- termToData @a c0+                cs1 <- go cs0+                Right (c1:cs1)+              _ -> Left t+        _ -> Left t -instance TermLiteral a => TermLiteral (Cv.Assertion' a) where-  termToData = $(deriveTermToData ''Cv.Assertion')+  showsTypePrec n _ =+    showParen (n > 10) $+        showString "Vec"+      . showChar ' '+      . showString (show (natToInteger @n))+      . showChar ' '+      . showsTypePrec 11 (Proxy @a) -instance TermLiteral a => TermLiteral (Cv.Property' a) where-  termToData = $(deriveTermToData ''Cv.Property')+deriveTermLiteral ''Bool+deriveTermLiteral ''Maybe+deriveTermLiteral ''Either+deriveTermLiteral ''Cv.RenderAs+deriveTermLiteral ''Cv.Assertion'+deriveTermLiteral ''Cv.Property'+deriveTermLiteral ''Attr  -- | Same as 'termToData', but returns printable error message if it couldn't -- translate a term. termToDataError :: forall a. TermLiteral a => Term -> Either String a termToDataError term = bimap err id (termToData term)  where-  typ = show (typeRep (Proxy @a))+  -- XXX: If we put this construct in the quasiquoted part, it yields a parse+  --      error on some platforms. This is likely related to some older version+  --      of dependencies. In the interested of time yours truly just moved it+  --      outside of the quasiquoter.+  shownType = showType (Proxy @a)    err failedTerm = [I.i|     Failed to translate term to literal. Term that failed to translate:        #{showPpr failedTerm} +    In its non-pretty-printed form:++      #{ppShow failedTerm}+     In the full term:        #{showPpr term}      While trying to interpret something to type: -      #{typ}+      #{shownType}   |]

@@ -1,7 +1,20 @@-{-# LANGUAGE TemplateHaskellQuotes #-}+{-|+Copyright   :  (C) 2019, Myrtle Software Ltd,+                   2021, QBayLogic B.V.+                   2022, Google Inc+License     :  BSD2 (see the file LICENSE)+Maintainer  :  QBayLogic B.V. <devops@qbaylogic.com> +Template Haskell utilities for "Clash.Core.TermLiteral".+-}+{-# LANGUAGE CPP #-}+{-# LANGUAGE LambdaCase #-}+{-# LANGUAGE TemplateHaskell #-}+ module Clash.Core.TermLiteral.TH-  (  deriveTermToData+  ( deriveTermToData+  , deriveShowsTypePrec+  , deriveTermLiteral      -- Stop exporting @dcName'@  once `ghcide` stops type-checking expanded      -- TH splices   ,  dcName'@@ -9,7 +22,12 @@  import           Data.Either import qualified Data.Text                       as Text+import           Data.List                       (intersperse)+import qualified Data.List.NonEmpty              as NE+import           Data.Proxy+import           Data.Maybe                      (isNothing) import           Language.Haskell.TH.Syntax+import           Language.Haskell.TH.Lib         hiding (match)  import           Clash.Core.DataCon import           Clash.Core.Term                 (collectArgs, Term(Data))@@ -21,18 +39,136 @@ -- module Clash.Core.Subst cannot be linked; it is only available as a boot module import Clash.Core.Subst () +#if __GLASGOW_HASKELL__ >= 900+type CompatTyVarBndr = TyVarBndr ()+#else+type CompatTyVarBndr = TyVarBndr+#endif+ dcName' :: DataCon -> String dcName' = Text.unpack . nameOcc . dcName  termToDataName :: Name-termToDataName = mkName "Clash.Core.TermLiteral.termToData"+termToDataName =+  -- Note that we can't use a fully qualified name here: GHC disallows fully+  -- qualified names in instance function declarations.+  mkName "termToData" +showsTypePrecName :: Name+showsTypePrecName =+  -- Note that we can't use a fully qualified name here: GHC disallows fully+  -- qualified names in instance function declarations.+  mkName "showsTypePrec"++termLiteralName :: Name+termLiteralName = mkName "Clash.Core.TermLiteral.TermLiteral"++-- | Extracts variable names from a 'TyVarBndr'.+typeVarName :: CompatTyVarBndr -> Q (Name, Maybe Type)+typeVarName = \case+#if __GLASGOW_HASKELL__ >= 900+  PlainTV typVarName ()        -> pure (typVarName, Nothing)+  KindedTV typVarName () StarT -> pure (typVarName, Nothing)+  KindedTV typVarName () kind  -> pure (typVarName, Just kind)+#else+  PlainTV typVarName        -> pure (typVarName, Nothing)+  KindedTV typVarName StarT -> pure (typVarName, Nothing)+  KindedTV typVarName kind  -> pure (typVarName, Just kind)+#endif++-- | Derive a t'Clash.Core.TermLiteral.TermLiteral' instance for given type+deriveTermLiteral :: Name -> Q [Dec]+deriveTermLiteral typName = do+  TyConI (DataD _ _ typeVars _ _ _) <- reify typName+#if MIN_VERSION_template_haskell(2,21,0)+  typeVarNames <- mapM (typeVarName . fmap (const ())) typeVars+#else+  typeVarNames <- mapM typeVarName typeVars+#endif+  showsTypePrec <- deriveShowsTypePrec typName+  termToDataBody <- deriveTermToData typName+  let+    termToData = FunD termToDataName [Clause [] (NormalB termToDataBody) []]+    innerInstanceType = foldl AppT (ConT typName) (map (VarT . fst) typeVarNames)+    instanceType = ConT termLiteralName `AppT` innerInstanceType+    constraint typVarName = [t| $(conT termLiteralName) $(varT typVarName) |]+  constraints <- mapM (constraint . fst) (filter (isNothing . snd) typeVarNames)+  pure $ [InstanceD Nothing constraints instanceType [showsTypePrec, termToData]]++-- | For 'Maybe', constructs:+--+-- > showsTypePrec n _+-- >   = let+-- >       showSpace = showChar ' '+-- >       precCalls = [showsTypePrec 11 (Proxy @a)]+-- >       interspersedPrecCalls = intersperse showSpace precCalls+-- >       showType = foldl (.) (showString "Maybe") (showSpace : interspersedPrecCalls)+-- >     in+-- >       showParen (n > 10) showType+--+deriveShowsTypePrec :: Name -> Q Dec+deriveShowsTypePrec typName = do+  TyConI (DataD _ _ typeVars _ _ _) <- reify typName+#if MIN_VERSION_template_haskell(2,21,0)+  typeVarNames <- mapM (typeVarName . fmap (const ())) typeVars+#else+  typeVarNames <- mapM typeVarName typeVars+#endif+  showTypeBody <- mkShowTypeBody typeVarNames+  pure (FunD showsTypePrecName [Clause [VarP nName, WildP] (NormalB showTypeBody) []])+ where+  showTypeName = [| showString $(litE (StringL (nameBase typName))) |]++  -- Constructs:+  --+  -- > showsTypePrec 11 (Proxy @a)+  --+  -- where the 'a' is given as an argument. The surrounding operator precedence+  -- is set to indicate "function" application. I.e., it instructs the call to+  -- wrap the type string in parentheses.+  --+  mkTypePrecCall = \case+    (typVarName, Nothing) ->+      [| $(varE showsTypePrecName) 11 (Proxy @($(varT typVarName))) |]+    (_, Just _) ->+      -- XXX: Not sure how to deal with non-Type type variables so we do the dumb+      --      thing and insert an underscore.+      [| showString "_" |]++  -- Constructs:+  --+  -- > showString "Maybe" . showChar ' ' . showsTypePrec 11 (Proxy @a)+  --+  -- This is wrapped in an if-statement wrapping the result in parentheses if the+  -- incoming prec is more than 10 (function application).+  --+  mkShowTypeBody :: [(Name, Maybe Type)] -> Q Exp+  mkShowTypeBody typeVarNames =+    case typeVarNames of+      [] ->+        -- We seq on `n` here to prevent _unused variable_ warnings. This is a+        -- bit of a hack (the real solution would be to selectively pattern+        -- match).+        [| $(varE nName) `seq` $(showTypeName) |]+      _  -> [|+        let+          showSpace = showChar ' '+          precCalls = $(listE (map mkTypePrecCall typeVarNames))+          interspersedPrecCalls = intersperse showSpace precCalls+          showType = foldl (.) $(showTypeName) (showSpace : interspersedPrecCalls)+        in+          showParen ($(varE nName) > 10) showType+       |]++  nName = mkName "n"+ deriveTermToData :: Name -> Q Exp deriveTermToData typName = do   TyConI (DataD _ _ _ _ constrs _) <- reify typName   pure (deriveTermToData1 (map toConstr' constrs))  where   toConstr' (NormalC cName fields) = (cName, length fields)+  toConstr' (RecC cName fields) = (cName, length fields)   toConstr' c = error $ "Unexpected constructor: " ++ show c  deriveTermToData1 :: [(Name, Int)] -> Exp@@ -46,7 +182,7 @@   nArgs = maximum (map snd constrs)    args :: [Dec]-  args = zipWith (\n nm -> ValD (VarP nm) (NormalB (arg n)) []) [0..] argNames+  args = zipWith (\n nm -> ValD (VarP nm) (NormalB (arg (toInteger n))) []) [0..nArgs-1] (NE.toList argNames)   arg n = UInfixE (VarE argsName) (VarE '(!!)) (LitE (IntegerL n))    -- case nm of {"ConstrOne" -> ConstOne <$> termToData arg0; "ConstrTwo" -> ...}@@ -68,7 +204,7 @@     UInfixE       (ConE cName)       (VarE '(<$>))-      (VarE termToDataName `AppE` VarE (head argNames))+      (VarE termToDataName `AppE` VarE (NE.head argNames))   mkCall cName nFields =     foldl       (\e aName ->@@ -77,7 +213,7 @@           (VarE '(<*>))           (VarE termToDataName `AppE` VarE aName))       (mkCall cName 1)-      (take (nFields-1) (tail argNames))+      (take (nFields-1) (NE.tail argNames))    -- term@(collectArgs -> (Data (dcName' -> nm), args))   pat :: Pat@@ -86,13 +222,16 @@       termName       (ViewP         (VarE 'collectArgs)+#if MIN_VERSION_template_haskell(2,18,0)+        (TupP [ ConP 'Data [] [ViewP (VarE 'dcName') (VarP nameName)]+#else         (TupP [ ConP 'Data [ViewP (VarE 'dcName') (VarP nameName)]+#endif               , ViewP                  (VarE 'lefts)                  (if nArgs == 0 then WildP else VarP argsName)]))    termName = mkName "term"   argsName = mkName "args"-  argNames = [mkName ("arg" ++ show n) | n <- [0..nArgs-1]]+  argNames = fmap (mkName . ("arg" <>) . show) (NE.iterate (+1) (0 :: Word))   nameName = mkName "nm"-