clash-lib-1.8.0: prims/vhdl/Clash_Signal_Internal.primitives.yaml
- BlackBox:
name: Clash.Signal.Internal.delay#
kind: Declaration
outputUsage: NonBlocking
type: |-
delay#
:: ( KnownDomain dom -- ARG[0]
, NFDataX a ) -- ARG[1]
=> Clock dom -- ARG[2]
-> Enable dom -- ARG[3]
-> a -- ARG[4]
-> Signal clk a -- ARG[5]
-> Signal clk a
resultInit:
template: ~IF~ISINITDEFINED[0]~THEN~CONST[4]~ELSE~FI
resultName:
template: ~CTXNAME
template: |-
-- delay begin~IF ~ISACTIVEENABLE[3] ~THEN
~GENSYM[~RESULT_delay][4] : process(~ARG[2])
begin
if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[2]) then
if ~ARG[3] then
~RESULT <= ~ARG[5];
end if;
end if;
end process;~ELSE
~SYM[4] : process(~ARG[2])
begin
if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[2]) then
~RESULT <= ~ARG[5];
end if;
end process;~FI
-- delay end
- BlackBox:
name: Clash.Signal.Internal.asyncRegister#
kind: Declaration
outputUsage: NonBlocking
type: |-
asyncRegister#
:: ( KnownDomain dom -- ARG[0]
, NFDataX a ) -- ARG[1]
=> Clock dom -- ARG[2]
-> Reset dom -- ARG[3]
-> Enable dom -- ARG[4]
-> a -- ARG[5] (powerup value)
-> a -- ARG[6] (reset value)
-> Signal clk a -- ARG[7]
-> Signal clk a
resultInit:
template: ~IF~ISINITDEFINED[0]~THEN~CONST[5]~ELSE~FI
resultName:
template: ~CTXNAME
template: |-
-- async register begin
~SYM[2] : process(~ARG[2]~IF ~ISUNDEFINED[6] ~THEN ~ELSE,~ARG[3]~FI)
begin
~IF ~ISUNDEFINED[6] ~THEN ~ELSEif ~ARG[3] = ~IF ~ISACTIVEHIGH[0] ~THEN '1' ~ELSE '0' ~FI then
~RESULT <= ~CONST[6];
els~FIif ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[2]) then
~IF ~ISACTIVEENABLE[4] ~THEN
if ~ARG[4] then
~RESULT <= ~ARG[7];
end if;
~ELSE
~RESULT <= ~ARG[7];
~FI
end if;
end process;
-- async register end
- BlackBox:
name: Clash.Signal.Internal.register#
kind: Declaration
outputUsage: NonBlocking
type: |-
register#
:: ( KnownDomain dom -- ARG[0]
, NFDataX a ) -- ARG[1]
=> Clock dom -- ARG[2]
-> Reset dom -- ARG[3]
-> Enable dom -- ARG[4]
-> a -- ARG[5] (powerup value)
-> a -- ARG[6] (reset value)
-> Signal clk a -- ARG[7]
-> Signal clk a
resultInit:
template: ~IF~ISINITDEFINED[0]~THEN~CONST[5]~ELSE~FI
resultName:
template: ~CTXNAME
template: |-
-- register begin~IF ~ISACTIVEENABLE[4] ~THEN ~IF ~ISSYNC[0] ~THEN
~GENSYM[~RESULT_register][2] : process(~ARG[2])
begin
if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[2]) then
~IF ~ISUNDEFINED[6] ~THEN ~ELSEif ~ARG[3] = ~IF ~ISACTIVEHIGH[0] ~THEN '1' ~ELSE '0' ~FI then
~RESULT <= ~CONST[6];
els~FIif ~ARG[4] then
~RESULT <= ~ARG[7];
end if;
end if;
end process;~ELSE
~SYM[2] : process(~ARG[2]~IF ~ISUNDEFINED[6] ~THEN ~ELSE,~ARG[3]~FI)
begin
~IF ~ISUNDEFINED[6] ~THEN ~ELSEif ~ARG[3] = ~IF ~ISACTIVEHIGH[0] ~THEN '1' ~ELSE '0' ~FI then
~RESULT <= ~CONST[6];
els~FIif ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[2]) then
if ~ARG[4] then
~RESULT <= ~ARG[7];
end if;
end if;
end process;~FI~ELSE ~IF ~ISSYNC[0] ~THEN
~SYM[2] : process(~ARG[2])
begin
if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[2]) then
~IF ~ISUNDEFINED[6] ~THEN ~ELSEif ~ARG[3] = ~IF ~ISACTIVEHIGH[0] ~THEN '1' ~ELSE '0' ~FI then
~RESULT <= ~CONST[6];
else
~FI~RESULT <= ~ARG[7];
~IF ~ISUNDEFINED[6] ~THEN ~ELSEend if;~FI
end if;
end process;~ELSE
~SYM[2] : process(~ARG[2]~IF ~ISUNDEFINED[6] ~THEN ~ELSE,~ARG[3]~FI)
begin
~IF ~ISUNDEFINED[6] ~THEN ~ELSEif ~ARG[3] = ~IF ~ISACTIVEHIGH[0] ~THEN '1' ~ELSE '0' ~FI then
~RESULT <= ~CONST[6];
els~FIif ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[2]) then
~RESULT <= ~ARG[7];
end if;
end process;~FI~FI
-- register end
- BlackBox:
name: Clash.Signal.Internal.tbClockGen
comment: |-
ModelSim and Vivado seem to round time values to an integer number of picoseconds.
Use two half periods to prevent rounding errors from affecting the full period.
kind: Declaration
outputUsage: NonBlocking
type: |-
tbClockGen
:: KnownDomain dom -- ARG[0]
=> Signal dom Bool -- ARG[1]
-> Clock dom
template: |-
-- tbClockGen begin
-- pragma translate_off
~GENSYM[clkGen][0] : process is
constant ~GENSYM[half_periodH][1] : time := ~PERIOD[0]000 fs / 2;
constant ~GENSYM[half_periodL][2] : time := ~PERIOD[0]000 fs - ~SYM[1];
begin
~RESULT <= ~IF~ACTIVEEDGE[Rising][0]~THEN'0'~ELSE'1'~FI;
wait for ~LONGESTPERIOD ps;
~IF~ISACTIVEENABLE[1]~THENwhile ~ARG[1] ~ELSE~FIloop
~RESULT <= not ~RESULT;
wait for ~SYM[1];
~RESULT <= not ~RESULT;
wait for ~SYM[2];
end loop;
wait;
end process;
-- pragma translate_on
-- tbClockGen end
warning: Clash.Signal.Internal.tbClockGen is not synthesizable!
workInfo: Always
- BlackBox:
name: Clash.Signal.Internal.tbDynamicClockGen
comment: |-
ModelSim and Vivado seem to round time values to an integer number of picoseconds.
Use two half periods to prevent rounding errors from affecting the full period.
kind: Declaration
outputUsage: NonBlocking
type: |-
tbDynamicClockGen
:: KnownDomain dom -- ARG[0]
=> Signal dom Int64 -- ARG[1]
-> Signal dom Bool -- ARG[2]
-> Clock dom
template: |-
-- tbDynamicClockGen begin
-- pragma translate_off
~GENSYM[dynClkGen][0] : process is
variable ~GENSYM[whole_period][1] : time;
variable ~GENSYM[half_periodH][2] : time;
variable ~GENSYM[half_periodL][3] : time;
begin
~RESULT <= ~IF~ACTIVEEDGE[Rising][0]~THEN'0'~ELSE'1'~FI;
wait for ~LONGESTPERIOD ps;
~IF~ISACTIVEENABLE[2]~THENwhile ~ARG[2] ~ELSE~FIloop
~SYM[1] := to_integer(~VAR[periods][1]) * 1 fs;
~SYM[2] := ~SYM[1] / 2;
~SYM[3] := ~SYM[1] - ~SYM[2];
~RESULT <= not ~RESULT;
wait for ~SYM[2];
~RESULT <= not ~RESULT;
wait for ~SYM[3];
end loop;
wait;
end process;
-- pragma translate_on
-- tbDynamicClockGen end
warning: Clash.Signal.Internal.tbDynamicClockGen is not synthesizable!
workInfo: Always
- BlackBox:
name: Clash.Signal.Internal.resetGenN
kind: Declaration
type: 'resetGenN :: (KnownDomain
dom, 1 <= n) => SNat n -> Reset dom'
template: |-
-- resetGen begin
~GENSYM[resetGen][0] : block
constant ~GENSYM[reset_delay][1] : time := ~LONGESTPERIOD ps - 1 ps + (integer'(~LIT[2]) * ~PERIOD[0] ps);
begin
-- pragma translate_off
~RESULT
<= ~IF ~ISACTIVEHIGH[0] ~THEN'1'~ELSE'0'~FI,
~IF ~ISACTIVEHIGH[0] ~THEN'0'~ELSE'1'~FI after ~SYM[1];
-- pragma translate_on
end block;
-- resetGen end
workInfo: Always
- BlackBox:
name: Clash.Signal.Internal.unsafeFromReset
kind: Declaration
type: 'unsafeFromReset
:: Reset dom -> Signal dom Bool'
template: ~RESULT <= true when ~ARG[0] = '1' else false;
workInfo: Never
- BlackBox:
name: Clash.Signal.Internal.unsafeToReset
kind: Declaration
type: 'unsafeToReset ::
KnownDomain dom => Signal dom Bool -> Reset dom'
template: ~RESULT <= '1' when ~ARG[1] = true else '0';
workInfo: Never