Cabal revisions of sv2v-0.0.12
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revision 1
-cabal-version: 2.4-name: sv2v-version: 0.0.12-license: BSD-3-Clause-license-file: LICENSE NOTICE-maintainer: Zachary Snow <zach@zachjs.com>-author:- Zachary Snow <zach@zachjs.com>, Tom Hawkins <tomahawkins@gmail.com>--homepage: https://github.com/zachjs/sv2v-synopsis: SystemVerilog to Verilog conversion-description:- A tool for coverting SystemVerilog to Verilog. Originally forked from the- Verilog parser found at https://github.com/tomahawkins/verilog--category: Language, Hardware, Embedded, Development-extra-doc-files:- README.md- CHANGELOG.md--source-repository head- type: git- location: git://github.com/zachjs/sv2v.git--executable sv2v- main-is: sv2v.hs- build-tool-depends: alex:alex >=3.2 && <4, happy:happy >=1.19 && <2- hs-source-dirs: src- other-modules:- Language.SystemVerilog- Language.SystemVerilog.AST- Language.SystemVerilog.AST.Attr- Language.SystemVerilog.AST.Decl- Language.SystemVerilog.AST.Description- Language.SystemVerilog.AST.Expr- Language.SystemVerilog.AST.GenItem- Language.SystemVerilog.AST.LHS- Language.SystemVerilog.AST.ModuleItem- Language.SystemVerilog.AST.Number- Language.SystemVerilog.AST.Op- Language.SystemVerilog.AST.ShowHelp- Language.SystemVerilog.AST.Stmt- Language.SystemVerilog.AST.Type- Language.SystemVerilog.Parser- Language.SystemVerilog.Parser.Keywords- Language.SystemVerilog.Parser.Lex- Language.SystemVerilog.Parser.Parse- Language.SystemVerilog.Parser.ParseDecl- Language.SystemVerilog.Parser.Preprocess- Language.SystemVerilog.Parser.Tokens- Convert- Convert.AlwaysKW- Convert.AsgnOp- Convert.Assertion- Convert.BlockDecl- Convert.Cast- Convert.DimensionQuery- Convert.DoWhile- Convert.DuplicateGenvar- Convert.EmptyArgs- Convert.Enum- Convert.EventEdge- Convert.ExprAsgn- Convert.ExprUtils- Convert.ForAsgn- Convert.Foreach- Convert.FuncRet- Convert.FuncRoutine- Convert.GenvarName- Convert.HierConst- Convert.ImplicitNet- Convert.Inside- Convert.Interface- Convert.IntTypes- Convert.Jump- Convert.KWArgs- Convert.Logic- Convert.LogOp- Convert.MultiplePacked- Convert.NamedBlock- Convert.Package- Convert.ParamNoDefault- Convert.ParamType- Convert.PortDecl- Convert.RemoveComments- Convert.ResolveBindings- Convert.Scoper- Convert.Simplify- Convert.Stream- Convert.StringParam- Convert.StringType- Convert.Struct- Convert.StructConst- Convert.TFBlock- Convert.Traverse- Convert.Typedef- Convert.TypeOf- Convert.UnbasedUnsized- Convert.Unique- Convert.UnnamedGenBlock- Convert.UnpackedArray- Convert.Unsigned- Convert.Wildcard- Job- Paths_sv2v-- autogen-modules: Paths_sv2v- default-language: Haskell2010- default-extensions: PatternSynonyms TupleSections- ghc-options:- -O3 -threaded -rtsopts "-with-rtsopts=-N -A32m"- -funbox-strict-fields -Wall -Wno-incomplete-uni-patterns-- build-depends:- array >=0.5.6.0 && <0.6,- base >=4.18.2.0 && <4.19,- cmdargs >=0.10.22 && <0.11,- containers >=0.6.7 && <0.7,- directory >=1.3.8.1 && <1.4,- filepath >=1.4.200.1 && <1.5,- githash >=0.1.7.0 && <0.2,- hashable >=1.4.4.0 && <1.5,- mtl >=2.3.1 && <2.4,- vector >=0.13.1.0 && <0.14+cabal-version: 2.4 +name: sv2v +version: 0.0.12 +x-revision: 1 +license: BSD-3-Clause +license-file: LICENSE NOTICE +maintainer: Zachary Snow <zach@zachjs.com> +author: + Zachary Snow <zach@zachjs.com>, Tom Hawkins <tomahawkins@gmail.com> + +homepage: https://github.com/zachjs/sv2v +synopsis: SystemVerilog to Verilog conversion +description: + A tool for coverting SystemVerilog to Verilog. Originally forked from the + Verilog parser found at https://github.com/tomahawkins/verilog + +category: Language, Hardware, Embedded, Development +extra-doc-files: + README.md + CHANGELOG.md + +source-repository head + type: git + location: git://github.com/zachjs/sv2v.git + +executable sv2v + main-is: sv2v.hs + build-tool-depends: alex:alex >=3.2 && <4, happy:happy >=1.19 && <2 + hs-source-dirs: src + other-modules: + Language.SystemVerilog + Language.SystemVerilog.AST + Language.SystemVerilog.AST.Attr + Language.SystemVerilog.AST.Decl + Language.SystemVerilog.AST.Description + Language.SystemVerilog.AST.Expr + Language.SystemVerilog.AST.GenItem + Language.SystemVerilog.AST.LHS + Language.SystemVerilog.AST.ModuleItem + Language.SystemVerilog.AST.Number + Language.SystemVerilog.AST.Op + Language.SystemVerilog.AST.ShowHelp + Language.SystemVerilog.AST.Stmt + Language.SystemVerilog.AST.Type + Language.SystemVerilog.Parser + Language.SystemVerilog.Parser.Keywords + Language.SystemVerilog.Parser.Lex + Language.SystemVerilog.Parser.Parse + Language.SystemVerilog.Parser.ParseDecl + Language.SystemVerilog.Parser.Preprocess + Language.SystemVerilog.Parser.Tokens + Convert + Convert.AlwaysKW + Convert.AsgnOp + Convert.Assertion + Convert.BlockDecl + Convert.Cast + Convert.DimensionQuery + Convert.DoWhile + Convert.DuplicateGenvar + Convert.EmptyArgs + Convert.Enum + Convert.EventEdge + Convert.ExprAsgn + Convert.ExprUtils + Convert.ForAsgn + Convert.Foreach + Convert.FuncRet + Convert.FuncRoutine + Convert.GenvarName + Convert.HierConst + Convert.ImplicitNet + Convert.Inside + Convert.Interface + Convert.IntTypes + Convert.Jump + Convert.KWArgs + Convert.Logic + Convert.LogOp + Convert.MultiplePacked + Convert.NamedBlock + Convert.Package + Convert.ParamNoDefault + Convert.ParamType + Convert.PortDecl + Convert.RemoveComments + Convert.ResolveBindings + Convert.Scoper + Convert.Simplify + Convert.Stream + Convert.StringParam + Convert.StringType + Convert.Struct + Convert.StructConst + Convert.TFBlock + Convert.Traverse + Convert.Typedef + Convert.TypeOf + Convert.UnbasedUnsized + Convert.Unique + Convert.UnnamedGenBlock + Convert.UnpackedArray + Convert.Unsigned + Convert.Wildcard + Job + Paths_sv2v + + autogen-modules: Paths_sv2v + default-language: Haskell2010 + default-extensions: PatternSynonyms TupleSections + ghc-options: + -O3 -threaded -rtsopts "-with-rtsopts=-N -A32m" + -funbox-strict-fields -Wall -Wno-incomplete-uni-patterns + + build-depends: + array <0.6, + base <4.19, + cmdargs <0.11, + containers <0.7, + directory <1.4, + filepath <1.5, + githash <0.2, + hashable <1.5, + mtl <2.4, + vector <0.14