name: netlist-to-vhdl
version: 0.2
synopsis: Convert a Netlist AST to VHDL
description: Convert a Netlist AST to VHDL
category: Language
license: BSD3
license-file: LICENSE
copyright: Copyright (c) 2010 University of Kansas
author: Garrin Kimmell
maintainer: garrin.kimmell@gmail.com
package-url: git://github.com/pheaver/netlist-verilog.git
build-type: Simple
cabal-version: >=1.6
flag base4
Description: Compile using base-4 instead of base-3
Default: True
Library
ghc-options: -Wall
exposed-modules: Language.Netlist.GenVHDL
build-depends: netlist == 0.2, pretty >= 1.0
if flag(base4)
build-depends: base == 4.*
else
build-depends: base == 3.*