hsverilog-0.1.0: hsverilog.cabal

-- Initial hspec-server.cabal generated by cabal init.  For further 
-- documentation, see http://haskell.org/cabal/users-guide/

name:                hsverilog
version:             0.1.0
synopsis:            Synthesizable Verilog DSL supporting for multiple clock and reset
description:         Synthesizable Verilog DSL supporting for multiple clock and reset
license:             BSD3
license-file:        LICENSE
author:              Junji Hashimoto
maintainer:          junji.hashimoto@gmail.com
stability:           Experimental
category:            Hardware
build-type:          Simple
-- extra-source-files:  
cabal-version:       >=1.10

bug-reports:         https://github.com/junjihashimoto/hsverilog/issues

extra-source-files:
  ChangeLog.md
  README.md

source-repository head
  type:           git
  location:       https://github.com/junjihashimoto/hsverilog.git

library
  exposed-modules:     HsVerilog
                     , HsVerilog.Type
                     , HsVerilog.Verilog
                     , HsVerilog.Verilog.Internal
                     , HsVerilog.Verilog.DSL
                     , HsVerilog.Library
                     , HsVerilog.Simulation
  -- other-modules:       
  -- other-extensions:    
  build-depends:       base >=4.6 && <5
                     , transformers
                     , shakespeare
                     , text
                     , containers
  hs-source-dirs:      src
  default-language:    Haskell2010

test-suite test
    type:              exitcode-stdio-1.0
    main-is:           test.hs
    hs-source-dirs:    tests,dist/build/autogen
    ghc-options:       -Wall

    build-depends: base
                 , hsverilog
                 , hspec
                 , hspec-contrib
                 , hspec-expectations-lifted
                 , shakespeare
                 , transformers
                 , text
                 , containers
    Default-Language:   Haskell2010