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<language name="VHDL" version="1.10" kateversion="2.3" section="Hardware" extensions="*.vhdl;*.vhd" mimetype="text/x-vhdl" author="Rocky Scaletta (rocky@purdue.edu), Stefan Endrullis (stefan@endrullis.de), Florent Ouchet (outchy@users.sourceforge.net), Chris Higgs (chiggs.99@gmail.com), Jan Michel (jan@mueschelsoft.de)">
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<item> file </item>
<!-- <item> package </item>-->
<item> library </item>
<item> use </item>
<!--
<item> entity </item>
<item> architecture </item>
<item> of </item>
<item> configuration </item>
-->
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<list name="keywords">
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<item> after </item>
<item> alias </item>
<item> all </item>
<item> array </item>
<item> assert </item>
<item> assume </item>
<item> assume_guarantee </item>
<item> attribute </item>
<item> begin </item>
<item> block </item>
<item> body </item>
<item> bus </item>
<item> component </item>
<item> constant </item>
<item> context </item>
<item> cover </item>
<item> default </item>
<item> disconnect </item>
<item> downto </item>
<item> end </item>
<item> exit </item>
<item> fairness </item>
<item> file </item>
<item> force </item>
<item> function </item>
<item> generate </item>
<item> generic </item>
<item> group </item>
<item> guarded </item>
<item> impure </item>
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<item> procedure </item>
<item> process </item>
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<item> pure </item>
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<item> units </item>
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<list name="if">
<item> if </item>
<item> else </item>
<item> elsif </item>
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<list name="forOrWhile">
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<list name="directions">
<item> in </item>
<item> inout </item>
<item> out </item>
<item> buffer </item>
<item> linkage </item>
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<list name="signals">
<item> signal </item>
<item> variable </item>
<item> constant </item>
<item> type </item>
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<item> or </item>
<item> xor </item>
<item> not </item>
</list>-->
<list name="range">
<item> to </item>
<item> downto </item>
<item> others </item>
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<list name="case">
<item> case </item>
<item> when </item>
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<item> bit_vector </item>
<item> character </item>
<item> boolean </item>
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<item> integer_vector </item>
<item> real </item>
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<item> time_vector </item>
<item> delay_length </item>
<item> string </item>
<item> severity_level </item>
<item> positive </item>
<item> natural </item>
<item> file_open_kind </item>
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<item> unresolved_unsigned </item>
<item> unresolved_signed </item>
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<item> text </item>
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<item> std_logic </item>
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<item> std_ulogic </item>
<item> std_ulogic_vector </item>
<item> x01 </item>
<item> x01z </item>
<item> ux01 </item>
<item> ux01z </item>
<item> qsim_state </item>
<item> qsim_state_vector </item>
<item> qsim_12state </item>
<item> qsim_12state_vector </item>
<item> qsim_strength </item>
<item> mux_bit </item>
<item> mux_vector </item>
<item> reg_bit </item>
<item> reg_vector </item>
<item> wor_bit </item>
<item> wor_vector </item>
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