data-svd-0.1.0.0: .golden/stm32f405/golden
STM32F405
TIM2 0x40000000 General purpose timers
CR1 0x0 - control register 1
_ :: Bits 22 -- (Reserved)
CKD :: Bits 2 -- Clock division
ARPE :: Bit -- Auto-reload preload enable
CMS :: Bits 2 -- Center-aligned mode selection
DIR :: Bit -- Direction
OPM :: Bit -- One-pulse mode
URS :: Bit -- Update request source
UDIS :: Bit -- Update disable
CEN :: Bit -- Counter enable
CR2 0x4 - control register 2
_ :: Bits 24 -- (Reserved)
TI1S :: Bit -- TI1 selection
MMS :: Bits 3 -- Master mode selection
CCDS :: Bit -- Capture/compare DMA selection
_ :: Bits 3 -- (Reserved)
SMCR 0x8 - slave mode control register
_ :: Bits 16 -- (Reserved)
ETP :: Bit -- External trigger polarity
ECE :: Bit -- External clock enable
ETPS :: Bits 2 -- External trigger prescaler
ETF :: Bits 4 -- External trigger filter
MSM :: Bit -- Master/Slave mode
TS :: Bits 3 -- Trigger selection
_ :: Bit -- (Reserved)
SMS :: Bits 3 -- Slave mode selection
DIER 0xc - DMA/Interrupt enable register
_ :: Bits 17 -- (Reserved)
TDE :: Bit -- Trigger DMA request enable
_ :: Bit -- (Reserved)
CC4DE :: Bit -- Capture/Compare 4 DMA request enable
CC3DE :: Bit -- Capture/Compare 3 DMA request enable
CC2DE :: Bit -- Capture/Compare 2 DMA request enable
CC1DE :: Bit -- Capture/Compare 1 DMA request enable
UDE :: Bit -- Update DMA request enable
_ :: Bit -- (Reserved)
TIE :: Bit -- Trigger interrupt enable
_ :: Bit -- (Reserved)
CC4IE :: Bit -- Capture/Compare 4 interrupt enable
CC3IE :: Bit -- Capture/Compare 3 interrupt enable
CC2IE :: Bit -- Capture/Compare 2 interrupt enable
CC1IE :: Bit -- Capture/Compare 1 interrupt enable
UIE :: Bit -- Update interrupt enable
SR 0x10 - status register
_ :: Bits 19 -- (Reserved)
CC4OF :: Bit -- Capture/Compare 4 overcapture flag
CC3OF :: Bit -- Capture/Compare 3 overcapture flag
CC2OF :: Bit -- Capture/compare 2 overcapture flag
CC1OF :: Bit -- Capture/Compare 1 overcapture flag
_ :: Bits 2 -- (Reserved)
TIF :: Bit -- Trigger interrupt flag
_ :: Bit -- (Reserved)
CC4IF :: Bit -- Capture/Compare 4 interrupt flag
CC3IF :: Bit -- Capture/Compare 3 interrupt flag
CC2IF :: Bit -- Capture/Compare 2 interrupt flag
CC1IF :: Bit -- Capture/compare 1 interrupt flag
UIF :: Bit -- Update interrupt flag
EGR 0x14 - event generation register
_ :: Bits 25 -- (Reserved)
TG :: Bit -- Trigger generation
_ :: Bit -- (Reserved)
CC4G :: Bit -- Capture/compare 4 generation
CC3G :: Bit -- Capture/compare 3 generation
CC2G :: Bit -- Capture/compare 2 generation
CC1G :: Bit -- Capture/compare 1 generation
UG :: Bit -- Update generation
CCMR1_Output 0x18 - capture/compare mode register 1 (output mode)
_ :: Bits 16 -- (Reserved)
OC2CE :: Bit -- OC2CE
OC2M :: Bits 3 -- OC2M
OC2PE :: Bit -- OC2PE
OC2FE :: Bit -- OC2FE
CC2S :: Bits 2 -- CC2S
OC1CE :: Bit -- OC1CE
OC1M :: Bits 3 -- OC1M
OC1PE :: Bit -- OC1PE
OC1FE :: Bit -- OC1FE
CC1S :: Bits 2 -- CC1S
CCMR1_Input 0x18 - capture/compare mode register 1 (input mode)
_ :: Bits 16 -- (Reserved)
IC2F :: Bits 4 -- Input capture 2 filter
IC2PSC :: Bits 2 -- Input capture 2 prescaler
CC2S :: Bits 2 -- Capture/Compare 2 selection
IC1F :: Bits 4 -- Input capture 1 filter
IC1PSC :: Bits 2 -- Input capture 1 prescaler
CC1S :: Bits 2 -- Capture/Compare 1 selection
CCMR2_Output 0x1c - capture/compare mode register 2 (output mode)
_ :: Bits 16 -- (Reserved)
OC4CE :: Bit -- O24CE
OC4M :: Bits 3 -- OC4M
OC4PE :: Bit -- OC4PE
OC4FE :: Bit -- OC4FE
CC4S :: Bits 2 -- CC4S
OC3CE :: Bit -- OC3CE
OC3M :: Bits 3 -- OC3M
OC3PE :: Bit -- OC3PE
OC3FE :: Bit -- OC3FE
CC3S :: Bits 2 -- CC3S
CCMR2_Input 0x1c - capture/compare mode register 2 (input mode)
_ :: Bits 16 -- (Reserved)
IC4F :: Bits 4 -- Input capture 4 filter
IC4PSC :: Bits 2 -- Input capture 4 prescaler
CC4S :: Bits 2 -- Capture/Compare 4 selection
IC3F :: Bits 4 -- Input capture 3 filter
IC3PSC :: Bits 2 -- Input capture 3 prescaler
CC3S :: Bits 2 -- Capture/compare 3 selection
CCER 0x20 - capture/compare enable register
_ :: Bits 16 -- (Reserved)
CC4NP :: Bit -- Capture/Compare 4 output Polarity
_ :: Bit -- (Reserved)
CC4P :: Bit -- Capture/Compare 3 output Polarity
CC4E :: Bit -- Capture/Compare 4 output enable
CC3NP :: Bit -- Capture/Compare 3 output Polarity
_ :: Bit -- (Reserved)
CC3P :: Bit -- Capture/Compare 3 output Polarity
CC3E :: Bit -- Capture/Compare 3 output enable
CC2NP :: Bit -- Capture/Compare 2 output Polarity
_ :: Bit -- (Reserved)
CC2P :: Bit -- Capture/Compare 2 output Polarity
CC2E :: Bit -- Capture/Compare 2 output enable
CC1NP :: Bit -- Capture/Compare 1 output Polarity
_ :: Bit -- (Reserved)
CC1P :: Bit -- Capture/Compare 1 output Polarity
CC1E :: Bit -- Capture/Compare 1 output enable
CNT 0x24 - counter
CNT :: Bits 32 -- Counter value
PSC 0x28 - prescaler
_ :: Bits 16 -- (Reserved)
PSC :: Bits 16 -- Prescaler value
ARR 0x2c - auto-reload register
ARR :: Bits 32 -- Auto-reload value
CCR1 0x34 - capture/compare register
CCR :: Bits 32 -- Capture/Compare value
CCR2 0x38 - capture/compare register
CCR :: Bits 32 -- Capture/Compare value
CCR3 0x3c - capture/compare register
CCR :: Bits 32 -- Capture/Compare value
CCR4 0x40 - capture/compare register
CCR :: Bits 32 -- Capture/Compare value
DCR 0x48 - DMA control register
_ :: Bits 19 -- (Reserved)
DBL :: Bits 5 -- DMA burst length
_ :: Bits 3 -- (Reserved)
DBA :: Bits 5 -- DMA base address
DMAR 0x4c - DMA address for full transfer
_ :: Bits 16 -- (Reserved)
DMAB :: Bits 16 -- DMA register for burst accesses
OR 0x50 - TIM5 option register
_ :: Bits 20 -- (Reserved)
ITR1_RMP :: Bits 2 -- Timer Input 4 remap
_ :: Bits 10 -- (Reserved)
TIM3 0x40000400 General purpose timers
CR1 0x0 - control register 1
_ :: Bits 22 -- (Reserved)
CKD :: Bits 2 -- Clock division
ARPE :: Bit -- Auto-reload preload enable
CMS :: Bits 2 -- Center-aligned mode selection
DIR :: Bit -- Direction
OPM :: Bit -- One-pulse mode
URS :: Bit -- Update request source
UDIS :: Bit -- Update disable
CEN :: Bit -- Counter enable
CR2 0x4 - control register 2
_ :: Bits 24 -- (Reserved)
TI1S :: Bit -- TI1 selection
MMS :: Bits 3 -- Master mode selection
CCDS :: Bit -- Capture/compare DMA selection
_ :: Bits 3 -- (Reserved)
SMCR 0x8 - slave mode control register
_ :: Bits 16 -- (Reserved)
ETP :: Bit -- External trigger polarity
ECE :: Bit -- External clock enable
ETPS :: Bits 2 -- External trigger prescaler
ETF :: Bits 4 -- External trigger filter
MSM :: Bit -- Master/Slave mode
TS :: Bits 3 -- Trigger selection
_ :: Bit -- (Reserved)
SMS :: Bits 3 -- Slave mode selection
DIER 0xc - DMA/Interrupt enable register
_ :: Bits 17 -- (Reserved)
TDE :: Bit -- Trigger DMA request enable
_ :: Bit -- (Reserved)
CC4DE :: Bit -- Capture/Compare 4 DMA request enable
CC3DE :: Bit -- Capture/Compare 3 DMA request enable
CC2DE :: Bit -- Capture/Compare 2 DMA request enable
CC1DE :: Bit -- Capture/Compare 1 DMA request enable
UDE :: Bit -- Update DMA request enable
_ :: Bit -- (Reserved)
TIE :: Bit -- Trigger interrupt enable
_ :: Bit -- (Reserved)
CC4IE :: Bit -- Capture/Compare 4 interrupt enable
CC3IE :: Bit -- Capture/Compare 3 interrupt enable
CC2IE :: Bit -- Capture/Compare 2 interrupt enable
CC1IE :: Bit -- Capture/Compare 1 interrupt enable
UIE :: Bit -- Update interrupt enable
SR 0x10 - status register
_ :: Bits 19 -- (Reserved)
CC4OF :: Bit -- Capture/Compare 4 overcapture flag
CC3OF :: Bit -- Capture/Compare 3 overcapture flag
CC2OF :: Bit -- Capture/compare 2 overcapture flag
CC1OF :: Bit -- Capture/Compare 1 overcapture flag
_ :: Bits 2 -- (Reserved)
TIF :: Bit -- Trigger interrupt flag
_ :: Bit -- (Reserved)
CC4IF :: Bit -- Capture/Compare 4 interrupt flag
CC3IF :: Bit -- Capture/Compare 3 interrupt flag
CC2IF :: Bit -- Capture/Compare 2 interrupt flag
CC1IF :: Bit -- Capture/compare 1 interrupt flag
UIF :: Bit -- Update interrupt flag
EGR 0x14 - event generation register
_ :: Bits 25 -- (Reserved)
TG :: Bit -- Trigger generation
_ :: Bit -- (Reserved)
CC4G :: Bit -- Capture/compare 4 generation
CC3G :: Bit -- Capture/compare 3 generation
CC2G :: Bit -- Capture/compare 2 generation
CC1G :: Bit -- Capture/compare 1 generation
UG :: Bit -- Update generation
CCMR1_Output 0x18 - capture/compare mode register 1 (output mode)
_ :: Bits 16 -- (Reserved)
OC2CE :: Bit -- OC2CE
OC2M :: Bits 3 -- OC2M
OC2PE :: Bit -- OC2PE
OC2FE :: Bit -- OC2FE
CC2S :: Bits 2 -- CC2S
OC1CE :: Bit -- OC1CE
OC1M :: Bits 3 -- OC1M
OC1PE :: Bit -- OC1PE
OC1FE :: Bit -- OC1FE
CC1S :: Bits 2 -- CC1S
CCMR1_Input 0x18 - capture/compare mode register 1 (input mode)
_ :: Bits 16 -- (Reserved)
IC2F :: Bits 4 -- Input capture 2 filter
IC2PSC :: Bits 2 -- Input capture 2 prescaler
CC2S :: Bits 2 -- Capture/Compare 2 selection
IC1F :: Bits 4 -- Input capture 1 filter
IC1PSC :: Bits 2 -- Input capture 1 prescaler
CC1S :: Bits 2 -- Capture/Compare 1 selection
CCMR2_Output 0x1c - capture/compare mode register 2 (output mode)
_ :: Bits 16 -- (Reserved)
OC4CE :: Bit -- O24CE
OC4M :: Bits 3 -- OC4M
OC4PE :: Bit -- OC4PE
OC4FE :: Bit -- OC4FE
CC4S :: Bits 2 -- CC4S
OC3CE :: Bit -- OC3CE
OC3M :: Bits 3 -- OC3M
OC3PE :: Bit -- OC3PE
OC3FE :: Bit -- OC3FE
CC3S :: Bits 2 -- CC3S
CCMR2_Input 0x1c - capture/compare mode register 2 (input mode)
_ :: Bits 16 -- (Reserved)
IC4F :: Bits 4 -- Input capture 4 filter
IC4PSC :: Bits 2 -- Input capture 4 prescaler
CC4S :: Bits 2 -- Capture/Compare 4 selection
IC3F :: Bits 4 -- Input capture 3 filter
IC3PSC :: Bits 2 -- Input capture 3 prescaler
CC3S :: Bits 2 -- Capture/compare 3 selection
CCER 0x20 - capture/compare enable register
_ :: Bits 16 -- (Reserved)
CC4NP :: Bit -- Capture/Compare 4 output Polarity
_ :: Bit -- (Reserved)
CC4P :: Bit -- Capture/Compare 3 output Polarity
CC4E :: Bit -- Capture/Compare 4 output enable
CC3NP :: Bit -- Capture/Compare 3 output Polarity
_ :: Bit -- (Reserved)
CC3P :: Bit -- Capture/Compare 3 output Polarity
CC3E :: Bit -- Capture/Compare 3 output enable
CC2NP :: Bit -- Capture/Compare 2 output Polarity
_ :: Bit -- (Reserved)
CC2P :: Bit -- Capture/Compare 2 output Polarity
CC2E :: Bit -- Capture/Compare 2 output enable
CC1NP :: Bit -- Capture/Compare 1 output Polarity
_ :: Bit -- (Reserved)
CC1P :: Bit -- Capture/Compare 1 output Polarity
CC1E :: Bit -- Capture/Compare 1 output enable
CNT 0x24 - counter
_ :: Bits 16 -- (Reserved)
CNT :: Bits 16 -- Counter value
PSC 0x28 - prescaler
_ :: Bits 16 -- (Reserved)
PSC :: Bits 16 -- Prescaler value
ARR 0x2c - auto-reload register
_ :: Bits 16 -- (Reserved)
ARR :: Bits 16 -- Auto-reload value
CCR1 0x34 - capture/compare register
_ :: Bits 16 -- (Reserved)
CCR :: Bits 16 -- Capture/Compare value
CCR2 0x38 - capture/compare register
_ :: Bits 16 -- (Reserved)
CCR :: Bits 16 -- Capture/Compare value
CCR3 0x3c - capture/compare register
_ :: Bits 16 -- (Reserved)
CCR :: Bits 16 -- Capture/Compare value
CCR4 0x40 - capture/compare register
_ :: Bits 16 -- (Reserved)
CCR :: Bits 16 -- Capture/Compare value
DCR 0x48 - DMA control register
_ :: Bits 19 -- (Reserved)
DBL :: Bits 5 -- DMA burst length
_ :: Bits 3 -- (Reserved)
DBA :: Bits 5 -- DMA base address
DMAR 0x4c - DMA address for full transfer
_ :: Bits 16 -- (Reserved)
DMAB :: Bits 16 -- DMA register for burst accesses
TIM4 0x40000800
Derived from TIM3
TIM5 0x40000c00 General-purpose-timers
CR1 0x0 - control register 1
_ :: Bits 22 -- (Reserved)
CKD :: Bits 2 -- Clock division
ARPE :: Bit -- Auto-reload preload enable
CMS :: Bits 2 -- Center-aligned mode selection
DIR :: Bit -- Direction
OPM :: Bit -- One-pulse mode
URS :: Bit -- Update request source
UDIS :: Bit -- Update disable
CEN :: Bit -- Counter enable
CR2 0x4 - control register 2
_ :: Bits 24 -- (Reserved)
TI1S :: Bit -- TI1 selection
MMS :: Bits 3 -- Master mode selection
CCDS :: Bit -- Capture/compare DMA selection
_ :: Bits 3 -- (Reserved)
SMCR 0x8 - slave mode control register
_ :: Bits 16 -- (Reserved)
ETP :: Bit -- External trigger polarity
ECE :: Bit -- External clock enable
ETPS :: Bits 2 -- External trigger prescaler
ETF :: Bits 4 -- External trigger filter
MSM :: Bit -- Master/Slave mode
TS :: Bits 3 -- Trigger selection
_ :: Bit -- (Reserved)
SMS :: Bits 3 -- Slave mode selection
DIER 0xc - DMA/Interrupt enable register
_ :: Bits 17 -- (Reserved)
TDE :: Bit -- Trigger DMA request enable
_ :: Bit -- (Reserved)
CC4DE :: Bit -- Capture/Compare 4 DMA request enable
CC3DE :: Bit -- Capture/Compare 3 DMA request enable
CC2DE :: Bit -- Capture/Compare 2 DMA request enable
CC1DE :: Bit -- Capture/Compare 1 DMA request enable
UDE :: Bit -- Update DMA request enable
_ :: Bit -- (Reserved)
TIE :: Bit -- Trigger interrupt enable
_ :: Bit -- (Reserved)
CC4IE :: Bit -- Capture/Compare 4 interrupt enable
CC3IE :: Bit -- Capture/Compare 3 interrupt enable
CC2IE :: Bit -- Capture/Compare 2 interrupt enable
CC1IE :: Bit -- Capture/Compare 1 interrupt enable
UIE :: Bit -- Update interrupt enable
SR 0x10 - status register
_ :: Bits 19 -- (Reserved)
CC4OF :: Bit -- Capture/Compare 4 overcapture flag
CC3OF :: Bit -- Capture/Compare 3 overcapture flag
CC2OF :: Bit -- Capture/compare 2 overcapture flag
CC1OF :: Bit -- Capture/Compare 1 overcapture flag
_ :: Bits 2 -- (Reserved)
TIF :: Bit -- Trigger interrupt flag
_ :: Bit -- (Reserved)
CC4IF :: Bit -- Capture/Compare 4 interrupt flag
CC3IF :: Bit -- Capture/Compare 3 interrupt flag
CC2IF :: Bit -- Capture/Compare 2 interrupt flag
CC1IF :: Bit -- Capture/compare 1 interrupt flag
UIF :: Bit -- Update interrupt flag
EGR 0x14 - event generation register
_ :: Bits 25 -- (Reserved)
TG :: Bit -- Trigger generation
_ :: Bit -- (Reserved)
CC4G :: Bit -- Capture/compare 4 generation
CC3G :: Bit -- Capture/compare 3 generation
CC2G :: Bit -- Capture/compare 2 generation
CC1G :: Bit -- Capture/compare 1 generation
UG :: Bit -- Update generation
CCMR1_Output 0x18 - capture/compare mode register 1 (output mode)
_ :: Bits 16 -- (Reserved)
OC2CE :: Bit -- OC2CE
OC2M :: Bits 3 -- OC2M
OC2PE :: Bit -- OC2PE
OC2FE :: Bit -- OC2FE
CC2S :: Bits 2 -- CC2S
OC1CE :: Bit -- OC1CE
OC1M :: Bits 3 -- OC1M
OC1PE :: Bit -- OC1PE
OC1FE :: Bit -- OC1FE
CC1S :: Bits 2 -- CC1S
CCMR1_Input 0x18 - capture/compare mode register 1 (input mode)
_ :: Bits 16 -- (Reserved)
IC2F :: Bits 4 -- Input capture 2 filter
IC2PSC :: Bits 2 -- Input capture 2 prescaler
CC2S :: Bits 2 -- Capture/Compare 2 selection
IC1F :: Bits 4 -- Input capture 1 filter
IC1PSC :: Bits 2 -- Input capture 1 prescaler
CC1S :: Bits 2 -- Capture/Compare 1 selection
CCMR2_Output 0x1c - capture/compare mode register 2 (output mode)
_ :: Bits 16 -- (Reserved)
OC4CE :: Bit -- O24CE
OC4M :: Bits 3 -- OC4M
OC4PE :: Bit -- OC4PE
OC4FE :: Bit -- OC4FE
CC4S :: Bits 2 -- CC4S
OC3CE :: Bit -- OC3CE
OC3M :: Bits 3 -- OC3M
OC3PE :: Bit -- OC3PE
OC3FE :: Bit -- OC3FE
CC3S :: Bits 2 -- CC3S
CCMR2_Input 0x1c - capture/compare mode register 2 (input mode)
_ :: Bits 16 -- (Reserved)
IC4F :: Bits 4 -- Input capture 4 filter
IC4PSC :: Bits 2 -- Input capture 4 prescaler
CC4S :: Bits 2 -- Capture/Compare 4 selection
IC3F :: Bits 4 -- Input capture 3 filter
IC3PSC :: Bits 2 -- Input capture 3 prescaler
CC3S :: Bits 2 -- Capture/compare 3 selection
CCER 0x20 - capture/compare enable register
_ :: Bits 16 -- (Reserved)
CC4NP :: Bit -- Capture/Compare 4 output Polarity
_ :: Bit -- (Reserved)
CC4P :: Bit -- Capture/Compare 3 output Polarity
CC4E :: Bit -- Capture/Compare 4 output enable
CC3NP :: Bit -- Capture/Compare 3 output Polarity
_ :: Bit -- (Reserved)
CC3P :: Bit -- Capture/Compare 3 output Polarity
CC3E :: Bit -- Capture/Compare 3 output enable
CC2NP :: Bit -- Capture/Compare 2 output Polarity
_ :: Bit -- (Reserved)
CC2P :: Bit -- Capture/Compare 2 output Polarity
CC2E :: Bit -- Capture/Compare 2 output enable
CC1NP :: Bit -- Capture/Compare 1 output Polarity
_ :: Bit -- (Reserved)
CC1P :: Bit -- Capture/Compare 1 output Polarity
CC1E :: Bit -- Capture/Compare 1 output enable
CNT 0x24 - counter
CNT :: Bits 32 -- Counter value
PSC 0x28 - prescaler
_ :: Bits 16 -- (Reserved)
PSC :: Bits 16 -- Prescaler value
ARR 0x2c - auto-reload register
ARR :: Bits 32 -- Auto-reload value
CCR1 0x34 - capture/compare register
CCR :: Bits 32 -- Capture/Compare value
CCR2 0x38 - capture/compare register
CCR :: Bits 32 -- Capture/Compare value
CCR3 0x3c - capture/compare register
CCR :: Bits 32 -- Capture/Compare value
CCR4 0x40 - capture/compare register
CCR :: Bits 32 -- Capture/Compare value
DCR 0x48 - DMA control register
_ :: Bits 19 -- (Reserved)
DBL :: Bits 5 -- DMA burst length
_ :: Bits 3 -- (Reserved)
DBA :: Bits 5 -- DMA base address
DMAR 0x4c - DMA address for full transfer
_ :: Bits 16 -- (Reserved)
DMAB :: Bits 16 -- DMA register for burst accesses
OR 0x50 - TIM5 option register
_ :: Bits 24 -- (Reserved)
IT4_RMP :: Bits 2 -- Timer Input 4 remap
_ :: Bits 6 -- (Reserved)
TIM6 0x40001000 Basic timers
CR1 0x0 - control register 1
_ :: Bits 24 -- (Reserved)
ARPE :: Bit -- Auto-reload preload enable
_ :: Bits 3 -- (Reserved)
OPM :: Bit -- One-pulse mode
URS :: Bit -- Update request source
UDIS :: Bit -- Update disable
CEN :: Bit -- Counter enable
CR2 0x4 - control register 2
_ :: Bits 25 -- (Reserved)
MMS :: Bits 3 -- Master mode selection
_ :: Bits 4 -- (Reserved)
DIER 0xc - DMA/Interrupt enable register
_ :: Bits 23 -- (Reserved)
UDE :: Bit -- Update DMA request enable
_ :: Bits 7 -- (Reserved)
UIE :: Bit -- Update interrupt enable
SR 0x10 - status register
_ :: Bits 31 -- (Reserved)
UIF :: Bit -- Update interrupt flag
EGR 0x14 - event generation register
_ :: Bits 31 -- (Reserved)
UG :: Bit -- Update generation
CNT 0x24 - counter
_ :: Bits 16 -- (Reserved)
CNT :: Bits 16 -- Low counter value
PSC 0x28 - prescaler
_ :: Bits 16 -- (Reserved)
PSC :: Bits 16 -- Prescaler value
ARR 0x2c - auto-reload register
_ :: Bits 16 -- (Reserved)
ARR :: Bits 16 -- Low Auto-reload value
TIM7 0x40001400
Derived from TIM6
TIM12 0x40001800
Derived from TIM9
TIM13 0x40001c00
Derived from TIM10
TIM14 0x40002000
Derived from TIM10
RTC 0x40002800 Real-time clock
TR 0x0 - time register
_ :: Bits 9 -- (Reserved)
PM :: Bit -- AM/PM notation
HT :: Bits 2 -- Hour tens in BCD format
HU :: Bits 4 -- Hour units in BCD format
_ :: Bit -- (Reserved)
MNT :: Bits 3 -- Minute tens in BCD format
MNU :: Bits 4 -- Minute units in BCD format
_ :: Bit -- (Reserved)
ST :: Bits 3 -- Second tens in BCD format
SU :: Bits 4 -- Second units in BCD format
DR 0x4 - date register
_ :: Bits 8 -- (Reserved)
YT :: Bits 4 -- Year tens in BCD format
YU :: Bits 4 -- Year units in BCD format
WDU :: Bits 3 -- Week day units
MT :: Bit -- Month tens in BCD format
MU :: Bits 4 -- Month units in BCD format
_ :: Bits 2 -- (Reserved)
DT :: Bits 2 -- Date tens in BCD format
DU :: Bits 4 -- Date units in BCD format
CR 0x8 - control register
_ :: Bits 8 -- (Reserved)
COE :: Bit -- Calibration output enable
OSEL :: Bits 2 -- Output selection
POL :: Bit -- Output polarity
COSEL :: Bit -- Calibration output selection
BKP :: Bit -- Backup
SUB1H :: Bit -- Subtract 1 hour (winter time change)
ADD1H :: Bit -- Add 1 hour (summer time change)
TSIE :: Bit -- Time-stamp interrupt enable
WUTIE :: Bit -- Wakeup timer interrupt enable
ALRBIE :: Bit -- Alarm B interrupt enable
ALRAIE :: Bit -- Alarm A interrupt enable
TSE :: Bit -- Time stamp enable
WUTE :: Bit -- Wakeup timer enable
ALRBE :: Bit -- Alarm B enable
ALRAE :: Bit -- Alarm A enable
DCE :: Bit -- Coarse digital calibration enable
FMT :: Bit -- Hour format
BYPSHAD :: Bit -- Bypass the shadow registers
REFCKON :: Bit -- Reference clock detection enable (50 or 60 Hz)
TSEDGE :: Bit -- Time-stamp event active edge
WUCKSEL :: Bits 3 -- Wakeup clock selection
ISR 0xc - initialization and status register
_ :: Bits 15 -- (Reserved)
RECALPF :: Bit -- Recalibration pending Flag
_ :: Bit -- (Reserved)
TAMP2F :: Bit -- TAMPER2 detection flag
TAMP1F :: Bit -- Tamper detection flag
TSOVF :: Bit -- Time-stamp overflow flag
TSF :: Bit -- Time-stamp flag
WUTF :: Bit -- Wakeup timer flag
ALRBF :: Bit -- Alarm B flag
ALRAF :: Bit -- Alarm A flag
INIT :: Bit -- Initialization mode
INITF :: Bit -- Initialization flag
RSF :: Bit -- Registers synchronization flag
INITS :: Bit -- Initialization status flag
SHPF :: Bit -- Shift operation pending
WUTWF :: Bit -- Wakeup timer write flag
ALRBWF :: Bit -- Alarm B write flag
ALRAWF :: Bit -- Alarm A write flag
PRER 0x10 - prescaler register
_ :: Bits 9 -- (Reserved)
PREDIV_A :: Bits 7 -- Asynchronous prescaler factor
_ :: Bit -- (Reserved)
PREDIV_S :: Bits 15 -- Synchronous prescaler factor
WUTR 0x14 - wakeup timer register
_ :: Bits 16 -- (Reserved)
WUT :: Bits 16 -- Wakeup auto-reload value bits
CALIBR 0x18 - calibration register
_ :: Bits 24 -- (Reserved)
DCS :: Bit -- Digital calibration sign
_ :: Bits 2 -- (Reserved)
DC :: Bits 5 -- Digital calibration
ALRMAR 0x1c - Alarm A register
MSK4 :: Bit -- Alarm date mask
WDSEL :: Bit -- Week day selection
DT :: Bits 2 -- Date tens in BCD format
DU :: Bits 4 -- Date units or day in BCD format
MSK3 :: Bit -- Alarm hours mask
PM :: Bit -- AM/PM notation
HT :: Bits 2 -- Hour tens in BCD format
HU :: Bits 4 -- Hour units in BCD format
MSK2 :: Bit -- Alarm minutes mask
MNT :: Bits 3 -- Minute tens in BCD format
MNU :: Bits 4 -- Minute units in BCD format
MSK1 :: Bit -- Alarm seconds mask
ST :: Bits 3 -- Second tens in BCD format
SU :: Bits 4 -- Second units in BCD format
ALRMBR 0x20 - Alarm B register
MSK4 :: Bit -- Alarm date mask
WDSEL :: Bit -- Week day selection
DT :: Bits 2 -- Date tens in BCD format
DU :: Bits 4 -- Date units or day in BCD format
MSK3 :: Bit -- Alarm hours mask
PM :: Bit -- AM/PM notation
HT :: Bits 2 -- Hour tens in BCD format
HU :: Bits 4 -- Hour units in BCD format
MSK2 :: Bit -- Alarm minutes mask
MNT :: Bits 3 -- Minute tens in BCD format
MNU :: Bits 4 -- Minute units in BCD format
MSK1 :: Bit -- Alarm seconds mask
ST :: Bits 3 -- Second tens in BCD format
SU :: Bits 4 -- Second units in BCD format
WPR 0x24 - write protection register
_ :: Bits 24 -- (Reserved)
KEY :: Bits 8 -- Write protection key
SSR 0x28 - sub second register
_ :: Bits 16 -- (Reserved)
SS :: Bits 16 -- Sub second value
SHIFTR 0x2c - shift control register
ADD1S :: Bit -- Add one second
_ :: Bits 16 -- (Reserved)
SUBFS :: Bits 15 -- Subtract a fraction of a second
CALR 0x3c - calibration register
_ :: Bits 16 -- (Reserved)
CALP :: Bit -- Increase frequency of RTC by 488.5 ppm
CALW8 :: Bit -- Use an 8-second calibration cycle period
CALW16 :: Bit -- Use a 16-second calibration cycle period
_ :: Bits 4 -- (Reserved)
CALM :: Bits 9 -- Calibration minus
TAFCR 0x40 - tamper and alternate function configuration register
_ :: Bits 13 -- (Reserved)
ALARMOUTTYPE :: Bit -- AFO_ALARM output type
TSINSEL :: Bit -- TIMESTAMP mapping
TAMP1INSEL :: Bit -- TAMPER1 mapping
TAMPPUDIS :: Bit -- TAMPER pull-up disable
TAMPPRCH :: Bits 2 -- Tamper precharge duration
TAMPFLT :: Bits 2 -- Tamper filter count
TAMPFREQ :: Bits 3 -- Tamper sampling frequency
TAMPTS :: Bit -- Activate timestamp on tamper detection event
_ :: Bits 2 -- (Reserved)
TAMP2TRG :: Bit -- Active level for tamper 2
TAMP2E :: Bit -- Tamper 2 detection enable
TAMPIE :: Bit -- Tamper interrupt enable
TAMP1TRG :: Bit -- Active level for tamper 1
TAMP1E :: Bit -- Tamper 1 detection enable
ALRMASSR 0x44 - Alarm A sub-second register
_ :: Bits 4 -- (Reserved)
MASKSS :: Bits 4 -- Mask the most-significant bits starting at this bit
_ :: Bits 9 -- (Reserved)
SS :: Bits 15 -- Sub seconds value
ALRMBSSR 0x48 - Alarm B sub-second register
_ :: Bits 4 -- (Reserved)
MASKSS :: Bits 4 -- Mask the most-significant bits starting at this bit
_ :: Bits 9 -- (Reserved)
SS :: Bits 15 -- Sub seconds value
BKP0R 0x50 - backup register
BKP :: Bits 32 -- BKP
BKP1R 0x54 - backup register
BKP :: Bits 32 -- BKP
BKP2R 0x58 - backup register
BKP :: Bits 32 -- BKP
BKP3R 0x5c - backup register
BKP :: Bits 32 -- BKP
BKP4R 0x60 - backup register
BKP :: Bits 32 -- BKP
BKP5R 0x64 - backup register
BKP :: Bits 32 -- BKP
BKP6R 0x68 - backup register
BKP :: Bits 32 -- BKP
BKP7R 0x6c - backup register
BKP :: Bits 32 -- BKP
BKP8R 0x70 - backup register
BKP :: Bits 32 -- BKP
BKP9R 0x74 - backup register
BKP :: Bits 32 -- BKP
BKP10R 0x78 - backup register
BKP :: Bits 32 -- BKP
BKP11R 0x7c - backup register
BKP :: Bits 32 -- BKP
BKP12R 0x80 - backup register
BKP :: Bits 32 -- BKP
BKP13R 0x84 - backup register
BKP :: Bits 32 -- BKP
BKP14R 0x88 - backup register
BKP :: Bits 32 -- BKP
BKP15R 0x8c - backup register
BKP :: Bits 32 -- BKP
BKP16R 0x90 - backup register
BKP :: Bits 32 -- BKP
BKP17R 0x94 - backup register
BKP :: Bits 32 -- BKP
BKP18R 0x98 - backup register
BKP :: Bits 32 -- BKP
BKP19R 0x9c - backup register
BKP :: Bits 32 -- BKP
WWDG 0x40002c00 Window watchdog
CR 0x0 - Control register
_ :: Bits 24 -- (Reserved)
WDGA :: Bit -- Activation bit
T :: Bits 7 -- 7-bit counter (MSB to LSB)
CFR 0x4 - Configuration register
_ :: Bits 22 -- (Reserved)
EWI :: Bit -- Early wakeup interrupt
WDGTB :: Bits 2 -- Timer base
W :: Bits 7 -- 7-bit window value
SR 0x8 - Status register
_ :: Bits 31 -- (Reserved)
EWIF :: Bit -- Early wakeup interrupt flag
IWDG 0x40003000 Independent watchdog
KR 0x0 - Key register
_ :: Bits 16 -- (Reserved)
KEY :: Bits 16 -- Key value (write only, read 0000h)
PR 0x4 - Prescaler register
_ :: Bits 29 -- (Reserved)
PR :: Bits 3 -- Prescaler divider
RLR 0x8 - Reload register
_ :: Bits 20 -- (Reserved)
RL :: Bits 12 -- Watchdog counter reload value
SR 0xc - Status register
_ :: Bits 30 -- (Reserved)
RVU :: Bit -- Watchdog counter reload value update
PVU :: Bit -- Watchdog prescaler value update
I2S2ext 0x40003400
Derived from SPI1
SPI2 0x40003800
Derived from SPI1
SPI3 0x40003c00
Derived from SPI1
I2S3ext 0x40004000
Derived from SPI1
USART2 0x40004400
Derived from USART1
USART3 0x40004800
Derived from USART1
UART4 0x40004c00 Universal synchronous asynchronous receiver transmitter
SR 0x0 - Status register
_ :: Bits 23 -- (Reserved)
LBD :: Bit -- LIN break detection flag
TXE :: Bit -- Transmit data register empty
TC :: Bit -- Transmission complete
RXNE :: Bit -- Read data register not empty
IDLE :: Bit -- IDLE line detected
ORE :: Bit -- Overrun error
NF :: Bit -- Noise detected flag
FE :: Bit -- Framing error
PE :: Bit -- Parity error
DR 0x4 - Data register
_ :: Bits 23 -- (Reserved)
DR :: Bits 9 -- Data value
BRR 0x8 - Baud rate register
_ :: Bits 16 -- (Reserved)
DIV_Mantissa :: Bits 12 -- mantissa of USARTDIV
DIV_Fraction :: Bits 4 -- fraction of USARTDIV
CR1 0xc - Control register 1
_ :: Bits 16 -- (Reserved)
OVER8 :: Bit -- Oversampling mode
_ :: Bit -- (Reserved)
UE :: Bit -- USART enable
M :: Bit -- Word length
WAKE :: Bit -- Wakeup method
PCE :: Bit -- Parity control enable
PS :: Bit -- Parity selection
PEIE :: Bit -- PE interrupt enable
TXEIE :: Bit -- TXE interrupt enable
TCIE :: Bit -- Transmission complete interrupt enable
RXNEIE :: Bit -- RXNE interrupt enable
IDLEIE :: Bit -- IDLE interrupt enable
TE :: Bit -- Transmitter enable
RE :: Bit -- Receiver enable
RWU :: Bit -- Receiver wakeup
SBK :: Bit -- Send break
CR2 0x10 - Control register 2
_ :: Bits 17 -- (Reserved)
LINEN :: Bit -- LIN mode enable
STOP :: Bits 2 -- STOP bits
_ :: Bits 5 -- (Reserved)
LBDIE :: Bit -- LIN break detection interrupt enable
LBDL :: Bit -- lin break detection length
_ :: Bit -- (Reserved)
ADD :: Bits 4 -- Address of the USART node
CR3 0x14 - Control register 3
_ :: Bits 20 -- (Reserved)
ONEBIT :: Bit -- One sample bit method enable
_ :: Bits 3 -- (Reserved)
DMAT :: Bit -- DMA enable transmitter
DMAR :: Bit -- DMA enable receiver
_ :: Bits 2 -- (Reserved)
HDSEL :: Bit -- Half-duplex selection
IRLP :: Bit -- IrDA low-power
IREN :: Bit -- IrDA mode enable
EIE :: Bit -- Error interrupt enable
UART5 0x40005000
Derived from UART4
I2C1 0x40005400 Inter-integrated circuit
CR1 0x0 - Control register 1
_ :: Bits 16 -- (Reserved)
SWRST :: Bit -- Software reset
_ :: Bit -- (Reserved)
ALERT :: Bit -- SMBus alert
PEC :: Bit -- Packet error checking
POS :: Bit -- Acknowledge/PEC Position (for data reception)
ACK :: Bit -- Acknowledge enable
STOP :: Bit -- Stop generation
START :: Bit -- Start generation
NOSTRETCH :: Bit -- Clock stretching disable (Slave mode)
ENGC :: Bit -- General call enable
ENPEC :: Bit -- PEC enable
ENARP :: Bit -- ARP enable
SMBTYPE :: Bit -- SMBus type
_ :: Bit -- (Reserved)
SMBUS :: Bit -- SMBus mode
PE :: Bit -- Peripheral enable
CR2 0x4 - Control register 2
_ :: Bits 19 -- (Reserved)
LAST :: Bit -- DMA last transfer
DMAEN :: Bit -- DMA requests enable
ITBUFEN :: Bit -- Buffer interrupt enable
ITEVTEN :: Bit -- Event interrupt enable
ITERREN :: Bit -- Error interrupt enable
_ :: Bits 2 -- (Reserved)
FREQ :: Bits 6 -- Peripheral clock frequency
OAR1 0x8 - Own address register 1
_ :: Bits 16 -- (Reserved)
ADDMODE :: Bit -- Addressing mode (slave mode)
_ :: Bits 5 -- (Reserved)
ADD :: Bits 10 -- Interface address
OAR2 0xc - Own address register 2
_ :: Bits 24 -- (Reserved)
ADD2 :: Bits 7 -- Interface address
ENDUAL :: Bit -- Dual addressing mode enable
DR 0x10 - Data register
_ :: Bits 24 -- (Reserved)
DR :: Bits 8 -- 8-bit data register
SR1 0x14 - Status register 1
_ :: Bits 16 -- (Reserved)
SMBALERT :: Bit -- SMBus alert
TIMEOUT :: Bit -- Timeout or Tlow error
_ :: Bit -- (Reserved)
PECERR :: Bit -- PEC Error in reception
OVR :: Bit -- Overrun/Underrun
AF :: Bit -- Acknowledge failure
ARLO :: Bit -- Arbitration lost (master mode)
BERR :: Bit -- Bus error
TxE :: Bit -- Data register empty (transmitters)
RxNE :: Bit -- Data register not empty (receivers)
_ :: Bit -- (Reserved)
STOPF :: Bit -- Stop detection (slave mode)
ADD10 :: Bit -- 10-bit header sent (Master mode)
BTF :: Bit -- Byte transfer finished
ADDR :: Bit -- Address sent (master mode)/matched (slave mode)
SB :: Bit -- Start bit (Master mode)
SR2 0x18 - Status register 2
_ :: Bits 16 -- (Reserved)
PEC :: Bits 8 -- acket error checking register
DUALF :: Bit -- Dual flag (Slave mode)
SMBHOST :: Bit -- SMBus host header (Slave mode)
SMBDEFAULT :: Bit -- SMBus device default address (Slave mode)
GENCALL :: Bit -- General call address (Slave mode)
_ :: Bit -- (Reserved)
TRA :: Bit -- Transmitter/receiver
BUSY :: Bit -- Bus busy
MSL :: Bit -- Master/slave
CCR 0x1c - Clock control register
_ :: Bits 16 -- (Reserved)
F_S :: Bit -- I2C master mode selection
DUTY :: Bit -- Fast mode duty cycle
_ :: Bits 2 -- (Reserved)
CCR :: Bits 12 -- Clock control register in Fast/Standard mode (Master mode)
TRISE 0x20 - TRISE register
_ :: Bits 26 -- (Reserved)
TRISE :: Bits 6 -- Maximum rise time in Fast/Standard mode (Master mode)
I2C2 0x40005800
Derived from I2C1
I2C3 0x40005c00
Derived from I2C1
CAN1 0x40006400 Controller area network
MCR 0x0 - master control register
_ :: Bits 15 -- (Reserved)
DBF :: Bit -- DBF
RESET :: Bit -- RESET
_ :: Bits 7 -- (Reserved)
TTCM :: Bit -- TTCM
ABOM :: Bit -- ABOM
AWUM :: Bit -- AWUM
NART :: Bit -- NART
RFLM :: Bit -- RFLM
TXFP :: Bit -- TXFP
SLEEP :: Bit -- SLEEP
INRQ :: Bit -- INRQ
MSR 0x4 - master status register
_ :: Bits 20 -- (Reserved)
RX :: Bit -- RX
SAMP :: Bit -- SAMP
RXM :: Bit -- RXM
TXM :: Bit -- TXM
_ :: Bits 3 -- (Reserved)
SLAKI :: Bit -- SLAKI
WKUI :: Bit -- WKUI
ERRI :: Bit -- ERRI
SLAK :: Bit -- SLAK
INAK :: Bit -- INAK
TSR 0x8 - transmit status register
LOW2 :: Bit -- Lowest priority flag for mailbox 2
LOW1 :: Bit -- Lowest priority flag for mailbox 1
LOW0 :: Bit -- Lowest priority flag for mailbox 0
TME2 :: Bit -- Lowest priority flag for mailbox 2
TME1 :: Bit -- Lowest priority flag for mailbox 1
TME0 :: Bit -- Lowest priority flag for mailbox 0
CODE :: Bits 2 -- CODE
ABRQ2 :: Bit -- ABRQ2
_ :: Bits 3 -- (Reserved)
TERR2 :: Bit -- TERR2
ALST2 :: Bit -- ALST2
TXOK2 :: Bit -- TXOK2
RQCP2 :: Bit -- RQCP2
ABRQ1 :: Bit -- ABRQ1
_ :: Bits 3 -- (Reserved)
TERR1 :: Bit -- TERR1
ALST1 :: Bit -- ALST1
TXOK1 :: Bit -- TXOK1
RQCP1 :: Bit -- RQCP1
ABRQ0 :: Bit -- ABRQ0
_ :: Bits 3 -- (Reserved)
TERR0 :: Bit -- TERR0
ALST0 :: Bit -- ALST0
TXOK0 :: Bit -- TXOK0
RQCP0 :: Bit -- RQCP0
RF0R 0xc - receive FIFO 0 register
_ :: Bits 26 -- (Reserved)
RFOM :: Bit -- RFOM0
FOVR :: Bit -- FOVR0
FULL :: Bit -- FULL0
_ :: Bit -- (Reserved)
FMP :: Bits 2 -- FMP0
RF1R 0x10 - receive FIFO 1 register
_ :: Bits 26 -- (Reserved)
RFOM :: Bit -- RFOM0
FOVR :: Bit -- FOVR0
FULL :: Bit -- FULL0
_ :: Bit -- (Reserved)
FMP :: Bits 2 -- FMP0
IER 0x14 - interrupt enable register
_ :: Bits 14 -- (Reserved)
SLKIE :: Bit -- SLKIE
WKUIE :: Bit -- WKUIE
ERRIE :: Bit -- ERRIE
_ :: Bits 3 -- (Reserved)
LECIE :: Bit -- LECIE
BOFIE :: Bit -- BOFIE
EPVIE :: Bit -- EPVIE
EWGIE :: Bit -- EWGIE
_ :: Bit -- (Reserved)
FOVIE1 :: Bit -- FOVIE1
FFIE1 :: Bit -- FFIE1
FMPIE1 :: Bit -- FMPIE1
FOVIE0 :: Bit -- FOVIE0
FFIE0 :: Bit -- FFIE0
FMPIE0 :: Bit -- FMPIE0
TMEIE :: Bit -- TMEIE
ESR 0x18 - interrupt enable register
REC :: Bits 8 -- REC
TEC :: Bits 8 -- TEC
_ :: Bits 9 -- (Reserved)
LEC :: Bits 3 -- LEC
_ :: Bit -- (Reserved)
BOFF :: Bit -- BOFF
EPVF :: Bit -- EPVF
EWGF :: Bit -- EWGF
BTR 0x1c - bit timing register
SILM :: Bit -- SILM
LBKM :: Bit -- LBKM
_ :: Bits 4 -- (Reserved)
SJW :: Bits 2 -- SJW
_ :: Bit -- (Reserved)
TS2 :: Bits 3 -- TS2
TS1 :: Bits 4 -- TS1
_ :: Bits 6 -- (Reserved)
BRP :: Bits 10 -- BRP
TIR 0x180 - TX mailbox identifier register
STID :: Bits 11 -- STID
EXID :: Bits 18 -- EXID
IDE :: Bit -- IDE
RTR :: Bit -- RTR
TXRQ :: Bit -- TXRQ
TDTR 0x184 - mailbox data length control and time stamp register
TIME :: Bits 16 -- TIME
_ :: Bits 7 -- (Reserved)
TGT :: Bit -- TGT
_ :: Bits 4 -- (Reserved)
DLC :: Bits 4 -- DLC
TDLR 0x188 - mailbox data low register
DATA3 :: Bits 8 -- DATA3
DATA2 :: Bits 8 -- DATA2
DATA1 :: Bits 8 -- DATA1
DATA0 :: Bits 8 -- DATA0
TDHR 0x18c - mailbox data high register
DATA7 :: Bits 8 -- DATA7
DATA6 :: Bits 8 -- DATA6
DATA5 :: Bits 8 -- DATA5
DATA4 :: Bits 8 -- DATA4
TIR 0x190 - TX mailbox identifier register
STID :: Bits 11 -- STID
EXID :: Bits 18 -- EXID
IDE :: Bit -- IDE
RTR :: Bit -- RTR
TXRQ :: Bit -- TXRQ
TDTR 0x194 - mailbox data length control and time stamp register
TIME :: Bits 16 -- TIME
_ :: Bits 7 -- (Reserved)
TGT :: Bit -- TGT
_ :: Bits 4 -- (Reserved)
DLC :: Bits 4 -- DLC
TDLR 0x198 - mailbox data low register
DATA3 :: Bits 8 -- DATA3
DATA2 :: Bits 8 -- DATA2
DATA1 :: Bits 8 -- DATA1
DATA0 :: Bits 8 -- DATA0
TDHR 0x19c - mailbox data high register
DATA7 :: Bits 8 -- DATA7
DATA6 :: Bits 8 -- DATA6
DATA5 :: Bits 8 -- DATA5
DATA4 :: Bits 8 -- DATA4
TIR 0x1a0 - TX mailbox identifier register
STID :: Bits 11 -- STID
EXID :: Bits 18 -- EXID
IDE :: Bit -- IDE
RTR :: Bit -- RTR
TXRQ :: Bit -- TXRQ
TDTR 0x1a4 - mailbox data length control and time stamp register
TIME :: Bits 16 -- TIME
_ :: Bits 7 -- (Reserved)
TGT :: Bit -- TGT
_ :: Bits 4 -- (Reserved)
DLC :: Bits 4 -- DLC
TDLR 0x1a8 - mailbox data low register
DATA3 :: Bits 8 -- DATA3
DATA2 :: Bits 8 -- DATA2
DATA1 :: Bits 8 -- DATA1
DATA0 :: Bits 8 -- DATA0
TDHR 0x1ac - mailbox data high register
DATA7 :: Bits 8 -- DATA7
DATA6 :: Bits 8 -- DATA6
DATA5 :: Bits 8 -- DATA5
DATA4 :: Bits 8 -- DATA4
RIR 0x1b0 - receive FIFO mailbox identifier register
STID :: Bits 11 -- STID
EXID :: Bits 18 -- EXID
IDE :: Bit -- IDE
RTR :: Bit -- RTR
_ :: Bit -- (Reserved)
RDTR 0x1b4 - mailbox data high register
TIME :: Bits 16 -- TIME
FMI :: Bits 8 -- FMI
_ :: Bits 4 -- (Reserved)
DLC :: Bits 4 -- DLC
RDLR 0x1b8 - mailbox data high register
DATA3 :: Bits 8 -- DATA3
DATA2 :: Bits 8 -- DATA2
DATA1 :: Bits 8 -- DATA1
DATA0 :: Bits 8 -- DATA0
RDHR 0x1bc - receive FIFO mailbox data high register
DATA7 :: Bits 8 -- DATA7
DATA6 :: Bits 8 -- DATA6
DATA5 :: Bits 8 -- DATA5
DATA4 :: Bits 8 -- DATA4
RIR 0x1c0 - receive FIFO mailbox identifier register
STID :: Bits 11 -- STID
EXID :: Bits 18 -- EXID
IDE :: Bit -- IDE
RTR :: Bit -- RTR
_ :: Bit -- (Reserved)
RDTR 0x1c4 - mailbox data high register
TIME :: Bits 16 -- TIME
FMI :: Bits 8 -- FMI
_ :: Bits 4 -- (Reserved)
DLC :: Bits 4 -- DLC
RDLR 0x1c8 - mailbox data high register
DATA3 :: Bits 8 -- DATA3
DATA2 :: Bits 8 -- DATA2
DATA1 :: Bits 8 -- DATA1
DATA0 :: Bits 8 -- DATA0
RDHR 0x1cc - receive FIFO mailbox data high register
DATA7 :: Bits 8 -- DATA7
DATA6 :: Bits 8 -- DATA6
DATA5 :: Bits 8 -- DATA5
DATA4 :: Bits 8 -- DATA4
FMR 0x200 - filter master register
_ :: Bits 18 -- (Reserved)
CAN2SB :: Bits 6 -- CAN2SB
_ :: Bits 7 -- (Reserved)
FINIT :: Bit -- FINIT
FM1R 0x204 - filter mode register
_ :: Bits 4 -- (Reserved)
FBM27 :: Bit -- Filter mode
FBM26 :: Bit -- Filter mode
FBM25 :: Bit -- Filter mode
FBM24 :: Bit -- Filter mode
FBM23 :: Bit -- Filter mode
FBM22 :: Bit -- Filter mode
FBM21 :: Bit -- Filter mode
FBM20 :: Bit -- Filter mode
FBM19 :: Bit -- Filter mode
FBM18 :: Bit -- Filter mode
FBM17 :: Bit -- Filter mode
FBM16 :: Bit -- Filter mode
FBM15 :: Bit -- Filter mode
FBM14 :: Bit -- Filter mode
FBM13 :: Bit -- Filter mode
FBM12 :: Bit -- Filter mode
FBM11 :: Bit -- Filter mode
FBM10 :: Bit -- Filter mode
FBM9 :: Bit -- Filter mode
FBM8 :: Bit -- Filter mode
FBM7 :: Bit -- Filter mode
FBM6 :: Bit -- Filter mode
FBM5 :: Bit -- Filter mode
FBM4 :: Bit -- Filter mode
FBM3 :: Bit -- Filter mode
FBM2 :: Bit -- Filter mode
FBM1 :: Bit -- Filter mode
FBM0 :: Bit -- Filter mode
FS1R 0x20c - filter scale register
_ :: Bits 4 -- (Reserved)
FSC27 :: Bit -- Filter scale configuration
FSC26 :: Bit -- Filter scale configuration
FSC25 :: Bit -- Filter scale configuration
FSC24 :: Bit -- Filter scale configuration
FSC23 :: Bit -- Filter scale configuration
FSC22 :: Bit -- Filter scale configuration
FSC21 :: Bit -- Filter scale configuration
FSC20 :: Bit -- Filter scale configuration
FSC19 :: Bit -- Filter scale configuration
FSC18 :: Bit -- Filter scale configuration
FSC17 :: Bit -- Filter scale configuration
FSC16 :: Bit -- Filter scale configuration
FSC15 :: Bit -- Filter scale configuration
FSC14 :: Bit -- Filter scale configuration
FSC13 :: Bit -- Filter scale configuration
FSC12 :: Bit -- Filter scale configuration
FSC11 :: Bit -- Filter scale configuration
FSC10 :: Bit -- Filter scale configuration
FSC9 :: Bit -- Filter scale configuration
FSC8 :: Bit -- Filter scale configuration
FSC7 :: Bit -- Filter scale configuration
FSC6 :: Bit -- Filter scale configuration
FSC5 :: Bit -- Filter scale configuration
FSC4 :: Bit -- Filter scale configuration
FSC3 :: Bit -- Filter scale configuration
FSC2 :: Bit -- Filter scale configuration
FSC1 :: Bit -- Filter scale configuration
FSC0 :: Bit -- Filter scale configuration
FFA1R 0x214 - filter FIFO assignment register
_ :: Bits 4 -- (Reserved)
FFA27 :: Bit -- Filter FIFO assignment for filter 27
FFA26 :: Bit -- Filter FIFO assignment for filter 26
FFA25 :: Bit -- Filter FIFO assignment for filter 25
FFA24 :: Bit -- Filter FIFO assignment for filter 24
FFA23 :: Bit -- Filter FIFO assignment for filter 23
FFA22 :: Bit -- Filter FIFO assignment for filter 22
FFA21 :: Bit -- Filter FIFO assignment for filter 21
FFA20 :: Bit -- Filter FIFO assignment for filter 20
FFA19 :: Bit -- Filter FIFO assignment for filter 19
FFA18 :: Bit -- Filter FIFO assignment for filter 18
FFA17 :: Bit -- Filter FIFO assignment for filter 17
FFA16 :: Bit -- Filter FIFO assignment for filter 16
FFA15 :: Bit -- Filter FIFO assignment for filter 15
FFA14 :: Bit -- Filter FIFO assignment for filter 14
FFA13 :: Bit -- Filter FIFO assignment for filter 13
FFA12 :: Bit -- Filter FIFO assignment for filter 12
FFA11 :: Bit -- Filter FIFO assignment for filter 11
FFA10 :: Bit -- Filter FIFO assignment for filter 10
FFA9 :: Bit -- Filter FIFO assignment for filter 9
FFA8 :: Bit -- Filter FIFO assignment for filter 8
FFA7 :: Bit -- Filter FIFO assignment for filter 7
FFA6 :: Bit -- Filter FIFO assignment for filter 6
FFA5 :: Bit -- Filter FIFO assignment for filter 5
FFA4 :: Bit -- Filter FIFO assignment for filter 4
FFA3 :: Bit -- Filter FIFO assignment for filter 3
FFA2 :: Bit -- Filter FIFO assignment for filter 2
FFA1 :: Bit -- Filter FIFO assignment for filter 1
FFA0 :: Bit -- Filter FIFO assignment for filter 0
FA1R 0x21c - filter activation register
_ :: Bits 4 -- (Reserved)
FACT27 :: Bit -- Filter active
FACT26 :: Bit -- Filter active
FACT25 :: Bit -- Filter active
FACT24 :: Bit -- Filter active
FACT23 :: Bit -- Filter active
FACT22 :: Bit -- Filter active
FACT21 :: Bit -- Filter active
FACT20 :: Bit -- Filter active
FACT19 :: Bit -- Filter active
FACT18 :: Bit -- Filter active
FACT17 :: Bit -- Filter active
FACT16 :: Bit -- Filter active
FACT15 :: Bit -- Filter active
FACT14 :: Bit -- Filter active
FACT13 :: Bit -- Filter active
FACT12 :: Bit -- Filter active
FACT11 :: Bit -- Filter active
FACT10 :: Bit -- Filter active
FACT9 :: Bit -- Filter active
FACT8 :: Bit -- Filter active
FACT7 :: Bit -- Filter active
FACT6 :: Bit -- Filter active
FACT5 :: Bit -- Filter active
FACT4 :: Bit -- Filter active
FACT3 :: Bit -- Filter active
FACT2 :: Bit -- Filter active
FACT1 :: Bit -- Filter active
FACT0 :: Bit -- Filter active
FR1 0x240 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x244 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x248 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x24c - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x250 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x254 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x258 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x25c - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x260 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x264 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x268 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x26c - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x270 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x274 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x278 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x27c - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x280 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x284 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x288 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x28c - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x290 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x294 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x298 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x29c - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x2a0 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x2a4 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x2a8 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x2ac - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x2b0 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x2b4 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x2b8 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x2bc - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x2c0 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x2c4 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x2c8 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x2cc - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x2d0 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x2d4 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x2d8 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x2dc - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x2e0 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x2e4 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x2e8 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x2ec - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x2f0 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x2f4 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x2f8 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x2fc - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x300 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x304 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x308 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x30c - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x310 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x314 - Filter bank x register 2
FB :: Bits 32 -- Filter bits
FR1 0x318 - Filter bank x register 1
FB :: Bits 32 -- Filter bits
FR2 0x31c - Filter bank x register 2
FB :: Bits 32 -- Filter bits
CAN2 0x40006800
Derived from CAN1
PWR 0x40007000 Power control
CR 0x0 - power control register
_ :: Bits 22 -- (Reserved)
FPDS :: Bit -- Flash power down in Stop mode
DBP :: Bit -- Disable backup domain write protection
PLS :: Bits 3 -- PVD level selection
PVDE :: Bit -- Power voltage detector enable
CSBF :: Bit -- Clear standby flag
CWUF :: Bit -- Clear wakeup flag
PDDS :: Bit -- Power down deepsleep
LPDS :: Bit -- Low-power deep sleep
CSR 0x4 - power control/status register
_ :: Bits 17 -- (Reserved)
VOSRDY :: Bit -- Regulator voltage scaling output selection ready bit
_ :: Bits 4 -- (Reserved)
BRE :: Bit -- Backup regulator enable
EWUP :: Bit -- Enable WKUP pin
_ :: Bits 4 -- (Reserved)
BRR :: Bit -- Backup regulator ready
PVDO :: Bit -- PVD output
SBF :: Bit -- Standby flag
WUF :: Bit -- Wakeup flag
DAC 0x40007400 Digital-to-analog converter
CR 0x0 - control register
_ :: Bits 2 -- (Reserved)
DMAUDRIE2 :: Bit -- DAC channel2 DMA underrun interrupt enable
DMAEN2 :: Bit -- DAC channel2 DMA enable
MAMP2 :: Bits 4 -- DAC channel2 mask/amplitude selector
WAVE2 :: Bits 2 -- DAC channel2 noise/triangle wave generation enable
TSEL2 :: Bits 3 -- DAC channel2 trigger selection
TEN2 :: Bit -- DAC channel2 trigger enable
BOFF2 :: Bit -- DAC channel2 output buffer disable
EN2 :: Bit -- DAC channel2 enable
_ :: Bits 2 -- (Reserved)
DMAUDRIE1 :: Bit -- DAC channel1 DMA Underrun Interrupt enable
DMAEN1 :: Bit -- DAC channel1 DMA enable
MAMP1 :: Bits 4 -- DAC channel1 mask/amplitude selector
WAVE1 :: Bits 2 -- DAC channel1 noise/triangle wave generation enable
TSEL1 :: Bits 3 -- DAC channel1 trigger selection
TEN1 :: Bit -- DAC channel1 trigger enable
BOFF1 :: Bit -- DAC channel1 output buffer disable
EN1 :: Bit -- DAC channel1 enable
SWTRIGR 0x4 - software trigger register
_ :: Bits 30 -- (Reserved)
SWTRIG2 :: Bit -- DAC channel2 software trigger
SWTRIG1 :: Bit -- DAC channel1 software trigger
DHR12R1 0x8 - channel1 12-bit right-aligned data holding register
_ :: Bits 20 -- (Reserved)
DACC1DHR :: Bits 12 -- DAC channel1 12-bit right-aligned data
DHR12L1 0xc - channel1 12-bit left aligned data holding register
_ :: Bits 16 -- (Reserved)
DACC1DHR :: Bits 12 -- DAC channel1 12-bit left-aligned data
_ :: Bits 4 -- (Reserved)
DHR8R1 0x10 - channel1 8-bit right aligned data holding register
_ :: Bits 24 -- (Reserved)
DACC1DHR :: Bits 8 -- DAC channel1 8-bit right-aligned data
DHR12R2 0x14 - channel2 12-bit right aligned data holding register
_ :: Bits 20 -- (Reserved)
DACC2DHR :: Bits 12 -- DAC channel2 12-bit right-aligned data
DHR12L2 0x18 - channel2 12-bit left aligned data holding register
_ :: Bits 16 -- (Reserved)
DACC2DHR :: Bits 12 -- DAC channel2 12-bit left-aligned data
_ :: Bits 4 -- (Reserved)
DHR8R2 0x1c - channel2 8-bit right-aligned data holding register
_ :: Bits 24 -- (Reserved)
DACC2DHR :: Bits 8 -- DAC channel2 8-bit right-aligned data
DHR12RD 0x20 - Dual DAC 12-bit right-aligned data holding register
_ :: Bits 4 -- (Reserved)
DACC2DHR :: Bits 12 -- DAC channel2 12-bit right-aligned data
_ :: Bits 4 -- (Reserved)
DACC1DHR :: Bits 12 -- DAC channel1 12-bit right-aligned data
DHR12LD 0x24 - DUAL DAC 12-bit left aligned data holding register
DACC2DHR :: Bits 12 -- DAC channel2 12-bit left-aligned data
_ :: Bits 4 -- (Reserved)
DACC1DHR :: Bits 12 -- DAC channel1 12-bit left-aligned data
_ :: Bits 4 -- (Reserved)
DHR8RD 0x28 - DUAL DAC 8-bit right aligned data holding register
_ :: Bits 16 -- (Reserved)
DACC2DHR :: Bits 8 -- DAC channel2 8-bit right-aligned data
DACC1DHR :: Bits 8 -- DAC channel1 8-bit right-aligned data
DOR1 0x2c - channel1 data output register
_ :: Bits 20 -- (Reserved)
DACC1DOR :: Bits 12 -- DAC channel1 data output
DOR2 0x30 - channel2 data output register
_ :: Bits 20 -- (Reserved)
DACC2DOR :: Bits 12 -- DAC channel2 data output
SR 0x34 - status register
_ :: Bits 2 -- (Reserved)
DMAUDR2 :: Bit -- DAC channel2 DMA underrun flag
_ :: Bits 15 -- (Reserved)
DMAUDR1 :: Bit -- DAC channel1 DMA underrun flag
_ :: Bits 13 -- (Reserved)
TIM1 0x40010000 Advanced-timers
CR1 0x0 - control register 1
_ :: Bits 22 -- (Reserved)
CKD :: Bits 2 -- Clock division
ARPE :: Bit -- Auto-reload preload enable
CMS :: Bits 2 -- Center-aligned mode selection
DIR :: Bit -- Direction
OPM :: Bit -- One-pulse mode
URS :: Bit -- Update request source
UDIS :: Bit -- Update disable
CEN :: Bit -- Counter enable
CR2 0x4 - control register 2
_ :: Bits 17 -- (Reserved)
OIS4 :: Bit -- Output Idle state 4
OIS3N :: Bit -- Output Idle state 3
OIS3 :: Bit -- Output Idle state 3
OIS2N :: Bit -- Output Idle state 2
OIS2 :: Bit -- Output Idle state 2
OIS1N :: Bit -- Output Idle state 1
OIS1 :: Bit -- Output Idle state 1
TI1S :: Bit -- TI1 selection
MMS :: Bits 3 -- Master mode selection
CCDS :: Bit -- Capture/compare DMA selection
CCUS :: Bit -- Capture/compare control update selection
_ :: Bit -- (Reserved)
CCPC :: Bit -- Capture/compare preloaded control
SMCR 0x8 - slave mode control register
_ :: Bits 16 -- (Reserved)
ETP :: Bit -- External trigger polarity
ECE :: Bit -- External clock enable
ETPS :: Bits 2 -- External trigger prescaler
ETF :: Bits 4 -- External trigger filter
MSM :: Bit -- Master/Slave mode
TS :: Bits 3 -- Trigger selection
_ :: Bit -- (Reserved)
SMS :: Bits 3 -- Slave mode selection
DIER 0xc - DMA/Interrupt enable register
_ :: Bits 17 -- (Reserved)
TDE :: Bit -- Trigger DMA request enable
COMDE :: Bit -- COM DMA request enable
CC4DE :: Bit -- Capture/Compare 4 DMA request enable
CC3DE :: Bit -- Capture/Compare 3 DMA request enable
CC2DE :: Bit -- Capture/Compare 2 DMA request enable
CC1DE :: Bit -- Capture/Compare 1 DMA request enable
UDE :: Bit -- Update DMA request enable
BIE :: Bit -- Break interrupt enable
TIE :: Bit -- Trigger interrupt enable
COMIE :: Bit -- COM interrupt enable
CC4IE :: Bit -- Capture/Compare 4 interrupt enable
CC3IE :: Bit -- Capture/Compare 3 interrupt enable
CC2IE :: Bit -- Capture/Compare 2 interrupt enable
CC1IE :: Bit -- Capture/Compare 1 interrupt enable
UIE :: Bit -- Update interrupt enable
SR 0x10 - status register
_ :: Bits 19 -- (Reserved)
CC4OF :: Bit -- Capture/Compare 4 overcapture flag
CC3OF :: Bit -- Capture/Compare 3 overcapture flag
CC2OF :: Bit -- Capture/compare 2 overcapture flag
CC1OF :: Bit -- Capture/Compare 1 overcapture flag
_ :: Bit -- (Reserved)
BIF :: Bit -- Break interrupt flag
TIF :: Bit -- Trigger interrupt flag
COMIF :: Bit -- COM interrupt flag
CC4IF :: Bit -- Capture/Compare 4 interrupt flag
CC3IF :: Bit -- Capture/Compare 3 interrupt flag
CC2IF :: Bit -- Capture/Compare 2 interrupt flag
CC1IF :: Bit -- Capture/compare 1 interrupt flag
UIF :: Bit -- Update interrupt flag
EGR 0x14 - event generation register
_ :: Bits 24 -- (Reserved)
BG :: Bit -- Break generation
TG :: Bit -- Trigger generation
COMG :: Bit -- Capture/Compare control update generation
CC4G :: Bit -- Capture/compare 4 generation
CC3G :: Bit -- Capture/compare 3 generation
CC2G :: Bit -- Capture/compare 2 generation
CC1G :: Bit -- Capture/compare 1 generation
UG :: Bit -- Update generation
CCMR1_Output 0x18 - capture/compare mode register 1 (output mode)
_ :: Bits 16 -- (Reserved)
OC2CE :: Bit -- Output Compare 2 clear enable
OC2M :: Bits 3 -- Output Compare 2 mode
OC2PE :: Bit -- Output Compare 2 preload enable
OC2FE :: Bit -- Output Compare 2 fast enable
CC2S :: Bits 2 -- Capture/Compare 2 selection
OC1CE :: Bit -- Output Compare 1 clear enable
OC1M :: Bits 3 -- Output Compare 1 mode
OC1PE :: Bit -- Output Compare 1 preload enable
OC1FE :: Bit -- Output Compare 1 fast enable
CC1S :: Bits 2 -- Capture/Compare 1 selection
CCMR1_Input 0x18 - capture/compare mode register 1 (input mode)
_ :: Bits 16 -- (Reserved)
IC2F :: Bits 4 -- Input capture 2 filter
IC2PSC :: Bits 2 -- Input capture 2 prescaler
CC2S :: Bits 2 -- Capture/Compare 2 selection
IC1F :: Bits 4 -- Input capture 1 filter
IC1PSC :: Bits 2 -- Input capture 1 prescaler
CC1S :: Bits 2 -- Capture/Compare 1 selection
CCMR2_Output 0x1c - capture/compare mode register 2 (output mode)
_ :: Bits 16 -- (Reserved)
OC4CE :: Bit -- Output compare 4 clear enable
OC4M :: Bits 3 -- Output compare 4 mode
OC4PE :: Bit -- Output compare 4 preload enable
OC4FE :: Bit -- Output compare 4 fast enable
CC4S :: Bits 2 -- Capture/Compare 4 selection
OC3CE :: Bit -- Output compare 3 clear enable
OC3M :: Bits 3 -- Output compare 3 mode
OC3PE :: Bit -- Output compare 3 preload enable
OC3FE :: Bit -- Output compare 3 fast enable
CC3S :: Bits 2 -- Capture/Compare 3 selection
CCMR2_Input 0x1c - capture/compare mode register 2 (input mode)
_ :: Bits 16 -- (Reserved)
IC4F :: Bits 4 -- Input capture 4 filter
IC4PSC :: Bits 2 -- Input capture 4 prescaler
CC4S :: Bits 2 -- Capture/Compare 4 selection
IC3F :: Bits 4 -- Input capture 3 filter
IC3PSC :: Bits 2 -- Input capture 3 prescaler
CC3S :: Bits 2 -- Capture/compare 3 selection
CCER 0x20 - capture/compare enable register
_ :: Bits 18 -- (Reserved)
CC4P :: Bit -- Capture/Compare 3 output Polarity
CC4E :: Bit -- Capture/Compare 4 output enable
CC3NP :: Bit -- Capture/Compare 3 output Polarity
CC3NE :: Bit -- Capture/Compare 3 complementary output enable
CC3P :: Bit -- Capture/Compare 3 output Polarity
CC3E :: Bit -- Capture/Compare 3 output enable
CC2NP :: Bit -- Capture/Compare 2 output Polarity
CC2NE :: Bit -- Capture/Compare 2 complementary output enable
CC2P :: Bit -- Capture/Compare 2 output Polarity
CC2E :: Bit -- Capture/Compare 2 output enable
CC1NP :: Bit -- Capture/Compare 1 output Polarity
CC1NE :: Bit -- Capture/Compare 1 complementary output enable
CC1P :: Bit -- Capture/Compare 1 output Polarity
CC1E :: Bit -- Capture/Compare 1 output enable
CNT 0x24 - counter
_ :: Bits 16 -- (Reserved)
CNT :: Bits 16 -- counter value
PSC 0x28 - prescaler
_ :: Bits 16 -- (Reserved)
PSC :: Bits 16 -- Prescaler value
ARR 0x2c - auto-reload register
_ :: Bits 16 -- (Reserved)
ARR :: Bits 16 -- Auto-reload value
RCR 0x30 - repetition counter register
_ :: Bits 24 -- (Reserved)
REP :: Bits 8 -- Repetition counter value
CCR1 0x34 - capture/compare register
_ :: Bits 16 -- (Reserved)
CCR :: Bits 16 -- Capture/Compare value
CCR2 0x38 - capture/compare register
_ :: Bits 16 -- (Reserved)
CCR :: Bits 16 -- Capture/Compare value
CCR3 0x3c - capture/compare register
_ :: Bits 16 -- (Reserved)
CCR :: Bits 16 -- Capture/Compare value
CCR4 0x40 - capture/compare register
_ :: Bits 16 -- (Reserved)
CCR :: Bits 16 -- Capture/Compare value
BDTR 0x44 - break and dead-time register
_ :: Bits 16 -- (Reserved)
MOE :: Bit -- Main output enable
AOE :: Bit -- Automatic output enable
BKP :: Bit -- Break polarity
BKE :: Bit -- Break enable
OSSR :: Bit -- Off-state selection for Run mode
OSSI :: Bit -- Off-state selection for Idle mode
LOCK :: Bits 2 -- Lock configuration
DTG :: Bits 8 -- Dead-time generator setup
DCR 0x48 - DMA control register
_ :: Bits 19 -- (Reserved)
DBL :: Bits 5 -- DMA burst length
_ :: Bits 3 -- (Reserved)
DBA :: Bits 5 -- DMA base address
DMAR 0x4c - DMA address for full transfer
_ :: Bits 16 -- (Reserved)
DMAB :: Bits 16 -- DMA register for burst accesses
TIM8 0x40010400
Derived from TIM1
USART1 0x40011000 Universal synchronous asynchronous receiver transmitter
SR 0x0 - Status register
_ :: Bits 22 -- (Reserved)
CTS :: Bit -- CTS flag
LBD :: Bit -- LIN break detection flag
TXE :: Bit -- Transmit data register empty
TC :: Bit -- Transmission complete
RXNE :: Bit -- Read data register not empty
IDLE :: Bit -- IDLE line detected
ORE :: Bit -- Overrun error
NF :: Bit -- Noise detected flag
FE :: Bit -- Framing error
PE :: Bit -- Parity error
DR 0x4 - Data register
_ :: Bits 23 -- (Reserved)
DR :: Bits 9 -- Data value
BRR 0x8 - Baud rate register
_ :: Bits 16 -- (Reserved)
DIV_Mantissa :: Bits 12 -- mantissa of USARTDIV
DIV_Fraction :: Bits 4 -- fraction of USARTDIV
CR1 0xc - Control register 1
_ :: Bits 16 -- (Reserved)
OVER8 :: Bit -- Oversampling mode
_ :: Bit -- (Reserved)
UE :: Bit -- USART enable
M :: Bit -- Word length
WAKE :: Bit -- Wakeup method
PCE :: Bit -- Parity control enable
PS :: Bit -- Parity selection
PEIE :: Bit -- PE interrupt enable
TXEIE :: Bit -- TXE interrupt enable
TCIE :: Bit -- Transmission complete interrupt enable
RXNEIE :: Bit -- RXNE interrupt enable
IDLEIE :: Bit -- IDLE interrupt enable
TE :: Bit -- Transmitter enable
RE :: Bit -- Receiver enable
RWU :: Bit -- Receiver wakeup
SBK :: Bit -- Send break
CR2 0x10 - Control register 2
_ :: Bits 17 -- (Reserved)
LINEN :: Bit -- LIN mode enable
STOP :: Bits 2 -- STOP bits
CLKEN :: Bit -- Clock enable
CPOL :: Bit -- Clock polarity
CPHA :: Bit -- Clock phase
LBCL :: Bit -- Last bit clock pulse
_ :: Bit -- (Reserved)
LBDIE :: Bit -- LIN break detection interrupt enable
LBDL :: Bit -- lin break detection length
_ :: Bit -- (Reserved)
ADD :: Bits 4 -- Address of the USART node
CR3 0x14 - Control register 3
_ :: Bits 20 -- (Reserved)
ONEBIT :: Bit -- One sample bit method enable
CTSIE :: Bit -- CTS interrupt enable
CTSE :: Bit -- CTS enable
RTSE :: Bit -- RTS enable
DMAT :: Bit -- DMA enable transmitter
DMAR :: Bit -- DMA enable receiver
SCEN :: Bit -- Smartcard mode enable
NACK :: Bit -- Smartcard NACK enable
HDSEL :: Bit -- Half-duplex selection
IRLP :: Bit -- IrDA low-power
IREN :: Bit -- IrDA mode enable
EIE :: Bit -- Error interrupt enable
GTPR 0x18 - Guard time and prescaler register
_ :: Bits 16 -- (Reserved)
GT :: Bits 8 -- Guard time value
PSC :: Bits 8 -- Prescaler value
USART6 0x40011400
Derived from USART1
ADC1 0x40012000 Analog-to-digital converter
SR 0x0 - status register
_ :: Bits 26 -- (Reserved)
OVR :: Bit -- Overrun
STRT :: Bit -- Regular channel start flag
JSTRT :: Bit -- Injected channel start flag
JEOC :: Bit -- Injected channel end of conversion
EOC :: Bit -- Regular channel end of conversion
AWD :: Bit -- Analog watchdog flag
CR1 0x4 - control register 1
_ :: Bits 5 -- (Reserved)
OVRIE :: Bit -- Overrun interrupt enable
RES :: Bits 2 -- Resolution
AWDEN :: Bit -- Analog watchdog enable on regular channels
JAWDEN :: Bit -- Analog watchdog enable on injected channels
_ :: Bits 6 -- (Reserved)
DISCNUM :: Bits 3 -- Discontinuous mode channel count
JDISCEN :: Bit -- Discontinuous mode on injected channels
DISCEN :: Bit -- Discontinuous mode on regular channels
JAUTO :: Bit -- Automatic injected group conversion
AWDSGL :: Bit -- Enable the watchdog on a single channel in scan mode
SCAN :: Bit -- Scan mode
JEOCIE :: Bit -- Interrupt enable for injected channels
AWDIE :: Bit -- Analog watchdog interrupt enable
EOCIE :: Bit -- Interrupt enable for EOC
AWDCH :: Bits 5 -- Analog watchdog channel select bits
CR2 0x8 - control register 2
_ :: Bit -- (Reserved)
SWSTART :: Bit -- Start conversion of regular channels
EXTEN :: Bits 2 -- External trigger enable for regular channels
EXTSEL :: Bits 4 -- External event select for regular group
_ :: Bit -- (Reserved)
JSWSTART :: Bit -- Start conversion of injected channels
JEXTEN :: Bits 2 -- External trigger enable for injected channels
JEXTSEL :: Bits 4 -- External event select for injected group
_ :: Bits 4 -- (Reserved)
ALIGN :: Bit -- Data alignment
EOCS :: Bit -- End of conversion selection
DDS :: Bit -- DMA disable selection (for single ADC mode)
DMA :: Bit -- Direct memory access mode (for single ADC mode)
_ :: Bits 6 -- (Reserved)
CONT :: Bit -- Continuous conversion
ADON :: Bit -- A/D Converter ON / OFF
SMPR1 0xc - sample time register 1
_ :: Bits 5 -- (Reserved)
SMP18 :: Bits 3 -- Channel 18 sampling time selection
SMP17 :: Bits 3 -- Channel 17 sampling time selection
SMP16 :: Bits 3 -- Channel 16 sampling time selection
SMP15 :: Bits 3 -- Channel 15 sampling time selection
SMP14 :: Bits 3 -- Channel 14 sampling time selection
SMP13 :: Bits 3 -- Channel 13 sampling time selection
SMP12 :: Bits 3 -- Channel 12 sampling time selection
SMP11 :: Bits 3 -- Channel 11 sampling time selection
SMP10 :: Bits 3 -- Channel 10 sampling time selection
SMPR2 0x10 - sample time register 2
_ :: Bits 2 -- (Reserved)
SMP9 :: Bits 3 -- Channel 9 sampling time selection
SMP8 :: Bits 3 -- Channel 8 sampling time selection
SMP7 :: Bits 3 -- Channel 7 sampling time selection
SMP6 :: Bits 3 -- Channel 6 sampling time selection
SMP5 :: Bits 3 -- Channel 5 sampling time selection
SMP4 :: Bits 3 -- Channel 4 sampling time selection
SMP3 :: Bits 3 -- Channel 3 sampling time selection
SMP2 :: Bits 3 -- Channel 2 sampling time selection
SMP1 :: Bits 3 -- Channel 1 sampling time selection
SMP0 :: Bits 3 -- Channel 0 sampling time selection
JOFR1 0x14 - injected channel data offset register x
_ :: Bits 20 -- (Reserved)
JOFFSET :: Bits 12 -- Data offset for injected channel x
JOFR2 0x18 - injected channel data offset register x
_ :: Bits 20 -- (Reserved)
JOFFSET :: Bits 12 -- Data offset for injected channel x
JOFR3 0x1c - injected channel data offset register x
_ :: Bits 20 -- (Reserved)
JOFFSET :: Bits 12 -- Data offset for injected channel x
JOFR4 0x20 - injected channel data offset register x
_ :: Bits 20 -- (Reserved)
JOFFSET :: Bits 12 -- Data offset for injected channel x
HTR 0x24 - watchdog higher threshold register
_ :: Bits 20 -- (Reserved)
HT :: Bits 12 -- Analog watchdog higher threshold
LTR 0x28 - watchdog lower threshold register
_ :: Bits 20 -- (Reserved)
LT :: Bits 12 -- Analog watchdog lower threshold
SQR1 0x2c - regular sequence register 1
_ :: Bits 8 -- (Reserved)
L :: Bits 4 -- Regular channel sequence length
SQ16 :: Bits 5 -- 16th conversion in regular sequence
SQ15 :: Bits 5 -- 15th conversion in regular sequence
SQ14 :: Bits 5 -- 14th conversion in regular sequence
SQ13 :: Bits 5 -- 13th conversion in regular sequence
SQR2 0x30 - regular sequence register 2
_ :: Bits 2 -- (Reserved)
SQ12 :: Bits 5 -- 12th conversion in regular sequence
SQ11 :: Bits 5 -- 11th conversion in regular sequence
SQ10 :: Bits 5 -- 10th conversion in regular sequence
SQ9 :: Bits 5 -- 9th conversion in regular sequence
SQ8 :: Bits 5 -- 8th conversion in regular sequence
SQ7 :: Bits 5 -- 7th conversion in regular sequence
SQR3 0x34 - regular sequence register 3
_ :: Bits 2 -- (Reserved)
SQ6 :: Bits 5 -- 6th conversion in regular sequence
SQ5 :: Bits 5 -- 5th conversion in regular sequence
SQ4 :: Bits 5 -- 4th conversion in regular sequence
SQ3 :: Bits 5 -- 3rd conversion in regular sequence
SQ2 :: Bits 5 -- 2nd conversion in regular sequence
SQ1 :: Bits 5 -- 1st conversion in regular sequence
JSQR 0x38 - injected sequence register
_ :: Bits 10 -- (Reserved)
JL :: Bits 2 -- Injected sequence length
JSQ4 :: Bits 5 -- 4th conversion in injected sequence
JSQ3 :: Bits 5 -- 3rd conversion in injected sequence
JSQ2 :: Bits 5 -- 2nd conversion in injected sequence
JSQ1 :: Bits 5 -- 1st conversion in injected sequence
JDR1 0x3c - injected data register x
_ :: Bits 16 -- (Reserved)
JDATA :: Bits 16 -- Injected data
JDR2 0x40 - injected data register x
_ :: Bits 16 -- (Reserved)
JDATA :: Bits 16 -- Injected data
JDR3 0x44 - injected data register x
_ :: Bits 16 -- (Reserved)
JDATA :: Bits 16 -- Injected data
JDR4 0x48 - injected data register x
_ :: Bits 16 -- (Reserved)
JDATA :: Bits 16 -- Injected data
DR 0x4c - regular data register
_ :: Bits 16 -- (Reserved)
DATA :: Bits 16 -- Regular data
ADC2 0x40012100
Derived from ADC1
ADC3 0x40012200
Derived from ADC1
ADC_Common 0x40012300 Common ADC registers
CSR 0x0 - ADC Common status register
_ :: Bits 10 -- (Reserved)
OVR3 :: Bit -- Overrun flag of ADC3
STRT3 :: Bit -- Regular channel Start flag of ADC 3
JSTRT3 :: Bit -- Injected channel Start flag of ADC 3
JEOC3 :: Bit -- Injected channel end of conversion of ADC 3
EOC3 :: Bit -- End of conversion of ADC 3
AWD3 :: Bit -- Analog watchdog flag of ADC 3
_ :: Bits 2 -- (Reserved)
OVR2 :: Bit -- Overrun flag of ADC 2
STRT2 :: Bit -- Regular channel Start flag of ADC 2
JSTRT2 :: Bit -- Injected channel Start flag of ADC 2
JEOC2 :: Bit -- Injected channel end of conversion of ADC 2
EOC2 :: Bit -- End of conversion of ADC 2
AWD2 :: Bit -- Analog watchdog flag of ADC 2
_ :: Bits 2 -- (Reserved)
OVR1 :: Bit -- Overrun flag of ADC 1
STRT1 :: Bit -- Regular channel Start flag of ADC 1
JSTRT1 :: Bit -- Injected channel Start flag of ADC 1
JEOC1 :: Bit -- Injected channel end of conversion of ADC 1
EOC1 :: Bit -- End of conversion of ADC 1
AWD1 :: Bit -- Analog watchdog flag of ADC 1
CCR 0x4 - ADC common control register
_ :: Bits 8 -- (Reserved)
TSVREFE :: Bit -- Temperature sensor and VREFINT enable
VBATE :: Bit -- VBAT enable
_ :: Bits 4 -- (Reserved)
ADCPRE :: Bits 2 -- ADC prescaler
DMA :: Bits 2 -- Direct memory access mode for multi ADC mode
DDS :: Bit -- DMA disable selection for multi-ADC mode
_ :: Bit -- (Reserved)
DELAY :: Bits 4 -- Delay between 2 sampling phases
_ :: Bits 3 -- (Reserved)
MULTI :: Bits 5 -- Multi ADC mode selection
CDR 0x8 - ADC common regular data register for dual and triple modes
DATA2 :: Bits 16 -- 2nd data item of a pair of regular conversions
DATA1 :: Bits 16 -- 1st data item of a pair of regular conversions
SDIO 0x40012c00 Secure digital input/output interface
POWER 0x0 - power control register
_ :: Bits 30 -- (Reserved)
PWRCTRL :: Bits 2 -- PWRCTRL
CLKCR 0x4 - SDI clock control register
_ :: Bits 17 -- (Reserved)
HWFC_EN :: Bit -- HW Flow Control enable
NEGEDGE :: Bit -- SDIO_CK dephasing selection bit
WIDBUS :: Bits 2 -- Wide bus mode enable bit
BYPASS :: Bit -- Clock divider bypass enable bit
PWRSAV :: Bit -- Power saving configuration bit
CLKEN :: Bit -- Clock enable bit
CLKDIV :: Bits 8 -- Clock divide factor
ARG 0x8 - argument register
CMDARG :: Bits 32 -- Command argument
CMD 0xc - command register
_ :: Bits 17 -- (Reserved)
CE_ATACMD :: Bit -- CE-ATA command
nIEN :: Bit -- not Interrupt Enable
ENCMDcompl :: Bit -- Enable CMD completion
SDIOSuspend :: Bit -- SD I/O suspend command
CPSMEN :: Bit -- Command path state machine (CPSM) Enable bit
WAITPEND :: Bit -- CPSM Waits for ends of data transfer (CmdPend internal signal).
WAITINT :: Bit -- CPSM waits for interrupt request
WAITRESP :: Bits 2 -- Wait for response bits
CMDINDEX :: Bits 6 -- Command index
RESPCMD 0x10 - command response register
_ :: Bits 26 -- (Reserved)
RESPCMD :: Bits 6 -- Response command index
RESP1 0x14 - SDIO response 1 register
CARDSTATUS :: Bits 32 -- Status of a card, which is part of the received response
RESP2 0x18 - SDIO response 2 register
CARDSTATUS :: Bits 32 -- Status of a card, which is part of the received response
RESP3 0x1c - SDIO response 3 register
CARDSTATUS :: Bits 32 -- Status of a card, which is part of the received response
RESP4 0x20 - SDIO response 4 register
CARDSTATUS :: Bits 32 -- Status of a card, which is part of the received response
DTIMER 0x24 - data timer register
DATATIME :: Bits 32 -- Data timeout period
DLEN 0x28 - data length register
_ :: Bits 7 -- (Reserved)
DATALENGTH :: Bits 25 -- Data length value
DCTRL 0x2c - data control register
_ :: Bits 20 -- (Reserved)
SDIOEN :: Bit -- SD I/O enable functions
RWMOD :: Bit -- Read wait mode
RWSTOP :: Bit -- Read wait stop
RWSTART :: Bit -- Read wait start
DBLOCKSIZE :: Bits 4 -- Data block size
DMAEN :: Bit -- DMA enable bit
DTMODE :: Bit -- Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
DTDIR :: Bit -- Data transfer direction selection
DTEN :: Bit -- DTEN
DCOUNT 0x30 - data counter register
_ :: Bits 7 -- (Reserved)
DATACOUNT :: Bits 25 -- Data count value
STA 0x34 - status register
_ :: Bits 8 -- (Reserved)
CEATAEND :: Bit -- CE-ATA command completion signal received for CMD61
SDIOIT :: Bit -- SDIO interrupt received
RXDAVL :: Bit -- Data available in receive FIFO
TXDAVL :: Bit -- Data available in transmit FIFO
RXFIFOE :: Bit -- Receive FIFO empty
TXFIFOE :: Bit -- Transmit FIFO empty
RXFIFOF :: Bit -- Receive FIFO full
TXFIFOF :: Bit -- Transmit FIFO full
RXFIFOHF :: Bit -- Receive FIFO half full: there are at least 8 words in the FIFO
TXFIFOHE :: Bit -- Transmit FIFO half empty: at least 8 words can be written into the FIFO
RXACT :: Bit -- Data receive in progress
TXACT :: Bit -- Data transmit in progress
CMDACT :: Bit -- Command transfer in progress
DBCKEND :: Bit -- Data block sent/received (CRC check passed)
STBITERR :: Bit -- Start bit not detected on all data signals in wide bus mode
DATAEND :: Bit -- Data end (data counter, SDIDCOUNT, is zero)
CMDSENT :: Bit -- Command sent (no response required)
CMDREND :: Bit -- Command response received (CRC check passed)
RXOVERR :: Bit -- Received FIFO overrun error
TXUNDERR :: Bit -- Transmit FIFO underrun error
DTIMEOUT :: Bit -- Data timeout
CTIMEOUT :: Bit -- Command response timeout
DCRCFAIL :: Bit -- Data block sent/received (CRC check failed)
CCRCFAIL :: Bit -- Command response received (CRC check failed)
ICR 0x38 - interrupt clear register
_ :: Bits 8 -- (Reserved)
CEATAENDC :: Bit -- CEATAEND flag clear bit
SDIOITC :: Bit -- SDIOIT flag clear bit
_ :: Bits 11 -- (Reserved)
DBCKENDC :: Bit -- DBCKEND flag clear bit
STBITERRC :: Bit -- STBITERR flag clear bit
DATAENDC :: Bit -- DATAEND flag clear bit
CMDSENTC :: Bit -- CMDSENT flag clear bit
CMDRENDC :: Bit -- CMDREND flag clear bit
RXOVERRC :: Bit -- RXOVERR flag clear bit
TXUNDERRC :: Bit -- TXUNDERR flag clear bit
DTIMEOUTC :: Bit -- DTIMEOUT flag clear bit
CTIMEOUTC :: Bit -- CTIMEOUT flag clear bit
DCRCFAILC :: Bit -- DCRCFAIL flag clear bit
CCRCFAILC :: Bit -- CCRCFAIL flag clear bit
MASK 0x3c - mask register
_ :: Bits 8 -- (Reserved)
CEATAENDIE :: Bit -- CE-ATA command completion signal received interrupt enable
SDIOITIE :: Bit -- SDIO mode interrupt received interrupt enable
RXDAVLIE :: Bit -- Data available in Rx FIFO interrupt enable
TXDAVLIE :: Bit -- Data available in Tx FIFO interrupt enable
RXFIFOEIE :: Bit -- Rx FIFO empty interrupt enable
TXFIFOEIE :: Bit -- Tx FIFO empty interrupt enable
RXFIFOFIE :: Bit -- Rx FIFO full interrupt enable
TXFIFOFIE :: Bit -- Tx FIFO full interrupt enable
RXFIFOHFIE :: Bit -- Rx FIFO half full interrupt enable
TXFIFOHEIE :: Bit -- Tx FIFO half empty interrupt enable
RXACTIE :: Bit -- Data receive acting interrupt enable
TXACTIE :: Bit -- Data transmit acting interrupt enable
CMDACTIE :: Bit -- Command acting interrupt enable
DBCKENDIE :: Bit -- Data block end interrupt enable
STBITERRIE :: Bit -- Start bit error interrupt enable
DATAENDIE :: Bit -- Data end interrupt enable
CMDSENTIE :: Bit -- Command sent interrupt enable
CMDRENDIE :: Bit -- Command response received interrupt enable
RXOVERRIE :: Bit -- Rx FIFO overrun error interrupt enable
TXUNDERRIE :: Bit -- Tx FIFO underrun error interrupt enable
DTIMEOUTIE :: Bit -- Data timeout interrupt enable
CTIMEOUTIE :: Bit -- Command timeout interrupt enable
DCRCFAILIE :: Bit -- Data CRC fail interrupt enable
CCRCFAILIE :: Bit -- Command CRC fail interrupt enable
FIFOCNT 0x48 - FIFO counter register
_ :: Bits 8 -- (Reserved)
FIFOCOUNT :: Bits 24 -- Remaining number of words to be written to or read from the FIFO.
FIFO 0x80 - data FIFO register
FIFOData :: Bits 32 -- Receive and transmit FIFO data
SPI1 0x40013000 Serial peripheral interface
CR1 0x0 - control register 1
_ :: Bits 16 -- (Reserved)
BIDIMODE :: Bit -- Bidirectional data mode enable
BIDIOE :: Bit -- Output enable in bidirectional mode
CRCEN :: Bit -- Hardware CRC calculation enable
CRCNEXT :: Bit -- CRC transfer next
DFF :: Bit -- Data frame format
RXONLY :: Bit -- Receive only
SSM :: Bit -- Software slave management
SSI :: Bit -- Internal slave select
LSBFIRST :: Bit -- Frame format
SPE :: Bit -- SPI enable
BR :: Bits 3 -- Baud rate control
MSTR :: Bit -- Master selection
CPOL :: Bit -- Clock polarity
CPHA :: Bit -- Clock phase
CR2 0x4 - control register 2
_ :: Bits 24 -- (Reserved)
TXEIE :: Bit -- Tx buffer empty interrupt enable
RXNEIE :: Bit -- RX buffer not empty interrupt enable
ERRIE :: Bit -- Error interrupt enable
FRF :: Bit -- Frame format
_ :: Bit -- (Reserved)
SSOE :: Bit -- SS output enable
TXDMAEN :: Bit -- Tx buffer DMA enable
RXDMAEN :: Bit -- Rx buffer DMA enable
SR 0x8 - status register
_ :: Bits 23 -- (Reserved)
FRE :: Bit -- TI frame format error
BSY :: Bit -- Busy flag
OVR :: Bit -- Overrun flag
MODF :: Bit -- Mode fault
CRCERR :: Bit -- CRC error flag
UDR :: Bit -- Underrun flag
CHSIDE :: Bit -- Channel side
TXE :: Bit -- Transmit buffer empty
RXNE :: Bit -- Receive buffer not empty
DR 0xc - data register
_ :: Bits 16 -- (Reserved)
DR :: Bits 16 -- Data register
CRCPR 0x10 - CRC polynomial register
_ :: Bits 16 -- (Reserved)
CRCPOLY :: Bits 16 -- CRC polynomial register
RXCRCR 0x14 - RX CRC register
_ :: Bits 16 -- (Reserved)
RxCRC :: Bits 16 -- Rx CRC register
TXCRCR 0x18 - TX CRC register
_ :: Bits 16 -- (Reserved)
TxCRC :: Bits 16 -- Tx CRC register
I2SCFGR 0x1c - I2S configuration register
_ :: Bits 20 -- (Reserved)
I2SMOD :: Bit -- I2S mode selection
I2SE :: Bit -- I2S Enable
I2SCFG :: Bits 2 -- I2S configuration mode
PCMSYNC :: Bit -- PCM frame synchronization
_ :: Bit -- (Reserved)
I2SSTD :: Bits 2 -- I2S standard selection
CKPOL :: Bit -- Steady state clock polarity
DATLEN :: Bits 2 -- Data length to be transferred
CHLEN :: Bit -- Channel length (number of bits per audio channel)
I2SPR 0x20 - I2S prescaler register
_ :: Bits 22 -- (Reserved)
MCKOE :: Bit -- Master clock output enable
ODD :: Bit -- Odd factor for the prescaler
I2SDIV :: Bits 8 -- I2S Linear prescaler
SPI4 0x40013400
Derived from SPI1
SYSCFG 0x40013800 System configuration controller
MEMRM 0x0 - memory remap register
_ :: Bits 30 -- (Reserved)
MEM_MODE :: Bits 2 -- MEM_MODE
EXTICR1 0x8 - external interrupt configuration register 1
_ :: Bits 16 -- (Reserved)
EXTI3 :: Bits 4 -- EXTI x configuration (x = 0 to 3)
EXTI2 :: Bits 4 -- EXTI x configuration (x = 0 to 3)
EXTI1 :: Bits 4 -- EXTI x configuration (x = 0 to 3)
EXTI0 :: Bits 4 -- EXTI x configuration (x = 0 to 3)
EXTICR2 0xc - external interrupt configuration register 2
_ :: Bits 16 -- (Reserved)
EXTI7 :: Bits 4 -- EXTI x configuration (x = 4 to 7)
EXTI6 :: Bits 4 -- EXTI x configuration (x = 4 to 7)
EXTI5 :: Bits 4 -- EXTI x configuration (x = 4 to 7)
EXTI4 :: Bits 4 -- EXTI x configuration (x = 4 to 7)
EXTICR3 0x10 - external interrupt configuration register 3
_ :: Bits 16 -- (Reserved)
EXTI11 :: Bits 4 -- EXTI x configuration (x = 8 to 11)
EXTI10 :: Bits 4 -- EXTI10
EXTI9 :: Bits 4 -- EXTI x configuration (x = 8 to 11)
EXTI8 :: Bits 4 -- EXTI x configuration (x = 8 to 11)
EXTICR4 0x14 - external interrupt configuration register 4
_ :: Bits 16 -- (Reserved)
EXTI15 :: Bits 4 -- EXTI x configuration (x = 12 to 15)
EXTI14 :: Bits 4 -- EXTI x configuration (x = 12 to 15)
EXTI13 :: Bits 4 -- EXTI x configuration (x = 12 to 15)
EXTI12 :: Bits 4 -- EXTI x configuration (x = 12 to 15)
CMPCR 0x20 - Compensation cell control register
_ :: Bits 23 -- (Reserved)
READY :: Bit -- READY
_ :: Bits 7 -- (Reserved)
CMP_PD :: Bit -- Compensation cell power-down
EXTI 0x40013c00 External interrupt/event controller
IMR 0x0 - Interrupt mask register (EXTI_IMR)
_ :: Bits 9 -- (Reserved)
MR22 :: Bit -- Interrupt Mask on line 22
MR21 :: Bit -- Interrupt Mask on line 21
MR20 :: Bit -- Interrupt Mask on line 20
MR19 :: Bit -- Interrupt Mask on line 19
MR18 :: Bit -- Interrupt Mask on line 18
MR17 :: Bit -- Interrupt Mask on line 17
MR16 :: Bit -- Interrupt Mask on line 16
MR15 :: Bit -- Interrupt Mask on line 15
MR14 :: Bit -- Interrupt Mask on line 14
MR13 :: Bit -- Interrupt Mask on line 13
MR12 :: Bit -- Interrupt Mask on line 12
MR11 :: Bit -- Interrupt Mask on line 11
MR10 :: Bit -- Interrupt Mask on line 10
MR9 :: Bit -- Interrupt Mask on line 9
MR8 :: Bit -- Interrupt Mask on line 8
MR7 :: Bit -- Interrupt Mask on line 7
MR6 :: Bit -- Interrupt Mask on line 6
MR5 :: Bit -- Interrupt Mask on line 5
MR4 :: Bit -- Interrupt Mask on line 4
MR3 :: Bit -- Interrupt Mask on line 3
MR2 :: Bit -- Interrupt Mask on line 2
MR1 :: Bit -- Interrupt Mask on line 1
MR0 :: Bit -- Interrupt Mask on line 0
EMR 0x4 - Event mask register (EXTI_EMR)
_ :: Bits 9 -- (Reserved)
MR22 :: Bit -- Event Mask on line 22
MR21 :: Bit -- Event Mask on line 21
MR20 :: Bit -- Event Mask on line 20
MR19 :: Bit -- Event Mask on line 19
MR18 :: Bit -- Event Mask on line 18
MR17 :: Bit -- Event Mask on line 17
MR16 :: Bit -- Event Mask on line 16
MR15 :: Bit -- Event Mask on line 15
MR14 :: Bit -- Event Mask on line 14
MR13 :: Bit -- Event Mask on line 13
MR12 :: Bit -- Event Mask on line 12
MR11 :: Bit -- Event Mask on line 11
MR10 :: Bit -- Event Mask on line 10
MR9 :: Bit -- Event Mask on line 9
MR8 :: Bit -- Event Mask on line 8
MR7 :: Bit -- Event Mask on line 7
MR6 :: Bit -- Event Mask on line 6
MR5 :: Bit -- Event Mask on line 5
MR4 :: Bit -- Event Mask on line 4
MR3 :: Bit -- Event Mask on line 3
MR2 :: Bit -- Event Mask on line 2
MR1 :: Bit -- Event Mask on line 1
MR0 :: Bit -- Event Mask on line 0
RTSR 0x8 - Rising Trigger selection register (EXTI_RTSR)
_ :: Bits 9 -- (Reserved)
TR22 :: Bit -- Rising trigger event configuration of line 22
TR21 :: Bit -- Rising trigger event configuration of line 21
TR20 :: Bit -- Rising trigger event configuration of line 20
TR19 :: Bit -- Rising trigger event configuration of line 19
TR18 :: Bit -- Rising trigger event configuration of line 18
TR17 :: Bit -- Rising trigger event configuration of line 17
TR16 :: Bit -- Rising trigger event configuration of line 16
TR15 :: Bit -- Rising trigger event configuration of line 15
TR14 :: Bit -- Rising trigger event configuration of line 14
TR13 :: Bit -- Rising trigger event configuration of line 13
TR12 :: Bit -- Rising trigger event configuration of line 12
TR11 :: Bit -- Rising trigger event configuration of line 11
TR10 :: Bit -- Rising trigger event configuration of line 10
TR9 :: Bit -- Rising trigger event configuration of line 9
TR8 :: Bit -- Rising trigger event configuration of line 8
TR7 :: Bit -- Rising trigger event configuration of line 7
TR6 :: Bit -- Rising trigger event configuration of line 6
TR5 :: Bit -- Rising trigger event configuration of line 5
TR4 :: Bit -- Rising trigger event configuration of line 4
TR3 :: Bit -- Rising trigger event configuration of line 3
TR2 :: Bit -- Rising trigger event configuration of line 2
TR1 :: Bit -- Rising trigger event configuration of line 1
TR0 :: Bit -- Rising trigger event configuration of line 0
FTSR 0xc - Falling Trigger selection register (EXTI_FTSR)
_ :: Bits 9 -- (Reserved)
TR22 :: Bit -- Falling trigger event configuration of line 22
TR21 :: Bit -- Falling trigger event configuration of line 21
TR20 :: Bit -- Falling trigger event configuration of line 20
TR19 :: Bit -- Falling trigger event configuration of line 19
TR18 :: Bit -- Falling trigger event configuration of line 18
TR17 :: Bit -- Falling trigger event configuration of line 17
TR16 :: Bit -- Falling trigger event configuration of line 16
TR15 :: Bit -- Falling trigger event configuration of line 15
TR14 :: Bit -- Falling trigger event configuration of line 14
TR13 :: Bit -- Falling trigger event configuration of line 13
TR12 :: Bit -- Falling trigger event configuration of line 12
TR11 :: Bit -- Falling trigger event configuration of line 11
TR10 :: Bit -- Falling trigger event configuration of line 10
TR9 :: Bit -- Falling trigger event configuration of line 9
TR8 :: Bit -- Falling trigger event configuration of line 8
TR7 :: Bit -- Falling trigger event configuration of line 7
TR6 :: Bit -- Falling trigger event configuration of line 6
TR5 :: Bit -- Falling trigger event configuration of line 5
TR4 :: Bit -- Falling trigger event configuration of line 4
TR3 :: Bit -- Falling trigger event configuration of line 3
TR2 :: Bit -- Falling trigger event configuration of line 2
TR1 :: Bit -- Falling trigger event configuration of line 1
TR0 :: Bit -- Falling trigger event configuration of line 0
SWIER 0x10 - Software interrupt event register (EXTI_SWIER)
_ :: Bits 9 -- (Reserved)
SWIER22 :: Bit -- Software Interrupt on line 22
SWIER21 :: Bit -- Software Interrupt on line 21
SWIER20 :: Bit -- Software Interrupt on line 20
SWIER19 :: Bit -- Software Interrupt on line 19
SWIER18 :: Bit -- Software Interrupt on line 18
SWIER17 :: Bit -- Software Interrupt on line 17
SWIER16 :: Bit -- Software Interrupt on line 16
SWIER15 :: Bit -- Software Interrupt on line 15
SWIER14 :: Bit -- Software Interrupt on line 14
SWIER13 :: Bit -- Software Interrupt on line 13
SWIER12 :: Bit -- Software Interrupt on line 12
SWIER11 :: Bit -- Software Interrupt on line 11
SWIER10 :: Bit -- Software Interrupt on line 10
SWIER9 :: Bit -- Software Interrupt on line 9
SWIER8 :: Bit -- Software Interrupt on line 8
SWIER7 :: Bit -- Software Interrupt on line 7
SWIER6 :: Bit -- Software Interrupt on line 6
SWIER5 :: Bit -- Software Interrupt on line 5
SWIER4 :: Bit -- Software Interrupt on line 4
SWIER3 :: Bit -- Software Interrupt on line 3
SWIER2 :: Bit -- Software Interrupt on line 2
SWIER1 :: Bit -- Software Interrupt on line 1
SWIER0 :: Bit -- Software Interrupt on line 0
PR 0x14 - Pending register (EXTI_PR)
_ :: Bits 9 -- (Reserved)
PR22 :: Bit -- Pending bit 22
PR21 :: Bit -- Pending bit 21
PR20 :: Bit -- Pending bit 20
PR19 :: Bit -- Pending bit 19
PR18 :: Bit -- Pending bit 18
PR17 :: Bit -- Pending bit 17
PR16 :: Bit -- Pending bit 16
PR15 :: Bit -- Pending bit 15
PR14 :: Bit -- Pending bit 14
PR13 :: Bit -- Pending bit 13
PR12 :: Bit -- Pending bit 12
PR11 :: Bit -- Pending bit 11
PR10 :: Bit -- Pending bit 10
PR9 :: Bit -- Pending bit 9
PR8 :: Bit -- Pending bit 8
PR7 :: Bit -- Pending bit 7
PR6 :: Bit -- Pending bit 6
PR5 :: Bit -- Pending bit 5
PR4 :: Bit -- Pending bit 4
PR3 :: Bit -- Pending bit 3
PR2 :: Bit -- Pending bit 2
PR1 :: Bit -- Pending bit 1
PR0 :: Bit -- Pending bit 0
TIM9 0x40014000 General purpose timers
CR1 0x0 - control register 1
_ :: Bits 22 -- (Reserved)
CKD :: Bits 2 -- Clock division
ARPE :: Bit -- Auto-reload preload enable
_ :: Bits 3 -- (Reserved)
OPM :: Bit -- One-pulse mode
URS :: Bit -- Update request source
UDIS :: Bit -- Update disable
CEN :: Bit -- Counter enable
CR2 0x4 - control register 2
_ :: Bits 25 -- (Reserved)
MMS :: Bits 3 -- Master mode selection
_ :: Bits 4 -- (Reserved)
SMCR 0x8 - slave mode control register
_ :: Bits 24 -- (Reserved)
MSM :: Bit -- Master/Slave mode
TS :: Bits 3 -- Trigger selection
_ :: Bit -- (Reserved)
SMS :: Bits 3 -- Slave mode selection
DIER 0xc - DMA/Interrupt enable register
_ :: Bits 25 -- (Reserved)
TIE :: Bit -- Trigger interrupt enable
_ :: Bits 3 -- (Reserved)
CC2IE :: Bit -- Capture/Compare 2 interrupt enable
CC1IE :: Bit -- Capture/Compare 1 interrupt enable
UIE :: Bit -- Update interrupt enable
SR 0x10 - status register
_ :: Bits 21 -- (Reserved)
CC2OF :: Bit -- Capture/compare 2 overcapture flag
CC1OF :: Bit -- Capture/Compare 1 overcapture flag
_ :: Bits 2 -- (Reserved)
TIF :: Bit -- Trigger interrupt flag
_ :: Bits 3 -- (Reserved)
CC2IF :: Bit -- Capture/Compare 2 interrupt flag
CC1IF :: Bit -- Capture/compare 1 interrupt flag
UIF :: Bit -- Update interrupt flag
EGR 0x14 - event generation register
_ :: Bits 25 -- (Reserved)
TG :: Bit -- Trigger generation
_ :: Bits 3 -- (Reserved)
CC2G :: Bit -- Capture/compare 2 generation
CC1G :: Bit -- Capture/compare 1 generation
UG :: Bit -- Update generation
CCMR1_Output 0x18 - capture/compare mode register 1 (output mode)
_ :: Bits 17 -- (Reserved)
OC2M :: Bits 3 -- Output Compare 2 mode
OC2PE :: Bit -- Output Compare 2 preload enable
OC2FE :: Bit -- Output Compare 2 fast enable
CC2S :: Bits 2 -- Capture/Compare 2 selection
_ :: Bit -- (Reserved)
OC1M :: Bits 3 -- Output Compare 1 mode
OC1PE :: Bit -- Output Compare 1 preload enable
OC1FE :: Bit -- Output Compare 1 fast enable
CC1S :: Bits 2 -- Capture/Compare 1 selection
CCMR1_Input 0x18 - capture/compare mode register 1 (input mode)
_ :: Bits 17 -- (Reserved)
IC2F :: Bits 3 -- Input capture 2 filter
IC2PSC :: Bits 2 -- Input capture 2 prescaler
CC2S :: Bits 2 -- Capture/Compare 2 selection
_ :: Bit -- (Reserved)
IC1F :: Bits 3 -- Input capture 1 filter
IC1PSC :: Bits 2 -- Input capture 1 prescaler
CC1S :: Bits 2 -- Capture/Compare 1 selection
CCER 0x20 - capture/compare enable register
_ :: Bits 24 -- (Reserved)
CC2NP :: Bit -- Capture/Compare 2 output Polarity
_ :: Bit -- (Reserved)
CC2P :: Bit -- Capture/Compare 2 output Polarity
CC2E :: Bit -- Capture/Compare 2 output enable
CC1NP :: Bit -- Capture/Compare 1 output Polarity
_ :: Bit -- (Reserved)
CC1P :: Bit -- Capture/Compare 1 output Polarity
CC1E :: Bit -- Capture/Compare 1 output enable
CNT 0x24 - counter
_ :: Bits 16 -- (Reserved)
CNT :: Bits 16 -- counter value
PSC 0x28 - prescaler
_ :: Bits 16 -- (Reserved)
PSC :: Bits 16 -- Prescaler value
ARR 0x2c - auto-reload register
_ :: Bits 16 -- (Reserved)
ARR :: Bits 16 -- Auto-reload value
CCR1 0x34 - capture/compare register
_ :: Bits 16 -- (Reserved)
CCR :: Bits 16 -- Capture/Compare value
CCR2 0x38 - capture/compare register
_ :: Bits 16 -- (Reserved)
CCR :: Bits 16 -- Capture/Compare value
TIM10 0x40014400 General-purpose-timers
CR1 0x0 - control register 1
_ :: Bits 22 -- (Reserved)
CKD :: Bits 2 -- Clock division
ARPE :: Bit -- Auto-reload preload enable
_ :: Bits 3 -- (Reserved)
OPM :: Bit -- One-pulse mode
URS :: Bit -- Update request source
UDIS :: Bit -- Update disable
CEN :: Bit -- Counter enable
DIER 0xc - DMA/Interrupt enable register
_ :: Bits 30 -- (Reserved)
CC1IE :: Bit -- Capture/Compare 1 interrupt enable
UIE :: Bit -- Update interrupt enable
SR 0x10 - status register
_ :: Bits 22 -- (Reserved)
CC1OF :: Bit -- Capture/Compare 1 overcapture flag
_ :: Bits 7 -- (Reserved)
CC1IF :: Bit -- Capture/compare 1 interrupt flag
UIF :: Bit -- Update interrupt flag
EGR 0x14 - event generation register
_ :: Bits 30 -- (Reserved)
CC1G :: Bit -- Capture/compare 1 generation
UG :: Bit -- Update generation
CCMR1_Output 0x18 - capture/compare mode register 1 (output mode)
_ :: Bits 25 -- (Reserved)
OC1M :: Bits 3 -- Output Compare 1 mode
OC1PE :: Bit -- Output Compare 1 preload enable
OC1FE :: Bit -- Output Compare 1 fast enable
CC1S :: Bits 2 -- Capture/Compare 1 selection
CCMR1_Input 0x18 - capture/compare mode register 1 (input mode)
_ :: Bits 24 -- (Reserved)
IC1F :: Bits 4 -- Input capture 1 filter
IC1PSC :: Bits 2 -- Input capture 1 prescaler
CC1S :: Bits 2 -- Capture/Compare 1 selection
CCER 0x20 - capture/compare enable register
_ :: Bits 28 -- (Reserved)
CC1NP :: Bit -- Capture/Compare 1 output Polarity
_ :: Bit -- (Reserved)
CC1P :: Bit -- Capture/Compare 1 output Polarity
CC1E :: Bit -- Capture/Compare 1 output enable
CNT 0x24 - counter
_ :: Bits 16 -- (Reserved)
CNT :: Bits 16 -- counter value
PSC 0x28 - prescaler
_ :: Bits 16 -- (Reserved)
PSC :: Bits 16 -- Prescaler value
ARR 0x2c - auto-reload register
_ :: Bits 16 -- (Reserved)
ARR :: Bits 16 -- Auto-reload value
CCR1 0x34 - capture/compare register
_ :: Bits 16 -- (Reserved)
CCR :: Bits 16 -- Capture/Compare value
TIM11 0x40014800 General-purpose-timers
CR1 0x0 - control register 1
_ :: Bits 22 -- (Reserved)
CKD :: Bits 2 -- Clock division
ARPE :: Bit -- Auto-reload preload enable
_ :: Bits 3 -- (Reserved)
OPM :: Bit -- One-pulse mode
URS :: Bit -- Update request source
UDIS :: Bit -- Update disable
CEN :: Bit -- Counter enable
DIER 0xc - DMA/Interrupt enable register
_ :: Bits 30 -- (Reserved)
CC1IE :: Bit -- Capture/Compare 1 interrupt enable
UIE :: Bit -- Update interrupt enable
SR 0x10 - status register
_ :: Bits 22 -- (Reserved)
CC1OF :: Bit -- Capture/Compare 1 overcapture flag
_ :: Bits 7 -- (Reserved)
CC1IF :: Bit -- Capture/compare 1 interrupt flag
UIF :: Bit -- Update interrupt flag
EGR 0x14 - event generation register
_ :: Bits 30 -- (Reserved)
CC1G :: Bit -- Capture/compare 1 generation
UG :: Bit -- Update generation
CCMR1_Output 0x18 - capture/compare mode register 1 (output mode)
_ :: Bits 25 -- (Reserved)
OC1M :: Bits 3 -- Output Compare 1 mode
OC1PE :: Bit -- Output Compare 1 preload enable
OC1FE :: Bit -- Output Compare 1 fast enable
CC1S :: Bits 2 -- Capture/Compare 1 selection
CCMR1_Input 0x18 - capture/compare mode register 1 (input mode)
_ :: Bits 24 -- (Reserved)
IC1F :: Bits 4 -- Input capture 1 filter
IC1PSC :: Bits 2 -- Input capture 1 prescaler
CC1S :: Bits 2 -- Capture/Compare 1 selection
CCER 0x20 - capture/compare enable register
_ :: Bits 28 -- (Reserved)
CC1NP :: Bit -- Capture/Compare 1 output Polarity
_ :: Bit -- (Reserved)
CC1P :: Bit -- Capture/Compare 1 output Polarity
CC1E :: Bit -- Capture/Compare 1 output enable
CNT 0x24 - counter
_ :: Bits 16 -- (Reserved)
CNT :: Bits 16 -- counter value
PSC 0x28 - prescaler
_ :: Bits 16 -- (Reserved)
PSC :: Bits 16 -- Prescaler value
ARR 0x2c - auto-reload register
_ :: Bits 16 -- (Reserved)
ARR :: Bits 16 -- Auto-reload value
CCR1 0x34 - capture/compare register
_ :: Bits 16 -- (Reserved)
CCR :: Bits 16 -- Capture/Compare value
OR 0x50 - option register
_ :: Bits 30 -- (Reserved)
RMP :: Bits 2 -- Input 1 remapping capability
SPI5 0x40015000
Derived from SPI1
SPI6 0x40015400
Derived from SPI1
SAI1 0x40015800 Serial audio interface
CR1 0x4 - SAI AConfiguration register 1
_ :: Bits 8 -- (Reserved)
MCKDIV :: Bits 4 -- Master clock divider
NODIV :: Bit -- No divider
_ :: Bit -- (Reserved)
DMAEN :: Bit -- DMA enable
SAIEN :: Bit -- Audio block enable
_ :: Bits 2 -- (Reserved)
OUTDRIV :: Bit -- Output drive
MONO :: Bit -- Mono mode
SYNCEN :: Bits 2 -- Synchronization enable
CKSTR :: Bit -- Clock strobing edge
LSBFIRST :: Bit -- Least significant bit first
DS :: Bits 3 -- Data size
_ :: Bit -- (Reserved)
PRTCFG :: Bits 2 -- Protocol configuration
MODE :: Bits 2 -- Audio block mode
CR2 0x8 - SAI AConfiguration register 2
_ :: Bits 16 -- (Reserved)
COMP :: Bits 2 -- Companding mode
CPL :: Bit -- Complement bit
MUTECNT :: Bits 6 -- Mute counter
MUTEVAL :: Bit -- Mute value
MUTE :: Bit -- Mute
TRIS :: Bit -- Tristate management on data line
FFLUSH :: Bit -- FIFO flush
FTH :: Bits 3 -- FIFO threshold
FRCR 0xc - SAI AFrame configuration register
_ :: Bits 13 -- (Reserved)
FSOFF :: Bit -- Frame synchronization offset
FSPOL :: Bit -- Frame synchronization polarity
FSDEF :: Bit -- Frame synchronization definition
_ :: Bit -- (Reserved)
FSALL :: Bits 7 -- Frame synchronization active level length
FRL :: Bits 8 -- Frame length
SLOTR 0x10 - SAI ASlot register
SLOTEN :: Bits 16 -- Slot enable
_ :: Bits 4 -- (Reserved)
NBSLOT :: Bits 4 -- Number of slots in an audio frame
SLOTSZ :: Bits 2 -- Slot size
_ :: Bit -- (Reserved)
FBOFF :: Bits 5 -- First bit offset
IM 0x14 - SAI AInterrupt mask register2
_ :: Bits 25 -- (Reserved)
LFSDETIE :: Bit -- Late frame synchronization detection interrupt enable
AFSDETIE :: Bit -- Anticipated frame synchronization detection interrupt enable
CNRDYIE :: Bit -- Codec not ready interrupt enable
FREQIE :: Bit -- FIFO request interrupt enable
WCKCFGIE :: Bit -- Wrong clock configuration interrupt enable
MUTEDETIE :: Bit -- Mute detection interrupt enable
OVRUDRIE :: Bit -- Overrun/underrun interrupt enable
SR 0x18 - SAI AStatus register
_ :: Bits 13 -- (Reserved)
FLVL :: Bits 3 -- FIFO level threshold
_ :: Bits 9 -- (Reserved)
LFSDET :: Bit -- Late frame synchronization detection
AFSDET :: Bit -- Anticipated frame synchronization detection
CNRDY :: Bit -- Codec not ready
FREQ :: Bit -- FIFO request
WCKCFG :: Bit -- Wrong clock configuration flag
MUTEDET :: Bit -- Mute detection
OVRUDR :: Bit -- Overrun / underrun
CLRFR 0x1c - SAI AClear flag register
_ :: Bits 25 -- (Reserved)
CLFSDET :: Bit -- Clear late frame synchronization detection flag
CAFSDET :: Bit -- Clear anticipated frame synchronization detection flag
CCNRDY :: Bit -- Clear codec not ready flag
_ :: Bit -- (Reserved)
CWCKCFG :: Bit -- Clear wrong clock configuration flag
CMUTEDET :: Bit -- Mute detection flag
COVRUDR :: Bit -- Clear overrun / underrun
DR 0x20 - SAI AData register
DATA :: Bits 32 -- Data
CR1 0x24 - SAI AConfiguration register 1
_ :: Bits 8 -- (Reserved)
MCKDIV :: Bits 4 -- Master clock divider
NODIV :: Bit -- No divider
_ :: Bit -- (Reserved)
DMAEN :: Bit -- DMA enable
SAIEN :: Bit -- Audio block enable
_ :: Bits 2 -- (Reserved)
OUTDRIV :: Bit -- Output drive
MONO :: Bit -- Mono mode
SYNCEN :: Bits 2 -- Synchronization enable
CKSTR :: Bit -- Clock strobing edge
LSBFIRST :: Bit -- Least significant bit first
DS :: Bits 3 -- Data size
_ :: Bit -- (Reserved)
PRTCFG :: Bits 2 -- Protocol configuration
MODE :: Bits 2 -- Audio block mode
CR2 0x28 - SAI AConfiguration register 2
_ :: Bits 16 -- (Reserved)
COMP :: Bits 2 -- Companding mode
CPL :: Bit -- Complement bit
MUTECNT :: Bits 6 -- Mute counter
MUTEVAL :: Bit -- Mute value
MUTE :: Bit -- Mute
TRIS :: Bit -- Tristate management on data line
FFLUSH :: Bit -- FIFO flush
FTH :: Bits 3 -- FIFO threshold
FRCR 0x2c - SAI AFrame configuration register
_ :: Bits 13 -- (Reserved)
FSOFF :: Bit -- Frame synchronization offset
FSPOL :: Bit -- Frame synchronization polarity
FSDEF :: Bit -- Frame synchronization definition
_ :: Bit -- (Reserved)
FSALL :: Bits 7 -- Frame synchronization active level length
FRL :: Bits 8 -- Frame length
SLOTR 0x30 - SAI ASlot register
SLOTEN :: Bits 16 -- Slot enable
_ :: Bits 4 -- (Reserved)
NBSLOT :: Bits 4 -- Number of slots in an audio frame
SLOTSZ :: Bits 2 -- Slot size
_ :: Bit -- (Reserved)
FBOFF :: Bits 5 -- First bit offset
IM 0x34 - SAI AInterrupt mask register2
_ :: Bits 25 -- (Reserved)
LFSDETIE :: Bit -- Late frame synchronization detection interrupt enable
AFSDETIE :: Bit -- Anticipated frame synchronization detection interrupt enable
CNRDYIE :: Bit -- Codec not ready interrupt enable
FREQIE :: Bit -- FIFO request interrupt enable
WCKCFGIE :: Bit -- Wrong clock configuration interrupt enable
MUTEDETIE :: Bit -- Mute detection interrupt enable
OVRUDRIE :: Bit -- Overrun/underrun interrupt enable
SR 0x38 - SAI AStatus register
_ :: Bits 13 -- (Reserved)
FLVL :: Bits 3 -- FIFO level threshold
_ :: Bits 9 -- (Reserved)
LFSDET :: Bit -- Late frame synchronization detection
AFSDET :: Bit -- Anticipated frame synchronization detection
CNRDY :: Bit -- Codec not ready
FREQ :: Bit -- FIFO request
WCKCFG :: Bit -- Wrong clock configuration flag
MUTEDET :: Bit -- Mute detection
OVRUDR :: Bit -- Overrun / underrun
CLRFR 0x3c - SAI AClear flag register
_ :: Bits 25 -- (Reserved)
CLFSDET :: Bit -- Clear late frame synchronization detection flag
CAFSDET :: Bit -- Clear anticipated frame synchronization detection flag
CCNRDY :: Bit -- Clear codec not ready flag
_ :: Bit -- (Reserved)
CWCKCFG :: Bit -- Clear wrong clock configuration flag
CMUTEDET :: Bit -- Mute detection flag
COVRUDR :: Bit -- Clear overrun / underrun
DR 0x40 - SAI AData register
DATA :: Bits 32 -- Data
LTDC 0x40016800 LCD-TFT Controller
SSCR 0x8 - Synchronization Size Configuration Register
_ :: Bits 4 -- (Reserved)
HSW :: Bits 12 -- Horizontal Synchronization Width (in units of pixel clock period)
_ :: Bits 5 -- (Reserved)
VSH :: Bits 11 -- Vertical Synchronization Height (in units of horizontal scan line)
BPCR 0xc - Back Porch Configuration Register
_ :: Bits 4 -- (Reserved)
AHBP :: Bits 12 -- Accumulated Horizontal back porch (in units of pixel clock period)
_ :: Bits 5 -- (Reserved)
AVBP :: Bits 11 -- Accumulated Vertical back porch (in units of horizontal scan line)
AWCR 0x10 - Active Width Configuration Register
_ :: Bits 4 -- (Reserved)
AAW :: Bits 12 -- Accumulated Active Width (in units of pixel clock period)
_ :: Bits 5 -- (Reserved)
AAH :: Bits 11 -- Accumulated Active Height (in units of horizontal scan line)
TWCR 0x14 - Total Width Configuration Register
_ :: Bits 4 -- (Reserved)
TOTALW :: Bits 12 -- Total Width (in units of pixel clock period)
_ :: Bits 5 -- (Reserved)
TOTALH :: Bits 11 -- Total Height (in units of horizontal scan line)
GCR 0x18 - Global Control Register
HSPOL :: Bit -- Horizontal Synchronization Polarity
VSPOL :: Bit -- Vertical Synchronization Polarity
DEPOL :: Bit -- Data Enable Polarity
PCPOL :: Bit -- Pixel Clock Polarity
_ :: Bits 11 -- (Reserved)
DEN :: Bit -- Dither Enable
_ :: Bit -- (Reserved)
DRW :: Bits 3 -- Dither Red Width
_ :: Bit -- (Reserved)
DGW :: Bits 3 -- Dither Green Width
_ :: Bit -- (Reserved)
DBW :: Bits 3 -- Dither Blue Width
_ :: Bits 3 -- (Reserved)
LTDCEN :: Bit -- LCD-TFT controller enable bit
SRCR 0x24 - Shadow Reload Configuration Register
_ :: Bits 30 -- (Reserved)
VBR :: Bit -- Vertical Blanking Reload
IMR :: Bit -- Immediate Reload
BCCR 0x2c - Background Color Configuration Register
_ :: Bits 8 -- (Reserved)
BCRED :: Bits 8 -- Background color red value
BCGREEN :: Bits 8 -- Background color green value
BCBLUE :: Bits 8 -- Background color blue value
IER 0x34 - Interrupt Enable Register
_ :: Bits 28 -- (Reserved)
RRIE :: Bit -- Register Reload interrupt enable
TERRIE :: Bit -- Transfer Error Interrupt Enable
FUIE :: Bit -- FIFO Underrun Interrupt Enable
LIE :: Bit -- Line Interrupt Enable
ISR 0x38 - Interrupt Status Register
_ :: Bits 28 -- (Reserved)
RRIF :: Bit -- Register Reload Interrupt Flag
TERRIF :: Bit -- Transfer Error interrupt flag
FUIF :: Bit -- FIFO Underrun Interrupt flag
LIF :: Bit -- Line Interrupt flag
ICR 0x3c - Interrupt Clear Register
_ :: Bits 28 -- (Reserved)
CRRIF :: Bit -- Clears Register Reload Interrupt Flag
CTERRIF :: Bit -- Clears the Transfer Error Interrupt Flag
CFUIF :: Bit -- Clears the FIFO Underrun Interrupt flag
CLIF :: Bit -- Clears the Line Interrupt Flag
LIPCR 0x40 - Line Interrupt Position Configuration Register
_ :: Bits 21 -- (Reserved)
LIPOS :: Bits 11 -- Line Interrupt Position
CPSR 0x44 - Current Position Status Register
CXPOS :: Bits 16 -- Current X Position
CYPOS :: Bits 16 -- Current Y Position
CDSR 0x48 - Current Display Status Register
_ :: Bits 28 -- (Reserved)
HSYNCS :: Bit -- Horizontal Synchronization display Status
VSYNCS :: Bit -- Vertical Synchronization display Status
HDES :: Bit -- Horizontal Data Enable display Status
VDES :: Bit -- Vertical Data Enable display Status
CR 0x84 - Layerx Control Register
_ :: Bits 27 -- (Reserved)
CLUTEN :: Bit -- Color Look-Up Table Enable
_ :: Bits 2 -- (Reserved)
COLKEN :: Bit -- Color Keying Enable
LEN :: Bit -- Layer Enable
WHPCR 0x88 - Layerx Window Horizontal Position Configuration Register
_ :: Bits 4 -- (Reserved)
WHSPPOS :: Bits 12 -- Window Horizontal Stop Position
_ :: Bits 4 -- (Reserved)
WHSTPOS :: Bits 12 -- Window Horizontal Start Position
WVPCR 0x8c - Layerx Window Vertical Position Configuration Register
_ :: Bits 5 -- (Reserved)
WVSPPOS :: Bits 11 -- Window Vertical Stop Position
_ :: Bits 5 -- (Reserved)
WVSTPOS :: Bits 11 -- Window Vertical Start Position
CKCR 0x90 - Layerx Color Keying Configuration Register
_ :: Bits 8 -- (Reserved)
CKRED :: Bits 8 -- Color Key Red value
CKGREEN :: Bits 8 -- Color Key Green value
CKBLUE :: Bits 8 -- Color Key Blue value
PFCR 0x94 - Layerx Pixel Format Configuration Register
_ :: Bits 29 -- (Reserved)
PF :: Bits 3 -- Pixel Format
CACR 0x98 - Layerx Constant Alpha Configuration Register
_ :: Bits 24 -- (Reserved)
CONSTA :: Bits 8 -- Constant Alpha
DCCR 0x9c - Layerx Default Color Configuration Register
DCALPHA :: Bits 8 -- Default Color Alpha
DCRED :: Bits 8 -- Default Color Red
DCGREEN :: Bits 8 -- Default Color Green
DCBLUE :: Bits 8 -- Default Color Blue
BFCR 0xa0 - Layerx Blending Factors Configuration Register
_ :: Bits 21 -- (Reserved)
BF1 :: Bits 3 -- Blending Factor 1
_ :: Bits 5 -- (Reserved)
BF2 :: Bits 3 -- Blending Factor 2
CFBAR 0xac - Layerx Color Frame Buffer Address Register
CFBADD :: Bits 32 -- Color Frame Buffer Start Address
CFBLR 0xb0 - Layerx Color Frame Buffer Length Register
_ :: Bits 3 -- (Reserved)
CFBP :: Bits 13 -- Color Frame Buffer Pitch in bytes
_ :: Bits 3 -- (Reserved)
CFBLL :: Bits 13 -- Color Frame Buffer Line Length
CFBLNR 0xb4 - Layerx ColorFrame Buffer Line Number Register
_ :: Bits 21 -- (Reserved)
CFBLNBR :: Bits 11 -- Frame Buffer Line Number
CLUTWR 0xc4 - Layerx CLUT Write Register
CLUTADD :: Bits 8 -- CLUT Address
RED :: Bits 8 -- Red value
GREEN :: Bits 8 -- Green value
BLUE :: Bits 8 -- Blue value
CR 0x104 - Layerx Control Register
_ :: Bits 27 -- (Reserved)
CLUTEN :: Bit -- Color Look-Up Table Enable
_ :: Bits 2 -- (Reserved)
COLKEN :: Bit -- Color Keying Enable
LEN :: Bit -- Layer Enable
WHPCR 0x108 - Layerx Window Horizontal Position Configuration Register
_ :: Bits 4 -- (Reserved)
WHSPPOS :: Bits 12 -- Window Horizontal Stop Position
_ :: Bits 4 -- (Reserved)
WHSTPOS :: Bits 12 -- Window Horizontal Start Position
WVPCR 0x10c - Layerx Window Vertical Position Configuration Register
_ :: Bits 5 -- (Reserved)
WVSPPOS :: Bits 11 -- Window Vertical Stop Position
_ :: Bits 5 -- (Reserved)
WVSTPOS :: Bits 11 -- Window Vertical Start Position
CKCR 0x110 - Layerx Color Keying Configuration Register
_ :: Bits 8 -- (Reserved)
CKRED :: Bits 8 -- Color Key Red value
CKGREEN :: Bits 8 -- Color Key Green value
CKBLUE :: Bits 8 -- Color Key Blue value
PFCR 0x114 - Layerx Pixel Format Configuration Register
_ :: Bits 29 -- (Reserved)
PF :: Bits 3 -- Pixel Format
CACR 0x118 - Layerx Constant Alpha Configuration Register
_ :: Bits 24 -- (Reserved)
CONSTA :: Bits 8 -- Constant Alpha
DCCR 0x11c - Layerx Default Color Configuration Register
DCALPHA :: Bits 8 -- Default Color Alpha
DCRED :: Bits 8 -- Default Color Red
DCGREEN :: Bits 8 -- Default Color Green
DCBLUE :: Bits 8 -- Default Color Blue
BFCR 0x120 - Layerx Blending Factors Configuration Register
_ :: Bits 21 -- (Reserved)
BF1 :: Bits 3 -- Blending Factor 1
_ :: Bits 5 -- (Reserved)
BF2 :: Bits 3 -- Blending Factor 2
CFBAR 0x12c - Layerx Color Frame Buffer Address Register
CFBADD :: Bits 32 -- Color Frame Buffer Start Address
CFBLR 0x130 - Layerx Color Frame Buffer Length Register
_ :: Bits 3 -- (Reserved)
CFBP :: Bits 13 -- Color Frame Buffer Pitch in bytes
_ :: Bits 3 -- (Reserved)
CFBLL :: Bits 13 -- Color Frame Buffer Line Length
CFBLNR 0x134 - Layerx ColorFrame Buffer Line Number Register
_ :: Bits 21 -- (Reserved)
CFBLNBR :: Bits 11 -- Frame Buffer Line Number
CLUTWR 0x144 - Layerx CLUT Write Register
CLUTADD :: Bits 8 -- CLUT Address
RED :: Bits 8 -- Red value
GREEN :: Bits 8 -- Green value
BLUE :: Bits 8 -- Blue value
GPIOA 0x40020000 General-purpose I/Os
MODER 0x0 - GPIO port mode register
MODER15 :: Bits 2 -- Port x configuration pin 15
MODER14 :: Bits 2 -- Port x configuration pin 14
MODER13 :: Bits 2 -- Port x configuration pin 13
MODER12 :: Bits 2 -- Port x configuration pin 12
MODER11 :: Bits 2 -- Port x configuration pin 11
MODER10 :: Bits 2 -- Port x configuration pin 10
MODER9 :: Bits 2 -- Port x configuration pin 9
MODER8 :: Bits 2 -- Port x configuration pin 8
MODER7 :: Bits 2 -- Port x configuration pin 7
MODER6 :: Bits 2 -- Port x configuration pin 6
MODER5 :: Bits 2 -- Port x configuration pin 5
MODER4 :: Bits 2 -- Port x configuration pin 4
MODER3 :: Bits 2 -- Port x configuration pin 3
MODER2 :: Bits 2 -- Port x configuration pin 2
MODER1 :: Bits 2 -- Port x configuration pin 1
MODER0 :: Bits 2 -- Port x configuration pin 0
OTYPER 0x4 - GPIO port output type register
_ :: Bits 16 -- (Reserved)
OT15 :: Bit -- Port x configuration pin 15
OT14 :: Bit -- Port x configuration pin 14
OT13 :: Bit -- Port x configuration pin 13
OT12 :: Bit -- Port x configuration pin 12
OT11 :: Bit -- Port x configuration pin 11
OT10 :: Bit -- Port x configuration pin 10
OT9 :: Bit -- Port x configuration pin 9
OT8 :: Bit -- Port x configuration pin 8
OT7 :: Bit -- Port x configuration pin 7
OT6 :: Bit -- Port x configuration pin 6
OT5 :: Bit -- Port x configuration pin 5
OT4 :: Bit -- Port x configuration pin 4
OT3 :: Bit -- Port x configuration pin 3
OT2 :: Bit -- Port x configuration pin 2
OT1 :: Bit -- Port x configuration pin 1
OT0 :: Bit -- Port x configuration pin 0
OSPEEDR 0x8 - GPIO port output speed register
OSPEEDR15 :: Bits 2 -- Port x configuration pin 15
OSPEEDR14 :: Bits 2 -- Port x configuration pin 14
OSPEEDR13 :: Bits 2 -- Port x configuration pin 13
OSPEEDR12 :: Bits 2 -- Port x configuration pin 12
OSPEEDR11 :: Bits 2 -- Port x configuration pin 11
OSPEEDR10 :: Bits 2 -- Port x configuration pin 10
OSPEEDR9 :: Bits 2 -- Port x configuration pin 9
OSPEEDR8 :: Bits 2 -- Port x configuration pin 8
OSPEEDR7 :: Bits 2 -- Port x configuration pin 7
OSPEEDR6 :: Bits 2 -- Port x configuration pin 6
OSPEEDR5 :: Bits 2 -- Port x configuration pin 5
OSPEEDR4 :: Bits 2 -- Port x configuration pin 4
OSPEEDR3 :: Bits 2 -- Port x configuration pin 3
OSPEEDR2 :: Bits 2 -- Port x configuration pin 2
OSPEEDR1 :: Bits 2 -- Port x configuration pin 1
OSPEEDR0 :: Bits 2 -- Port x configuration pin 0
PUPDR 0xc - GPIO port pull-up/pull-down register
PUPDR15 :: Bits 2 -- Port x configuration pin 15
PUPDR14 :: Bits 2 -- Port x configuration pin 14
PUPDR13 :: Bits 2 -- Port x configuration pin 13
PUPDR12 :: Bits 2 -- Port x configuration pin 12
PUPDR11 :: Bits 2 -- Port x configuration pin 11
PUPDR10 :: Bits 2 -- Port x configuration pin 10
PUPDR9 :: Bits 2 -- Port x configuration pin 9
PUPDR8 :: Bits 2 -- Port x configuration pin 8
PUPDR7 :: Bits 2 -- Port x configuration pin 7
PUPDR6 :: Bits 2 -- Port x configuration pin 6
PUPDR5 :: Bits 2 -- Port x configuration pin 5
PUPDR4 :: Bits 2 -- Port x configuration pin 4
PUPDR3 :: Bits 2 -- Port x configuration pin 3
PUPDR2 :: Bits 2 -- Port x configuration pin 2
PUPDR1 :: Bits 2 -- Port x configuration pin 1
PUPDR0 :: Bits 2 -- Port x configuration pin 0
IDR 0x10 - GPIO port input data register
_ :: Bits 16 -- (Reserved)
IDR15 :: Bit -- Port input data pin 15
IDR14 :: Bit -- Port input data pin 14
IDR13 :: Bit -- Port input data pin 13
IDR12 :: Bit -- Port input data pin 12
IDR11 :: Bit -- Port input data pin 11
IDR10 :: Bit -- Port input data pin 10
IDR9 :: Bit -- Port input data pin 9
IDR8 :: Bit -- Port input data pin 8
IDR7 :: Bit -- Port input data pin 7
IDR6 :: Bit -- Port input data pin 6
IDR5 :: Bit -- Port input data pin 5
IDR4 :: Bit -- Port input data pin 4
IDR3 :: Bit -- Port input data pin 3
IDR2 :: Bit -- Port input data pin 2
IDR1 :: Bit -- Port input data pin 1
IDR0 :: Bit -- Port input data pin 0
ODR 0x14 - GPIO port output data register
_ :: Bits 16 -- (Reserved)
ODR15 :: Bit -- Port output data pin 15
ODR14 :: Bit -- Port output data pin 14
ODR13 :: Bit -- Port output data pin 13
ODR12 :: Bit -- Port output data pin 12
ODR11 :: Bit -- Port output data pin 11
ODR10 :: Bit -- Port output data pin 10
ODR9 :: Bit -- Port output data pin 9
ODR8 :: Bit -- Port output data pin 8
ODR7 :: Bit -- Port output data pin 7
ODR6 :: Bit -- Port output data pin 6
ODR5 :: Bit -- Port output data pin 5
ODR4 :: Bit -- Port output data pin 4
ODR3 :: Bit -- Port output data pin 3
ODR2 :: Bit -- Port output data pin 2
ODR1 :: Bit -- Port output data pin 1
ODR0 :: Bit -- Port output data pin 0
BSRR 0x18 - GPIO port bit set/reset register
BR15 :: Bit -- Port x reset pin 15
BR14 :: Bit -- Port x reset pin 14
BR13 :: Bit -- Port x reset pin 13
BR12 :: Bit -- Port x reset pin 12
BR11 :: Bit -- Port x reset pin 11
BR10 :: Bit -- Port x reset pin 10
BR9 :: Bit -- Port x reset pin 9
BR8 :: Bit -- Port x reset pin 8
BR7 :: Bit -- Port x reset pin 7
BR6 :: Bit -- Port x reset pin 6
BR5 :: Bit -- Port x reset pin 5
BR4 :: Bit -- Port x reset pin 4
BR3 :: Bit -- Port x reset pin 3
BR2 :: Bit -- Port x reset pin 2
BR1 :: Bit -- Port x reset pin 1
BR0 :: Bit -- Port x reset pin 0
BS15 :: Bit -- Port x set pin 15
BS14 :: Bit -- Port x set pin 14
BS13 :: Bit -- Port x set pin 13
BS12 :: Bit -- Port x set pin 12
BS11 :: Bit -- Port x set pin 11
BS10 :: Bit -- Port x set pin 10
BS9 :: Bit -- Port x set pin 9
BS8 :: Bit -- Port x set pin 8
BS7 :: Bit -- Port x set pin 7
BS6 :: Bit -- Port x set pin 6
BS5 :: Bit -- Port x set pin 5
BS4 :: Bit -- Port x set pin 4
BS3 :: Bit -- Port x set pin 3
BS2 :: Bit -- Port x set pin 2
BS1 :: Bit -- Port x set pin 1
BS0 :: Bit -- Port x set pin 0
LCKR 0x1c - GPIO port configuration lock register
_ :: Bits 15 -- (Reserved)
LCKK :: Bit -- Port x lock bit y (y= 0..15)
LCK15 :: Bit -- Port x lock pin 15
LCK14 :: Bit -- Port x lock pin 14
LCK13 :: Bit -- Port x lock pin 13
LCK12 :: Bit -- Port x lock pin 12
LCK11 :: Bit -- Port x lock pin 11
LCK10 :: Bit -- Port x lock pin 10
LCK9 :: Bit -- Port x lock pin 9
LCK8 :: Bit -- Port x lock pin 8
LCK7 :: Bit -- Port x lock pin 7
LCK6 :: Bit -- Port x lock pin 6
LCK5 :: Bit -- Port x lock pin 5
LCK4 :: Bit -- Port x lock pin 4
LCK3 :: Bit -- Port x lock pin 3
LCK2 :: Bit -- Port x lock pin 2
LCK1 :: Bit -- Port x lock pin 1
LCK0 :: Bit -- Port x lock pin 0
AFRL 0x20 - GPIO alternate function low register
AFRL7 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL6 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL5 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL4 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL3 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL2 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL1 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL0 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRH 0x24 - GPIO alternate function high register
AFRH15 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH14 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH13 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH12 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH11 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH10 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH9 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH8 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
GPIOB 0x40020400 General-purpose I/Os
MODER 0x0 - GPIO port mode register
MODER15 :: Bits 2 -- Port x configuration pin 15
MODER14 :: Bits 2 -- Port x configuration pin 14
MODER13 :: Bits 2 -- Port x configuration pin 13
MODER12 :: Bits 2 -- Port x configuration pin 12
MODER11 :: Bits 2 -- Port x configuration pin 11
MODER10 :: Bits 2 -- Port x configuration pin 10
MODER9 :: Bits 2 -- Port x configuration pin 9
MODER8 :: Bits 2 -- Port x configuration pin 8
MODER7 :: Bits 2 -- Port x configuration pin 7
MODER6 :: Bits 2 -- Port x configuration pin 6
MODER5 :: Bits 2 -- Port x configuration pin 5
MODER4 :: Bits 2 -- Port x configuration pin 4
MODER3 :: Bits 2 -- Port x configuration pin 3
MODER2 :: Bits 2 -- Port x configuration pin 2
MODER1 :: Bits 2 -- Port x configuration pin 1
MODER0 :: Bits 2 -- Port x configuration pin 0
OTYPER 0x4 - GPIO port output type register
_ :: Bits 16 -- (Reserved)
OT15 :: Bit -- Port x configuration pin 15
OT14 :: Bit -- Port x configuration pin 14
OT13 :: Bit -- Port x configuration pin 13
OT12 :: Bit -- Port x configuration pin 12
OT11 :: Bit -- Port x configuration pin 11
OT10 :: Bit -- Port x configuration pin 10
OT9 :: Bit -- Port x configuration pin 9
OT8 :: Bit -- Port x configuration pin 8
OT7 :: Bit -- Port x configuration pin 7
OT6 :: Bit -- Port x configuration pin 6
OT5 :: Bit -- Port x configuration pin 5
OT4 :: Bit -- Port x configuration pin 4
OT3 :: Bit -- Port x configuration pin 3
OT2 :: Bit -- Port x configuration pin 2
OT1 :: Bit -- Port x configuration pin 1
OT0 :: Bit -- Port x configuration pin 0
OSPEEDR 0x8 - GPIO port output speed register
OSPEEDR15 :: Bits 2 -- Port x configuration pin 15
OSPEEDR14 :: Bits 2 -- Port x configuration pin 14
OSPEEDR13 :: Bits 2 -- Port x configuration pin 13
OSPEEDR12 :: Bits 2 -- Port x configuration pin 12
OSPEEDR11 :: Bits 2 -- Port x configuration pin 11
OSPEEDR10 :: Bits 2 -- Port x configuration pin 10
OSPEEDR9 :: Bits 2 -- Port x configuration pin 9
OSPEEDR8 :: Bits 2 -- Port x configuration pin 8
OSPEEDR7 :: Bits 2 -- Port x configuration pin 7
OSPEEDR6 :: Bits 2 -- Port x configuration pin 6
OSPEEDR5 :: Bits 2 -- Port x configuration pin 5
OSPEEDR4 :: Bits 2 -- Port x configuration pin 4
OSPEEDR3 :: Bits 2 -- Port x configuration pin 3
OSPEEDR2 :: Bits 2 -- Port x configuration pin 2
OSPEEDR1 :: Bits 2 -- Port x configuration pin 1
OSPEEDR0 :: Bits 2 -- Port x configuration pin 0
PUPDR 0xc - GPIO port pull-up/pull-down register
PUPDR15 :: Bits 2 -- Port x configuration pin 15
PUPDR14 :: Bits 2 -- Port x configuration pin 14
PUPDR13 :: Bits 2 -- Port x configuration pin 13
PUPDR12 :: Bits 2 -- Port x configuration pin 12
PUPDR11 :: Bits 2 -- Port x configuration pin 11
PUPDR10 :: Bits 2 -- Port x configuration pin 10
PUPDR9 :: Bits 2 -- Port x configuration pin 9
PUPDR8 :: Bits 2 -- Port x configuration pin 8
PUPDR7 :: Bits 2 -- Port x configuration pin 7
PUPDR6 :: Bits 2 -- Port x configuration pin 6
PUPDR5 :: Bits 2 -- Port x configuration pin 5
PUPDR4 :: Bits 2 -- Port x configuration pin 4
PUPDR3 :: Bits 2 -- Port x configuration pin 3
PUPDR2 :: Bits 2 -- Port x configuration pin 2
PUPDR1 :: Bits 2 -- Port x configuration pin 1
PUPDR0 :: Bits 2 -- Port x configuration pin 0
IDR 0x10 - GPIO port input data register
_ :: Bits 16 -- (Reserved)
IDR15 :: Bit -- Port input data pin 15
IDR14 :: Bit -- Port input data pin 14
IDR13 :: Bit -- Port input data pin 13
IDR12 :: Bit -- Port input data pin 12
IDR11 :: Bit -- Port input data pin 11
IDR10 :: Bit -- Port input data pin 10
IDR9 :: Bit -- Port input data pin 9
IDR8 :: Bit -- Port input data pin 8
IDR7 :: Bit -- Port input data pin 7
IDR6 :: Bit -- Port input data pin 6
IDR5 :: Bit -- Port input data pin 5
IDR4 :: Bit -- Port input data pin 4
IDR3 :: Bit -- Port input data pin 3
IDR2 :: Bit -- Port input data pin 2
IDR1 :: Bit -- Port input data pin 1
IDR0 :: Bit -- Port input data pin 0
ODR 0x14 - GPIO port output data register
_ :: Bits 16 -- (Reserved)
ODR15 :: Bit -- Port output data pin 15
ODR14 :: Bit -- Port output data pin 14
ODR13 :: Bit -- Port output data pin 13
ODR12 :: Bit -- Port output data pin 12
ODR11 :: Bit -- Port output data pin 11
ODR10 :: Bit -- Port output data pin 10
ODR9 :: Bit -- Port output data pin 9
ODR8 :: Bit -- Port output data pin 8
ODR7 :: Bit -- Port output data pin 7
ODR6 :: Bit -- Port output data pin 6
ODR5 :: Bit -- Port output data pin 5
ODR4 :: Bit -- Port output data pin 4
ODR3 :: Bit -- Port output data pin 3
ODR2 :: Bit -- Port output data pin 2
ODR1 :: Bit -- Port output data pin 1
ODR0 :: Bit -- Port output data pin 0
BSRR 0x18 - GPIO port bit set/reset register
BR15 :: Bit -- Port x reset pin 15
BR14 :: Bit -- Port x reset pin 14
BR13 :: Bit -- Port x reset pin 13
BR12 :: Bit -- Port x reset pin 12
BR11 :: Bit -- Port x reset pin 11
BR10 :: Bit -- Port x reset pin 10
BR9 :: Bit -- Port x reset pin 9
BR8 :: Bit -- Port x reset pin 8
BR7 :: Bit -- Port x reset pin 7
BR6 :: Bit -- Port x reset pin 6
BR5 :: Bit -- Port x reset pin 5
BR4 :: Bit -- Port x reset pin 4
BR3 :: Bit -- Port x reset pin 3
BR2 :: Bit -- Port x reset pin 2
BR1 :: Bit -- Port x reset pin 1
BR0 :: Bit -- Port x reset pin 0
BS15 :: Bit -- Port x set pin 15
BS14 :: Bit -- Port x set pin 14
BS13 :: Bit -- Port x set pin 13
BS12 :: Bit -- Port x set pin 12
BS11 :: Bit -- Port x set pin 11
BS10 :: Bit -- Port x set pin 10
BS9 :: Bit -- Port x set pin 9
BS8 :: Bit -- Port x set pin 8
BS7 :: Bit -- Port x set pin 7
BS6 :: Bit -- Port x set pin 6
BS5 :: Bit -- Port x set pin 5
BS4 :: Bit -- Port x set pin 4
BS3 :: Bit -- Port x set pin 3
BS2 :: Bit -- Port x set pin 2
BS1 :: Bit -- Port x set pin 1
BS0 :: Bit -- Port x set pin 0
LCKR 0x1c - GPIO port configuration lock register
_ :: Bits 15 -- (Reserved)
LCKK :: Bit -- Port x lock bit y (y= 0..15)
LCK15 :: Bit -- Port x lock pin 15
LCK14 :: Bit -- Port x lock pin 14
LCK13 :: Bit -- Port x lock pin 13
LCK12 :: Bit -- Port x lock pin 12
LCK11 :: Bit -- Port x lock pin 11
LCK10 :: Bit -- Port x lock pin 10
LCK9 :: Bit -- Port x lock pin 9
LCK8 :: Bit -- Port x lock pin 8
LCK7 :: Bit -- Port x lock pin 7
LCK6 :: Bit -- Port x lock pin 6
LCK5 :: Bit -- Port x lock pin 5
LCK4 :: Bit -- Port x lock pin 4
LCK3 :: Bit -- Port x lock pin 3
LCK2 :: Bit -- Port x lock pin 2
LCK1 :: Bit -- Port x lock pin 1
LCK0 :: Bit -- Port x lock pin 0
AFRL 0x20 - GPIO alternate function low register
AFRL7 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL6 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL5 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL4 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL3 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL2 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL1 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL0 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRH 0x24 - GPIO alternate function high register
AFRH15 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH14 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH13 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH12 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH11 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH10 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH9 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH8 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
GPIOC 0x40020800
Derived from GPIOI
GPIOD 0x40020c00
Derived from GPIOI
GPIOE 0x40021000
Derived from GPIOI
GPIOF 0x40021400
Derived from GPIOI
GPIOG 0x40021800
Derived from GPIOI
GPIOH 0x40021c00
Derived from GPIOI
GPIOI 0x40022000 General-purpose I/Os
MODER 0x0 - GPIO port mode register
MODER15 :: Bits 2 -- Port x configuration pin 15
MODER14 :: Bits 2 -- Port x configuration pin 14
MODER13 :: Bits 2 -- Port x configuration pin 13
MODER12 :: Bits 2 -- Port x configuration pin 12
MODER11 :: Bits 2 -- Port x configuration pin 11
MODER10 :: Bits 2 -- Port x configuration pin 10
MODER9 :: Bits 2 -- Port x configuration pin 9
MODER8 :: Bits 2 -- Port x configuration pin 8
MODER7 :: Bits 2 -- Port x configuration pin 7
MODER6 :: Bits 2 -- Port x configuration pin 6
MODER5 :: Bits 2 -- Port x configuration pin 5
MODER4 :: Bits 2 -- Port x configuration pin 4
MODER3 :: Bits 2 -- Port x configuration pin 3
MODER2 :: Bits 2 -- Port x configuration pin 2
MODER1 :: Bits 2 -- Port x configuration pin 1
MODER0 :: Bits 2 -- Port x configuration pin 0
OTYPER 0x4 - GPIO port output type register
_ :: Bits 16 -- (Reserved)
OT15 :: Bit -- Port x configuration pin 15
OT14 :: Bit -- Port x configuration pin 14
OT13 :: Bit -- Port x configuration pin 13
OT12 :: Bit -- Port x configuration pin 12
OT11 :: Bit -- Port x configuration pin 11
OT10 :: Bit -- Port x configuration pin 10
OT9 :: Bit -- Port x configuration pin 9
OT8 :: Bit -- Port x configuration pin 8
OT7 :: Bit -- Port x configuration pin 7
OT6 :: Bit -- Port x configuration pin 6
OT5 :: Bit -- Port x configuration pin 5
OT4 :: Bit -- Port x configuration pin 4
OT3 :: Bit -- Port x configuration pin 3
OT2 :: Bit -- Port x configuration pin 2
OT1 :: Bit -- Port x configuration pin 1
OT0 :: Bit -- Port x configuration pin 0
OSPEEDR 0x8 - GPIO port output speed register
OSPEEDR15 :: Bits 2 -- Port x configuration pin 15
OSPEEDR14 :: Bits 2 -- Port x configuration pin 14
OSPEEDR13 :: Bits 2 -- Port x configuration pin 13
OSPEEDR12 :: Bits 2 -- Port x configuration pin 12
OSPEEDR11 :: Bits 2 -- Port x configuration pin 11
OSPEEDR10 :: Bits 2 -- Port x configuration pin 10
OSPEEDR9 :: Bits 2 -- Port x configuration pin 9
OSPEEDR8 :: Bits 2 -- Port x configuration pin 8
OSPEEDR7 :: Bits 2 -- Port x configuration pin 7
OSPEEDR6 :: Bits 2 -- Port x configuration pin 6
OSPEEDR5 :: Bits 2 -- Port x configuration pin 5
OSPEEDR4 :: Bits 2 -- Port x configuration pin 4
OSPEEDR3 :: Bits 2 -- Port x configuration pin 3
OSPEEDR2 :: Bits 2 -- Port x configuration pin 2
OSPEEDR1 :: Bits 2 -- Port x configuration pin 1
OSPEEDR0 :: Bits 2 -- Port x configuration pin 0
PUPDR 0xc - GPIO port pull-up/pull-down register
PUPDR15 :: Bits 2 -- Port x configuration pin 15
PUPDR14 :: Bits 2 -- Port x configuration pin 14
PUPDR13 :: Bits 2 -- Port x configuration pin 13
PUPDR12 :: Bits 2 -- Port x configuration pin 12
PUPDR11 :: Bits 2 -- Port x configuration pin 11
PUPDR10 :: Bits 2 -- Port x configuration pin 10
PUPDR9 :: Bits 2 -- Port x configuration pin 9
PUPDR8 :: Bits 2 -- Port x configuration pin 8
PUPDR7 :: Bits 2 -- Port x configuration pin 7
PUPDR6 :: Bits 2 -- Port x configuration pin 6
PUPDR5 :: Bits 2 -- Port x configuration pin 5
PUPDR4 :: Bits 2 -- Port x configuration pin 4
PUPDR3 :: Bits 2 -- Port x configuration pin 3
PUPDR2 :: Bits 2 -- Port x configuration pin 2
PUPDR1 :: Bits 2 -- Port x configuration pin 1
PUPDR0 :: Bits 2 -- Port x configuration pin 0
IDR 0x10 - GPIO port input data register
_ :: Bits 16 -- (Reserved)
IDR15 :: Bit -- Port input data pin 15
IDR14 :: Bit -- Port input data pin 14
IDR13 :: Bit -- Port input data pin 13
IDR12 :: Bit -- Port input data pin 12
IDR11 :: Bit -- Port input data pin 11
IDR10 :: Bit -- Port input data pin 10
IDR9 :: Bit -- Port input data pin 9
IDR8 :: Bit -- Port input data pin 8
IDR7 :: Bit -- Port input data pin 7
IDR6 :: Bit -- Port input data pin 6
IDR5 :: Bit -- Port input data pin 5
IDR4 :: Bit -- Port input data pin 4
IDR3 :: Bit -- Port input data pin 3
IDR2 :: Bit -- Port input data pin 2
IDR1 :: Bit -- Port input data pin 1
IDR0 :: Bit -- Port input data pin 0
ODR 0x14 - GPIO port output data register
_ :: Bits 16 -- (Reserved)
ODR15 :: Bit -- Port output data pin 15
ODR14 :: Bit -- Port output data pin 14
ODR13 :: Bit -- Port output data pin 13
ODR12 :: Bit -- Port output data pin 12
ODR11 :: Bit -- Port output data pin 11
ODR10 :: Bit -- Port output data pin 10
ODR9 :: Bit -- Port output data pin 9
ODR8 :: Bit -- Port output data pin 8
ODR7 :: Bit -- Port output data pin 7
ODR6 :: Bit -- Port output data pin 6
ODR5 :: Bit -- Port output data pin 5
ODR4 :: Bit -- Port output data pin 4
ODR3 :: Bit -- Port output data pin 3
ODR2 :: Bit -- Port output data pin 2
ODR1 :: Bit -- Port output data pin 1
ODR0 :: Bit -- Port output data pin 0
BSRR 0x18 - GPIO port bit set/reset register
BR15 :: Bit -- Port x reset pin 15
BR14 :: Bit -- Port x reset pin 14
BR13 :: Bit -- Port x reset pin 13
BR12 :: Bit -- Port x reset pin 12
BR11 :: Bit -- Port x reset pin 11
BR10 :: Bit -- Port x reset pin 10
BR9 :: Bit -- Port x reset pin 9
BR8 :: Bit -- Port x reset pin 8
BR7 :: Bit -- Port x reset pin 7
BR6 :: Bit -- Port x reset pin 6
BR5 :: Bit -- Port x reset pin 5
BR4 :: Bit -- Port x reset pin 4
BR3 :: Bit -- Port x reset pin 3
BR2 :: Bit -- Port x reset pin 2
BR1 :: Bit -- Port x reset pin 1
BR0 :: Bit -- Port x reset pin 0
BS15 :: Bit -- Port x set pin 15
BS14 :: Bit -- Port x set pin 14
BS13 :: Bit -- Port x set pin 13
BS12 :: Bit -- Port x set pin 12
BS11 :: Bit -- Port x set pin 11
BS10 :: Bit -- Port x set pin 10
BS9 :: Bit -- Port x set pin 9
BS8 :: Bit -- Port x set pin 8
BS7 :: Bit -- Port x set pin 7
BS6 :: Bit -- Port x set pin 6
BS5 :: Bit -- Port x set pin 5
BS4 :: Bit -- Port x set pin 4
BS3 :: Bit -- Port x set pin 3
BS2 :: Bit -- Port x set pin 2
BS1 :: Bit -- Port x set pin 1
BS0 :: Bit -- Port x set pin 0
LCKR 0x1c - GPIO port configuration lock register
_ :: Bits 15 -- (Reserved)
LCKK :: Bit -- Port x lock bit y (y= 0..15)
LCK15 :: Bit -- Port x lock pin 15
LCK14 :: Bit -- Port x lock pin 14
LCK13 :: Bit -- Port x lock pin 13
LCK12 :: Bit -- Port x lock pin 12
LCK11 :: Bit -- Port x lock pin 11
LCK10 :: Bit -- Port x lock pin 10
LCK9 :: Bit -- Port x lock pin 9
LCK8 :: Bit -- Port x lock pin 8
LCK7 :: Bit -- Port x lock pin 7
LCK6 :: Bit -- Port x lock pin 6
LCK5 :: Bit -- Port x lock pin 5
LCK4 :: Bit -- Port x lock pin 4
LCK3 :: Bit -- Port x lock pin 3
LCK2 :: Bit -- Port x lock pin 2
LCK1 :: Bit -- Port x lock pin 1
LCK0 :: Bit -- Port x lock pin 0
AFRL 0x20 - GPIO alternate function low register
AFRL7 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL6 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL5 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL4 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL3 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL2 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL1 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRL0 :: Bits 4 -- Alternate function selection for port x bit y (y = 0..7)
AFRH 0x24 - GPIO alternate function high register
AFRH15 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH14 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH13 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH12 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH11 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH10 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH9 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
AFRH8 :: Bits 4 -- Alternate function selection for port x bit y (y = 8..15)
GPIOJ 0x40022400
Derived from GPIOI
GPIOK 0x40022800
Derived from GPIOI
CRC 0x40023000 Cryptographic processor
DR 0x0 - Data register
DR :: Bits 32 -- Data Register
IDR 0x4 - Independent Data register
_ :: Bits 24 -- (Reserved)
IDR :: Bits 8 -- Independent Data register
CR 0x8 - Control register
_ :: Bits 31 -- (Reserved)
RESET :: Bit -- Control regidter
RCC 0x40023800 Reset and clock control
CR 0x0 - clock control register
_ :: Bits 4 -- (Reserved)
PLLI2SRDY :: Bit -- PLLI2S clock ready flag
PLLI2SON :: Bit -- PLLI2S enable
PLLRDY :: Bit -- Main PLL (PLL) clock ready flag
PLLON :: Bit -- Main PLL (PLL) enable
_ :: Bits 4 -- (Reserved)
CSSON :: Bit -- Clock security system enable
HSEBYP :: Bit -- HSE clock bypass
HSERDY :: Bit -- HSE clock ready flag
HSEON :: Bit -- HSE clock enable
HSICAL :: Bits 8 -- Internal high-speed clock calibration
HSITRIM :: Bits 5 -- Internal high-speed clock trimming
_ :: Bit -- (Reserved)
HSIRDY :: Bit -- Internal high-speed clock ready flag
HSION :: Bit -- Internal high-speed clock enable
PLLCFGR 0x4 - PLL configuration register
_ :: Bits 4 -- (Reserved)
PLLQ :: Bits 4 -- Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
_ :: Bit -- (Reserved)
PLLSRC :: Bit -- Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
_ :: Bits 4 -- (Reserved)
PLLP :: Bits 2 -- Main PLL (PLL) division factor for main system clock
_ :: Bit -- (Reserved)
PLLN :: Bits 9 -- Main PLL (PLL) multiplication factor for VCO
PLLM :: Bits 6 -- Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
CFGR 0x8 - clock configuration register
MCO2 :: Bits 2 -- Microcontroller clock output 2
MCO2PRE :: Bits 3 -- MCO2 prescaler
MCO1PRE :: Bits 3 -- MCO1 prescaler
I2SSRC :: Bit -- I2S clock selection
MCO1 :: Bits 2 -- Microcontroller clock output 1
RTCPRE :: Bits 5 -- HSE division factor for RTC clock
PPRE2 :: Bits 3 -- APB high-speed prescaler (APB2)
PPRE1 :: Bits 3 -- APB Low speed prescaler (APB1)
_ :: Bits 2 -- (Reserved)
HPRE :: Bits 4 -- AHB prescaler
SWS :: Bits 2 -- System clock switch status
SW :: Bits 2 -- System clock switch
CIR 0xc - clock interrupt register
_ :: Bits 8 -- (Reserved)
CSSC :: Bit -- Clock security system interrupt clear
_ :: Bit -- (Reserved)
PLLI2SRDYC :: Bit -- PLLI2S ready interrupt clear
PLLRDYC :: Bit -- Main PLL(PLL) ready interrupt clear
HSERDYC :: Bit -- HSE ready interrupt clear
HSIRDYC :: Bit -- HSI ready interrupt clear
LSERDYC :: Bit -- LSE ready interrupt clear
LSIRDYC :: Bit -- LSI ready interrupt clear
_ :: Bits 2 -- (Reserved)
PLLI2SRDYIE :: Bit -- PLLI2S ready interrupt enable
PLLRDYIE :: Bit -- Main PLL (PLL) ready interrupt enable
HSERDYIE :: Bit -- HSE ready interrupt enable
HSIRDYIE :: Bit -- HSI ready interrupt enable
LSERDYIE :: Bit -- LSE ready interrupt enable
LSIRDYIE :: Bit -- LSI ready interrupt enable
CSSF :: Bit -- Clock security system interrupt flag
_ :: Bit -- (Reserved)
PLLI2SRDYF :: Bit -- PLLI2S ready interrupt flag
PLLRDYF :: Bit -- Main PLL (PLL) ready interrupt flag
HSERDYF :: Bit -- HSE ready interrupt flag
HSIRDYF :: Bit -- HSI ready interrupt flag
LSERDYF :: Bit -- LSE ready interrupt flag
LSIRDYF :: Bit -- LSI ready interrupt flag
AHB1RSTR 0x10 - AHB1 peripheral reset register
_ :: Bits 2 -- (Reserved)
OTGHSRST :: Bit -- USB OTG HS module reset
_ :: Bits 6 -- (Reserved)
DMA2RST :: Bit -- DMA2 reset
DMA1RST :: Bit -- DMA2 reset
_ :: Bits 8 -- (Reserved)
CRCRST :: Bit -- CRC reset
_ :: Bits 3 -- (Reserved)
GPIOIRST :: Bit -- IO port I reset
GPIOHRST :: Bit -- IO port H reset
GPIOGRST :: Bit -- IO port G reset
GPIOFRST :: Bit -- IO port F reset
GPIOERST :: Bit -- IO port E reset
GPIODRST :: Bit -- IO port D reset
GPIOCRST :: Bit -- IO port C reset
GPIOBRST :: Bit -- IO port B reset
GPIOARST :: Bit -- IO port A reset
AHB2RSTR 0x14 - AHB2 peripheral reset register
_ :: Bits 24 -- (Reserved)
OTGFSRST :: Bit -- USB OTG FS module reset
RNGRST :: Bit -- Random number generator module reset
_ :: Bits 5 -- (Reserved)
DCMIRST :: Bit -- Camera interface reset
AHB3RSTR 0x18 - AHB3 peripheral reset register
_ :: Bits 31 -- (Reserved)
FSMCRST :: Bit -- Flexible static memory controller module reset
APB1RSTR 0x20 - APB1 peripheral reset register
_ :: Bits 2 -- (Reserved)
DACRST :: Bit -- DAC reset
PWRRST :: Bit -- Power interface reset
_ :: Bit -- (Reserved)
CAN2RST :: Bit -- CAN2 reset
CAN1RST :: Bit -- CAN1 reset
_ :: Bit -- (Reserved)
I2C3RST :: Bit -- I2C3 reset
I2C2RST :: Bit -- I2C 2 reset
I2C1RST :: Bit -- I2C 1 reset
UART5RST :: Bit -- USART 5 reset
UART4RST :: Bit -- USART 4 reset
USART3RST :: Bit -- USART 3 reset
USART2RST :: Bit -- USART 2 reset
_ :: Bit -- (Reserved)
SPI3RST :: Bit -- SPI 3 reset
SPI2RST :: Bit -- SPI 2 reset
_ :: Bits 2 -- (Reserved)
WWDGRST :: Bit -- Window watchdog reset
_ :: Bits 2 -- (Reserved)
TIM14RST :: Bit -- TIM14 reset
TIM13RST :: Bit -- TIM13 reset
TIM12RST :: Bit -- TIM12 reset
TIM7RST :: Bit -- TIM7 reset
TIM6RST :: Bit -- TIM6 reset
TIM5RST :: Bit -- TIM5 reset
TIM4RST :: Bit -- TIM4 reset
TIM3RST :: Bit -- TIM3 reset
TIM2RST :: Bit -- TIM2 reset
APB2RSTR 0x24 - APB2 peripheral reset register
_ :: Bits 13 -- (Reserved)
TIM11RST :: Bit -- TIM11 reset
TIM10RST :: Bit -- TIM10 reset
TIM9RST :: Bit -- TIM9 reset
_ :: Bit -- (Reserved)
SYSCFGRST :: Bit -- System configuration controller reset
_ :: Bit -- (Reserved)
SPI1RST :: Bit -- SPI 1 reset
SDIORST :: Bit -- SDIO reset
_ :: Bits 2 -- (Reserved)
ADCRST :: Bit -- ADC interface reset (common to all ADCs)
_ :: Bits 2 -- (Reserved)
USART6RST :: Bit -- USART6 reset
USART1RST :: Bit -- USART1 reset
_ :: Bits 2 -- (Reserved)
TIM8RST :: Bit -- TIM8 reset
TIM1RST :: Bit -- TIM1 reset
AHB1ENR 0x30 - AHB1 peripheral clock register
_ :: Bit -- (Reserved)
OTGHSULPIEN :: Bit -- USB OTG HSULPI clock enable
OTGHSEN :: Bit -- USB OTG HS clock enable
_ :: Bits 6 -- (Reserved)
DMA2EN :: Bit -- DMA2 clock enable
DMA1EN :: Bit -- DMA1 clock enable
_ :: Bits 2 -- (Reserved)
BKPSRAMEN :: Bit -- Backup SRAM interface clock enable
_ :: Bits 5 -- (Reserved)
CRCEN :: Bit -- CRC clock enable
_ :: Bits 3 -- (Reserved)
GPIOIEN :: Bit -- IO port I clock enable
GPIOHEN :: Bit -- IO port H clock enable
GPIOGEN :: Bit -- IO port G clock enable
GPIOFEN :: Bit -- IO port F clock enable
GPIOEEN :: Bit -- IO port E clock enable
GPIODEN :: Bit -- IO port D clock enable
GPIOCEN :: Bit -- IO port C clock enable
GPIOBEN :: Bit -- IO port B clock enable
GPIOAEN :: Bit -- IO port A clock enable
AHB2ENR 0x34 - AHB2 peripheral clock enable register
_ :: Bits 24 -- (Reserved)
OTGFSEN :: Bit -- USB OTG FS clock enable
RNGEN :: Bit -- Random number generator clock enable
_ :: Bits 5 -- (Reserved)
DCMIEN :: Bit -- Camera interface enable
AHB3ENR 0x38 - AHB3 peripheral clock enable register
_ :: Bits 31 -- (Reserved)
FSMCEN :: Bit -- Flexible static memory controller module clock enable
APB1ENR 0x40 - APB1 peripheral clock enable register
_ :: Bits 2 -- (Reserved)
DACEN :: Bit -- DAC interface clock enable
PWREN :: Bit -- Power interface clock enable
_ :: Bit -- (Reserved)
CAN2EN :: Bit -- CAN 2 clock enable
CAN1EN :: Bit -- CAN 1 clock enable
_ :: Bit -- (Reserved)
I2C3EN :: Bit -- I2C3 clock enable
I2C2EN :: Bit -- I2C2 clock enable
I2C1EN :: Bit -- I2C1 clock enable
UART5EN :: Bit -- UART5 clock enable
UART4EN :: Bit -- UART4 clock enable
USART3EN :: Bit -- USART3 clock enable
USART2EN :: Bit -- USART 2 clock enable
_ :: Bit -- (Reserved)
SPI3EN :: Bit -- SPI3 clock enable
SPI2EN :: Bit -- SPI2 clock enable
_ :: Bits 2 -- (Reserved)
WWDGEN :: Bit -- Window watchdog clock enable
_ :: Bits 2 -- (Reserved)
TIM14EN :: Bit -- TIM14 clock enable
TIM13EN :: Bit -- TIM13 clock enable
TIM12EN :: Bit -- TIM12 clock enable
TIM7EN :: Bit -- TIM7 clock enable
TIM6EN :: Bit -- TIM6 clock enable
TIM5EN :: Bit -- TIM5 clock enable
TIM4EN :: Bit -- TIM4 clock enable
TIM3EN :: Bit -- TIM3 clock enable
TIM2EN :: Bit -- TIM2 clock enable
APB2ENR 0x44 - APB2 peripheral clock enable register
_ :: Bits 13 -- (Reserved)
TIM11EN :: Bit -- TIM11 clock enable
TIM10EN :: Bit -- TIM10 clock enable
TIM9EN :: Bit -- TIM9 clock enable
_ :: Bit -- (Reserved)
SYSCFGEN :: Bit -- System configuration controller clock enable
_ :: Bit -- (Reserved)
SPI1EN :: Bit -- SPI1 clock enable
SDIOEN :: Bit -- SDIO clock enable
ADC3EN :: Bit -- ADC3 clock enable
ADC2EN :: Bit -- ADC2 clock enable
ADC1EN :: Bit -- ADC1 clock enable
_ :: Bits 2 -- (Reserved)
USART6EN :: Bit -- USART6 clock enable
USART1EN :: Bit -- USART1 clock enable
_ :: Bits 2 -- (Reserved)
TIM8EN :: Bit -- TIM8 clock enable
TIM1EN :: Bit -- TIM1 clock enable
AHB1LPENR 0x50 - AHB1 peripheral clock enable in low power mode register
_ :: Bit -- (Reserved)
OTGHSULPILPEN :: Bit -- USB OTG HS ULPI clock enable during Sleep mode
OTGHSLPEN :: Bit -- USB OTG HS clock enable during Sleep mode
_ :: Bits 6 -- (Reserved)
DMA2LPEN :: Bit -- DMA2 clock enable during Sleep mode
DMA1LPEN :: Bit -- DMA1 clock enable during Sleep mode
_ :: Bits 2 -- (Reserved)
BKPSRAMLPEN :: Bit -- Backup SRAM interface clock enable during Sleep mode
SRAM2LPEN :: Bit -- SRAM 2 interface clock enable during Sleep mode
SRAM1LPEN :: Bit -- SRAM 1interface clock enable during Sleep mode
FLITFLPEN :: Bit -- Flash interface clock enable during Sleep mode
_ :: Bits 2 -- (Reserved)
CRCLPEN :: Bit -- CRC clock enable during Sleep mode
_ :: Bits 3 -- (Reserved)
GPIOILPEN :: Bit -- IO port I clock enable during Sleep mode
GPIOHLPEN :: Bit -- IO port H clock enable during Sleep mode
GPIOGLPEN :: Bit -- IO port G clock enable during Sleep mode
GPIOFLPEN :: Bit -- IO port F clock enable during Sleep mode
GPIOELPEN :: Bit -- IO port E clock enable during Sleep mode
GPIODLPEN :: Bit -- IO port D clock enable during Sleep mode
GPIOCLPEN :: Bit -- IO port C clock enable during Sleep mode
GPIOBLPEN :: Bit -- IO port B clock enable during Sleep mode
GPIOALPEN :: Bit -- IO port A clock enable during sleep mode
AHB2LPENR 0x54 - AHB2 peripheral clock enable in low power mode register
_ :: Bits 24 -- (Reserved)
OTGFSLPEN :: Bit -- USB OTG FS clock enable during Sleep mode
RNGLPEN :: Bit -- Random number generator clock enable during Sleep mode
_ :: Bits 5 -- (Reserved)
DCMILPEN :: Bit -- Camera interface enable during Sleep mode
AHB3LPENR 0x58 - AHB3 peripheral clock enable in low power mode register
_ :: Bits 31 -- (Reserved)
FSMCLPEN :: Bit -- Flexible static memory controller module clock enable during Sleep mode
APB1LPENR 0x60 - APB1 peripheral clock enable in low power mode register
_ :: Bits 2 -- (Reserved)
DACLPEN :: Bit -- DAC interface clock enable during Sleep mode
PWRLPEN :: Bit -- Power interface clock enable during Sleep mode
_ :: Bit -- (Reserved)
CAN2LPEN :: Bit -- CAN 2 clock enable during Sleep mode
CAN1LPEN :: Bit -- CAN 1 clock enable during Sleep mode
_ :: Bit -- (Reserved)
I2C3LPEN :: Bit -- I2C3 clock enable during Sleep mode
I2C2LPEN :: Bit -- I2C2 clock enable during Sleep mode
I2C1LPEN :: Bit -- I2C1 clock enable during Sleep mode
UART5LPEN :: Bit -- UART5 clock enable during Sleep mode
UART4LPEN :: Bit -- UART4 clock enable during Sleep mode
USART3LPEN :: Bit -- USART3 clock enable during Sleep mode
USART2LPEN :: Bit -- USART2 clock enable during Sleep mode
_ :: Bit -- (Reserved)
SPI3LPEN :: Bit -- SPI3 clock enable during Sleep mode
SPI2LPEN :: Bit -- SPI2 clock enable during Sleep mode
_ :: Bits 2 -- (Reserved)
WWDGLPEN :: Bit -- Window watchdog clock enable during Sleep mode
_ :: Bits 2 -- (Reserved)
TIM14LPEN :: Bit -- TIM14 clock enable during Sleep mode
TIM13LPEN :: Bit -- TIM13 clock enable during Sleep mode
TIM12LPEN :: Bit -- TIM12 clock enable during Sleep mode
TIM7LPEN :: Bit -- TIM7 clock enable during Sleep mode
TIM6LPEN :: Bit -- TIM6 clock enable during Sleep mode
TIM5LPEN :: Bit -- TIM5 clock enable during Sleep mode
TIM4LPEN :: Bit -- TIM4 clock enable during Sleep mode
TIM3LPEN :: Bit -- TIM3 clock enable during Sleep mode
TIM2LPEN :: Bit -- TIM2 clock enable during Sleep mode
APB2LPENR 0x64 - APB2 peripheral clock enabled in low power mode register
_ :: Bits 13 -- (Reserved)
TIM11LPEN :: Bit -- TIM11 clock enable during Sleep mode
TIM10LPEN :: Bit -- TIM10 clock enable during Sleep mode
TIM9LPEN :: Bit -- TIM9 clock enable during sleep mode
_ :: Bit -- (Reserved)
SYSCFGLPEN :: Bit -- System configuration controller clock enable during Sleep mode
_ :: Bit -- (Reserved)
SPI1LPEN :: Bit -- SPI 1 clock enable during Sleep mode
SDIOLPEN :: Bit -- SDIO clock enable during Sleep mode
ADC3LPEN :: Bit -- ADC 3 clock enable during Sleep mode
ADC2LPEN :: Bit -- ADC2 clock enable during Sleep mode
ADC1LPEN :: Bit -- ADC1 clock enable during Sleep mode
_ :: Bits 2 -- (Reserved)
USART6LPEN :: Bit -- USART6 clock enable during Sleep mode
USART1LPEN :: Bit -- USART1 clock enable during Sleep mode
_ :: Bits 2 -- (Reserved)
TIM8LPEN :: Bit -- TIM8 clock enable during Sleep mode
TIM1LPEN :: Bit -- TIM1 clock enable during Sleep mode
BDCR 0x70 - Backup domain control register
_ :: Bits 15 -- (Reserved)
BDRST :: Bit -- Backup domain software reset
RTCEN :: Bit -- RTC clock enable
_ :: Bits 5 -- (Reserved)
RTCSEL :: Bits 2 -- RTC clock source selection
_ :: Bits 5 -- (Reserved)
LSEBYP :: Bit -- External low-speed oscillator bypass
LSERDY :: Bit -- External low-speed oscillator ready
LSEON :: Bit -- External low-speed oscillator enable
CSR 0x74 - clock control & status register
LPWRRSTF :: Bit -- Low-power reset flag
WWDGRSTF :: Bit -- Window watchdog reset flag
WDGRSTF :: Bit -- Independent watchdog reset flag
SFTRSTF :: Bit -- Software reset flag
PORRSTF :: Bit -- POR/PDR reset flag
PADRSTF :: Bit -- PIN reset flag
BORRSTF :: Bit -- BOR reset flag
RMVF :: Bit -- Remove reset flag
_ :: Bits 22 -- (Reserved)
LSIRDY :: Bit -- Internal low-speed oscillator ready
LSION :: Bit -- Internal low-speed oscillator enable
SSCGR 0x80 - spread spectrum clock generation register
SSCGEN :: Bit -- Spread spectrum modulation enable
SPREADSEL :: Bit -- Spread Select
_ :: Bits 2 -- (Reserved)
INCSTEP :: Bits 15 -- Incrementation step
MODPER :: Bits 13 -- Modulation period
PLLI2SCFGR 0x84 - PLLI2S configuration register
_ :: Bit -- (Reserved)
PLLI2SR :: Bits 3 -- PLLI2S division factor for I2S clocks
_ :: Bits 13 -- (Reserved)
PLLI2SN :: Bits 9 -- PLLI2S multiplication factor for VCO
_ :: Bits 6 -- (Reserved)
FLASH 0x40023c00 FLASH
ACR 0x0 - Flash access control register
_ :: Bits 19 -- (Reserved)
DCRST :: Bit -- Data cache reset
ICRST :: Bit -- Instruction cache reset
DCEN :: Bit -- Data cache enable
ICEN :: Bit -- Instruction cache enable
PRFTEN :: Bit -- Prefetch enable
_ :: Bits 5 -- (Reserved)
LATENCY :: Bits 3 -- Latency
KEYR 0x4 - Flash key register
KEY :: Bits 32 -- FPEC key
OPTKEYR 0x8 - Flash option key register
OPTKEY :: Bits 32 -- Option byte key
SR 0xc - Status register
_ :: Bits 15 -- (Reserved)
BSY :: Bit -- Busy
_ :: Bits 8 -- (Reserved)
PGSERR :: Bit -- Programming sequence error
PGPERR :: Bit -- Programming parallelism error
PGAERR :: Bit -- Programming alignment error
WRPERR :: Bit -- Write protection error
_ :: Bits 2 -- (Reserved)
OPERR :: Bit -- Operation error
EOP :: Bit -- End of operation
CR 0x10 - Control register
LOCK :: Bit -- Lock
_ :: Bits 5 -- (Reserved)
ERRIE :: Bit -- Error interrupt enable
EOPIE :: Bit -- End of operation interrupt enable
_ :: Bits 7 -- (Reserved)
STRT :: Bit -- Start
_ :: Bits 6 -- (Reserved)
PSIZE :: Bits 2 -- Program size
_ :: Bit -- (Reserved)
SNB :: Bits 4 -- Sector number
MER :: Bit -- Mass Erase
SER :: Bit -- Sector Erase
PG :: Bit -- Programming
OPTCR 0x14 - Flash option control register
_ :: Bits 4 -- (Reserved)
nWRP :: Bits 12 -- Not write protect
RDP :: Bits 8 -- Read protect
nRST_STDBY :: Bit -- nRST_STDBY User option bytes
nRST_STOP :: Bit -- nRST_STOP User option bytes
WDG_SW :: Bit -- WDG_SW User option bytes
_ :: Bit -- (Reserved)
BOR_LEV :: Bits 2 -- BOR reset Level
OPTSTRT :: Bit -- Option start
OPTLOCK :: Bit -- Option lock
DMA1 0x40026000
Derived from DMA2
DMA2 0x40026400 DMA controller
LISR 0x0 - low interrupt status register
_ :: Bits 4 -- (Reserved)
TCIF3 :: Bit -- Stream x transfer complete interrupt flag (x = 3..0)
HTIF3 :: Bit -- Stream x half transfer interrupt flag (x=3..0)
TEIF3 :: Bit -- Stream x transfer error interrupt flag (x=3..0)
DMEIF3 :: Bit -- Stream x direct mode error interrupt flag (x=3..0)
_ :: Bit -- (Reserved)
FEIF3 :: Bit -- Stream x FIFO error interrupt flag (x=3..0)
TCIF2 :: Bit -- Stream x transfer complete interrupt flag (x = 3..0)
HTIF2 :: Bit -- Stream x half transfer interrupt flag (x=3..0)
TEIF2 :: Bit -- Stream x transfer error interrupt flag (x=3..0)
DMEIF2 :: Bit -- Stream x direct mode error interrupt flag (x=3..0)
_ :: Bit -- (Reserved)
FEIF2 :: Bit -- Stream x FIFO error interrupt flag (x=3..0)
_ :: Bits 4 -- (Reserved)
TCIF1 :: Bit -- Stream x transfer complete interrupt flag (x = 3..0)
HTIF1 :: Bit -- Stream x half transfer interrupt flag (x=3..0)
TEIF1 :: Bit -- Stream x transfer error interrupt flag (x=3..0)
DMEIF1 :: Bit -- Stream x direct mode error interrupt flag (x=3..0)
_ :: Bit -- (Reserved)
FEIF1 :: Bit -- Stream x FIFO error interrupt flag (x=3..0)
TCIF0 :: Bit -- Stream x transfer complete interrupt flag (x = 3..0)
HTIF0 :: Bit -- Stream x half transfer interrupt flag (x=3..0)
TEIF0 :: Bit -- Stream x transfer error interrupt flag (x=3..0)
DMEIF0 :: Bit -- Stream x direct mode error interrupt flag (x=3..0)
_ :: Bit -- (Reserved)
FEIF0 :: Bit -- Stream x FIFO error interrupt flag (x=3..0)
HISR 0x4 - high interrupt status register
_ :: Bits 4 -- (Reserved)
TCIF7 :: Bit -- Stream x transfer complete interrupt flag (x=7..4)
HTIF7 :: Bit -- Stream x half transfer interrupt flag (x=7..4)
TEIF7 :: Bit -- Stream x transfer error interrupt flag (x=7..4)
DMEIF7 :: Bit -- Stream x direct mode error interrupt flag (x=7..4)
_ :: Bit -- (Reserved)
FEIF7 :: Bit -- Stream x FIFO error interrupt flag (x=7..4)
TCIF6 :: Bit -- Stream x transfer complete interrupt flag (x=7..4)
HTIF6 :: Bit -- Stream x half transfer interrupt flag (x=7..4)
TEIF6 :: Bit -- Stream x transfer error interrupt flag (x=7..4)
DMEIF6 :: Bit -- Stream x direct mode error interrupt flag (x=7..4)
_ :: Bit -- (Reserved)
FEIF6 :: Bit -- Stream x FIFO error interrupt flag (x=7..4)
_ :: Bits 4 -- (Reserved)
TCIF5 :: Bit -- Stream x transfer complete interrupt flag (x=7..4)
HTIF5 :: Bit -- Stream x half transfer interrupt flag (x=7..4)
TEIF5 :: Bit -- Stream x transfer error interrupt flag (x=7..4)
DMEIF5 :: Bit -- Stream x direct mode error interrupt flag (x=7..4)
_ :: Bit -- (Reserved)
FEIF5 :: Bit -- Stream x FIFO error interrupt flag (x=7..4)
TCIF4 :: Bit -- Stream x transfer complete interrupt flag (x=7..4)
HTIF4 :: Bit -- Stream x half transfer interrupt flag (x=7..4)
TEIF4 :: Bit -- Stream x transfer error interrupt flag (x=7..4)
DMEIF4 :: Bit -- Stream x direct mode error interrupt flag (x=7..4)
_ :: Bit -- (Reserved)
FEIF4 :: Bit -- Stream x FIFO error interrupt flag (x=7..4)
LIFCR 0x8 - low interrupt flag clear register
_ :: Bits 4 -- (Reserved)
CTCIF3 :: Bit -- Stream x clear transfer complete interrupt flag (x = 3..0)
CHTIF3 :: Bit -- Stream x clear half transfer interrupt flag (x = 3..0)
CTEIF3 :: Bit -- Stream x clear transfer error interrupt flag (x = 3..0)
CDMEIF3 :: Bit -- Stream x clear direct mode error interrupt flag (x = 3..0)
_ :: Bit -- (Reserved)
CFEIF3 :: Bit -- Stream x clear FIFO error interrupt flag (x = 3..0)
CTCIF2 :: Bit -- Stream x clear transfer complete interrupt flag (x = 3..0)
CHTIF2 :: Bit -- Stream x clear half transfer interrupt flag (x = 3..0)
CTEIF2 :: Bit -- Stream x clear transfer error interrupt flag (x = 3..0)
CDMEIF2 :: Bit -- Stream x clear direct mode error interrupt flag (x = 3..0)
_ :: Bit -- (Reserved)
CFEIF2 :: Bit -- Stream x clear FIFO error interrupt flag (x = 3..0)
_ :: Bits 4 -- (Reserved)
CTCIF1 :: Bit -- Stream x clear transfer complete interrupt flag (x = 3..0)
CHTIF1 :: Bit -- Stream x clear half transfer interrupt flag (x = 3..0)
CTEIF1 :: Bit -- Stream x clear transfer error interrupt flag (x = 3..0)
CDMEIF1 :: Bit -- Stream x clear direct mode error interrupt flag (x = 3..0)
_ :: Bit -- (Reserved)
CFEIF1 :: Bit -- Stream x clear FIFO error interrupt flag (x = 3..0)
CTCIF0 :: Bit -- Stream x clear transfer complete interrupt flag (x = 3..0)
CHTIF0 :: Bit -- Stream x clear half transfer interrupt flag (x = 3..0)
CTEIF0 :: Bit -- Stream x clear transfer error interrupt flag (x = 3..0)
CDMEIF0 :: Bit -- Stream x clear direct mode error interrupt flag (x = 3..0)
_ :: Bit -- (Reserved)
CFEIF0 :: Bit -- Stream x clear FIFO error interrupt flag (x = 3..0)
HIFCR 0xc - high interrupt flag clear register
_ :: Bits 4 -- (Reserved)
CTCIF7 :: Bit -- Stream x clear transfer complete interrupt flag (x = 7..4)
CHTIF7 :: Bit -- Stream x clear half transfer interrupt flag (x = 7..4)
CTEIF7 :: Bit -- Stream x clear transfer error interrupt flag (x = 7..4)
CDMEIF7 :: Bit -- Stream x clear direct mode error interrupt flag (x = 7..4)
_ :: Bit -- (Reserved)
CFEIF7 :: Bit -- Stream x clear FIFO error interrupt flag (x = 7..4)
CTCIF6 :: Bit -- Stream x clear transfer complete interrupt flag (x = 7..4)
CHTIF6 :: Bit -- Stream x clear half transfer interrupt flag (x = 7..4)
CTEIF6 :: Bit -- Stream x clear transfer error interrupt flag (x = 7..4)
CDMEIF6 :: Bit -- Stream x clear direct mode error interrupt flag (x = 7..4)
_ :: Bit -- (Reserved)
CFEIF6 :: Bit -- Stream x clear FIFO error interrupt flag (x = 7..4)
_ :: Bits 4 -- (Reserved)
CTCIF5 :: Bit -- Stream x clear transfer complete interrupt flag (x = 7..4)
CHTIF5 :: Bit -- Stream x clear half transfer interrupt flag (x = 7..4)
CTEIF5 :: Bit -- Stream x clear transfer error interrupt flag (x = 7..4)
CDMEIF5 :: Bit -- Stream x clear direct mode error interrupt flag (x = 7..4)
_ :: Bit -- (Reserved)
CFEIF5 :: Bit -- Stream x clear FIFO error interrupt flag (x = 7..4)
CTCIF4 :: Bit -- Stream x clear transfer complete interrupt flag (x = 7..4)
CHTIF4 :: Bit -- Stream x clear half transfer interrupt flag (x = 7..4)
CTEIF4 :: Bit -- Stream x clear transfer error interrupt flag (x = 7..4)
CDMEIF4 :: Bit -- Stream x clear direct mode error interrupt flag (x = 7..4)
_ :: Bit -- (Reserved)
CFEIF4 :: Bit -- Stream x clear FIFO error interrupt flag (x = 7..4)
CR 0x10 - stream x configuration register
_ :: Bits 4 -- (Reserved)
CHSEL :: Bits 3 -- Channel selection
MBURST :: Bits 2 -- Memory burst transfer configuration
PBURST :: Bits 2 -- Peripheral burst transfer configuration
_ :: Bit -- (Reserved)
CT :: Bit -- Current target (only in double buffer mode)
DBM :: Bit -- Double buffer mode
PL :: Bits 2 -- Priority level
PINCOS :: Bit -- Peripheral increment offset size
MSIZE :: Bits 2 -- Memory data size
PSIZE :: Bits 2 -- Peripheral data size
MINC :: Bit -- Memory increment mode
PINC :: Bit -- Peripheral increment mode
CIRC :: Bit -- Circular mode
DIR :: Bits 2 -- Data transfer direction
PFCTRL :: Bit -- Peripheral flow controller
TCIE :: Bit -- Transfer complete interrupt enable
HTIE :: Bit -- Half transfer interrupt enable
TEIE :: Bit -- Transfer error interrupt enable
DMEIE :: Bit -- Direct mode error interrupt enable
EN :: Bit -- Stream enable / flag stream ready when read low
NDTR 0x14 - stream x number of data register
_ :: Bits 16 -- (Reserved)
NDT :: Bits 16 -- Number of data items to transfer
PAR 0x18 - stream x peripheral address register
PA :: Bits 32 -- Peripheral address
M0AR 0x1c - stream x memory 0 address register
M0A :: Bits 32 -- Memory 0 address
M1AR 0x20 - stream x memory 1 address register
M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode)
FCR 0x24 - stream x FIFO control register
_ :: Bits 24 -- (Reserved)
FEIE :: Bit -- FIFO error interrupt enable
_ :: Bit -- (Reserved)
FS :: Bits 3 -- FIFO status
DMDIS :: Bit -- Direct mode disable
FTH :: Bits 2 -- FIFO threshold selection
CR 0x28 - stream x configuration register
_ :: Bits 4 -- (Reserved)
CHSEL :: Bits 3 -- Channel selection
MBURST :: Bits 2 -- Memory burst transfer configuration
PBURST :: Bits 2 -- Peripheral burst transfer configuration
_ :: Bit -- (Reserved)
CT :: Bit -- Current target (only in double buffer mode)
DBM :: Bit -- Double buffer mode
PL :: Bits 2 -- Priority level
PINCOS :: Bit -- Peripheral increment offset size
MSIZE :: Bits 2 -- Memory data size
PSIZE :: Bits 2 -- Peripheral data size
MINC :: Bit -- Memory increment mode
PINC :: Bit -- Peripheral increment mode
CIRC :: Bit -- Circular mode
DIR :: Bits 2 -- Data transfer direction
PFCTRL :: Bit -- Peripheral flow controller
TCIE :: Bit -- Transfer complete interrupt enable
HTIE :: Bit -- Half transfer interrupt enable
TEIE :: Bit -- Transfer error interrupt enable
DMEIE :: Bit -- Direct mode error interrupt enable
EN :: Bit -- Stream enable / flag stream ready when read low
NDTR 0x2c - stream x number of data register
_ :: Bits 16 -- (Reserved)
NDT :: Bits 16 -- Number of data items to transfer
PAR 0x30 - stream x peripheral address register
PA :: Bits 32 -- Peripheral address
M0AR 0x34 - stream x memory 0 address register
M0A :: Bits 32 -- Memory 0 address
M1AR 0x38 - stream x memory 1 address register
M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode)
FCR 0x3c - stream x FIFO control register
_ :: Bits 24 -- (Reserved)
FEIE :: Bit -- FIFO error interrupt enable
_ :: Bit -- (Reserved)
FS :: Bits 3 -- FIFO status
DMDIS :: Bit -- Direct mode disable
FTH :: Bits 2 -- FIFO threshold selection
CR 0x40 - stream x configuration register
_ :: Bits 4 -- (Reserved)
CHSEL :: Bits 3 -- Channel selection
MBURST :: Bits 2 -- Memory burst transfer configuration
PBURST :: Bits 2 -- Peripheral burst transfer configuration
_ :: Bit -- (Reserved)
CT :: Bit -- Current target (only in double buffer mode)
DBM :: Bit -- Double buffer mode
PL :: Bits 2 -- Priority level
PINCOS :: Bit -- Peripheral increment offset size
MSIZE :: Bits 2 -- Memory data size
PSIZE :: Bits 2 -- Peripheral data size
MINC :: Bit -- Memory increment mode
PINC :: Bit -- Peripheral increment mode
CIRC :: Bit -- Circular mode
DIR :: Bits 2 -- Data transfer direction
PFCTRL :: Bit -- Peripheral flow controller
TCIE :: Bit -- Transfer complete interrupt enable
HTIE :: Bit -- Half transfer interrupt enable
TEIE :: Bit -- Transfer error interrupt enable
DMEIE :: Bit -- Direct mode error interrupt enable
EN :: Bit -- Stream enable / flag stream ready when read low
NDTR 0x44 - stream x number of data register
_ :: Bits 16 -- (Reserved)
NDT :: Bits 16 -- Number of data items to transfer
PAR 0x48 - stream x peripheral address register
PA :: Bits 32 -- Peripheral address
M0AR 0x4c - stream x memory 0 address register
M0A :: Bits 32 -- Memory 0 address
M1AR 0x50 - stream x memory 1 address register
M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode)
FCR 0x54 - stream x FIFO control register
_ :: Bits 24 -- (Reserved)
FEIE :: Bit -- FIFO error interrupt enable
_ :: Bit -- (Reserved)
FS :: Bits 3 -- FIFO status
DMDIS :: Bit -- Direct mode disable
FTH :: Bits 2 -- FIFO threshold selection
CR 0x58 - stream x configuration register
_ :: Bits 4 -- (Reserved)
CHSEL :: Bits 3 -- Channel selection
MBURST :: Bits 2 -- Memory burst transfer configuration
PBURST :: Bits 2 -- Peripheral burst transfer configuration
_ :: Bit -- (Reserved)
CT :: Bit -- Current target (only in double buffer mode)
DBM :: Bit -- Double buffer mode
PL :: Bits 2 -- Priority level
PINCOS :: Bit -- Peripheral increment offset size
MSIZE :: Bits 2 -- Memory data size
PSIZE :: Bits 2 -- Peripheral data size
MINC :: Bit -- Memory increment mode
PINC :: Bit -- Peripheral increment mode
CIRC :: Bit -- Circular mode
DIR :: Bits 2 -- Data transfer direction
PFCTRL :: Bit -- Peripheral flow controller
TCIE :: Bit -- Transfer complete interrupt enable
HTIE :: Bit -- Half transfer interrupt enable
TEIE :: Bit -- Transfer error interrupt enable
DMEIE :: Bit -- Direct mode error interrupt enable
EN :: Bit -- Stream enable / flag stream ready when read low
NDTR 0x5c - stream x number of data register
_ :: Bits 16 -- (Reserved)
NDT :: Bits 16 -- Number of data items to transfer
PAR 0x60 - stream x peripheral address register
PA :: Bits 32 -- Peripheral address
M0AR 0x64 - stream x memory 0 address register
M0A :: Bits 32 -- Memory 0 address
M1AR 0x68 - stream x memory 1 address register
M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode)
FCR 0x6c - stream x FIFO control register
_ :: Bits 24 -- (Reserved)
FEIE :: Bit -- FIFO error interrupt enable
_ :: Bit -- (Reserved)
FS :: Bits 3 -- FIFO status
DMDIS :: Bit -- Direct mode disable
FTH :: Bits 2 -- FIFO threshold selection
CR 0x70 - stream x configuration register
_ :: Bits 4 -- (Reserved)
CHSEL :: Bits 3 -- Channel selection
MBURST :: Bits 2 -- Memory burst transfer configuration
PBURST :: Bits 2 -- Peripheral burst transfer configuration
_ :: Bit -- (Reserved)
CT :: Bit -- Current target (only in double buffer mode)
DBM :: Bit -- Double buffer mode
PL :: Bits 2 -- Priority level
PINCOS :: Bit -- Peripheral increment offset size
MSIZE :: Bits 2 -- Memory data size
PSIZE :: Bits 2 -- Peripheral data size
MINC :: Bit -- Memory increment mode
PINC :: Bit -- Peripheral increment mode
CIRC :: Bit -- Circular mode
DIR :: Bits 2 -- Data transfer direction
PFCTRL :: Bit -- Peripheral flow controller
TCIE :: Bit -- Transfer complete interrupt enable
HTIE :: Bit -- Half transfer interrupt enable
TEIE :: Bit -- Transfer error interrupt enable
DMEIE :: Bit -- Direct mode error interrupt enable
EN :: Bit -- Stream enable / flag stream ready when read low
NDTR 0x74 - stream x number of data register
_ :: Bits 16 -- (Reserved)
NDT :: Bits 16 -- Number of data items to transfer
PAR 0x78 - stream x peripheral address register
PA :: Bits 32 -- Peripheral address
M0AR 0x7c - stream x memory 0 address register
M0A :: Bits 32 -- Memory 0 address
M1AR 0x80 - stream x memory 1 address register
M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode)
FCR 0x84 - stream x FIFO control register
_ :: Bits 24 -- (Reserved)
FEIE :: Bit -- FIFO error interrupt enable
_ :: Bit -- (Reserved)
FS :: Bits 3 -- FIFO status
DMDIS :: Bit -- Direct mode disable
FTH :: Bits 2 -- FIFO threshold selection
CR 0x88 - stream x configuration register
_ :: Bits 4 -- (Reserved)
CHSEL :: Bits 3 -- Channel selection
MBURST :: Bits 2 -- Memory burst transfer configuration
PBURST :: Bits 2 -- Peripheral burst transfer configuration
_ :: Bit -- (Reserved)
CT :: Bit -- Current target (only in double buffer mode)
DBM :: Bit -- Double buffer mode
PL :: Bits 2 -- Priority level
PINCOS :: Bit -- Peripheral increment offset size
MSIZE :: Bits 2 -- Memory data size
PSIZE :: Bits 2 -- Peripheral data size
MINC :: Bit -- Memory increment mode
PINC :: Bit -- Peripheral increment mode
CIRC :: Bit -- Circular mode
DIR :: Bits 2 -- Data transfer direction
PFCTRL :: Bit -- Peripheral flow controller
TCIE :: Bit -- Transfer complete interrupt enable
HTIE :: Bit -- Half transfer interrupt enable
TEIE :: Bit -- Transfer error interrupt enable
DMEIE :: Bit -- Direct mode error interrupt enable
EN :: Bit -- Stream enable / flag stream ready when read low
NDTR 0x8c - stream x number of data register
_ :: Bits 16 -- (Reserved)
NDT :: Bits 16 -- Number of data items to transfer
PAR 0x90 - stream x peripheral address register
PA :: Bits 32 -- Peripheral address
M0AR 0x94 - stream x memory 0 address register
M0A :: Bits 32 -- Memory 0 address
M1AR 0x98 - stream x memory 1 address register
M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode)
FCR 0x9c - stream x FIFO control register
_ :: Bits 24 -- (Reserved)
FEIE :: Bit -- FIFO error interrupt enable
_ :: Bit -- (Reserved)
FS :: Bits 3 -- FIFO status
DMDIS :: Bit -- Direct mode disable
FTH :: Bits 2 -- FIFO threshold selection
CR 0xa0 - stream x configuration register
_ :: Bits 4 -- (Reserved)
CHSEL :: Bits 3 -- Channel selection
MBURST :: Bits 2 -- Memory burst transfer configuration
PBURST :: Bits 2 -- Peripheral burst transfer configuration
_ :: Bit -- (Reserved)
CT :: Bit -- Current target (only in double buffer mode)
DBM :: Bit -- Double buffer mode
PL :: Bits 2 -- Priority level
PINCOS :: Bit -- Peripheral increment offset size
MSIZE :: Bits 2 -- Memory data size
PSIZE :: Bits 2 -- Peripheral data size
MINC :: Bit -- Memory increment mode
PINC :: Bit -- Peripheral increment mode
CIRC :: Bit -- Circular mode
DIR :: Bits 2 -- Data transfer direction
PFCTRL :: Bit -- Peripheral flow controller
TCIE :: Bit -- Transfer complete interrupt enable
HTIE :: Bit -- Half transfer interrupt enable
TEIE :: Bit -- Transfer error interrupt enable
DMEIE :: Bit -- Direct mode error interrupt enable
EN :: Bit -- Stream enable / flag stream ready when read low
NDTR 0xa4 - stream x number of data register
_ :: Bits 16 -- (Reserved)
NDT :: Bits 16 -- Number of data items to transfer
PAR 0xa8 - stream x peripheral address register
PA :: Bits 32 -- Peripheral address
M0AR 0xac - stream x memory 0 address register
M0A :: Bits 32 -- Memory 0 address
M1AR 0xb0 - stream x memory 1 address register
M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode)
FCR 0xb4 - stream x FIFO control register
_ :: Bits 24 -- (Reserved)
FEIE :: Bit -- FIFO error interrupt enable
_ :: Bit -- (Reserved)
FS :: Bits 3 -- FIFO status
DMDIS :: Bit -- Direct mode disable
FTH :: Bits 2 -- FIFO threshold selection
CR 0xb8 - stream x configuration register
_ :: Bits 4 -- (Reserved)
CHSEL :: Bits 3 -- Channel selection
MBURST :: Bits 2 -- Memory burst transfer configuration
PBURST :: Bits 2 -- Peripheral burst transfer configuration
_ :: Bit -- (Reserved)
CT :: Bit -- Current target (only in double buffer mode)
DBM :: Bit -- Double buffer mode
PL :: Bits 2 -- Priority level
PINCOS :: Bit -- Peripheral increment offset size
MSIZE :: Bits 2 -- Memory data size
PSIZE :: Bits 2 -- Peripheral data size
MINC :: Bit -- Memory increment mode
PINC :: Bit -- Peripheral increment mode
CIRC :: Bit -- Circular mode
DIR :: Bits 2 -- Data transfer direction
PFCTRL :: Bit -- Peripheral flow controller
TCIE :: Bit -- Transfer complete interrupt enable
HTIE :: Bit -- Half transfer interrupt enable
TEIE :: Bit -- Transfer error interrupt enable
DMEIE :: Bit -- Direct mode error interrupt enable
EN :: Bit -- Stream enable / flag stream ready when read low
NDTR 0xbc - stream x number of data register
_ :: Bits 16 -- (Reserved)
NDT :: Bits 16 -- Number of data items to transfer
PAR 0xc0 - stream x peripheral address register
PA :: Bits 32 -- Peripheral address
M0AR 0xc4 - stream x memory 0 address register
M0A :: Bits 32 -- Memory 0 address
M1AR 0xc8 - stream x memory 1 address register
M1A :: Bits 32 -- Memory 1 address (used in case of Double buffer mode)
FCR 0xcc - stream x FIFO control register
_ :: Bits 24 -- (Reserved)
FEIE :: Bit -- FIFO error interrupt enable
_ :: Bit -- (Reserved)
FS :: Bits 3 -- FIFO status
DMDIS :: Bit -- Direct mode disable
FTH :: Bits 2 -- FIFO threshold selection
OTG_HS_GLOBAL 0x40040000 USB on the go high speed
GOTGCTL 0x0 - OTG_HS control and status register
_ :: Bits 12 -- (Reserved)
BSVLD :: Bit -- B-session valid
ASVLD :: Bit -- A-session valid
DBCT :: Bit -- Long/short debounce time
CIDSTS :: Bit -- Connector ID status
_ :: Bits 4 -- (Reserved)
DHNPEN :: Bit -- Device HNP enabled
HSHNPEN :: Bit -- Host set HNP enable
HNPRQ :: Bit -- HNP request
HNGSCS :: Bit -- Host negotiation success
_ :: Bits 6 -- (Reserved)
SRQ :: Bit -- Session request
SRQSCS :: Bit -- Session request success
GOTGINT 0x4 - OTG_HS interrupt register
_ :: Bits 12 -- (Reserved)
DBCDNE :: Bit -- Debounce done
ADTOCHG :: Bit -- A-device timeout change
HNGDET :: Bit -- Host negotiation detected
_ :: Bits 7 -- (Reserved)
HNSSCHG :: Bit -- Host negotiation success status change
SRSSCHG :: Bit -- Session request success status change
_ :: Bits 5 -- (Reserved)
SEDET :: Bit -- Session end detected
_ :: Bits 2 -- (Reserved)
GAHBCFG 0x8 - OTG_HS AHB configuration register
_ :: Bits 23 -- (Reserved)
PTXFELVL :: Bit -- Periodic TxFIFO empty level
TXFELVL :: Bit -- TxFIFO empty level
_ :: Bit -- (Reserved)
DMAEN :: Bit -- DMA enable
HBSTLEN :: Bits 4 -- Burst length/type
GINT :: Bit -- Global interrupt mask
GUSBCFG 0xc - OTG_HS USB configuration register
CTXPKT :: Bit -- Corrupt Tx packet
FDMOD :: Bit -- Forced peripheral mode
FHMOD :: Bit -- Forced host mode
_ :: Bits 3 -- (Reserved)
ULPIIPD :: Bit -- ULPI interface protect disable
PTCI :: Bit -- Indicator pass through
PCCI :: Bit -- Indicator complement
TSDPS :: Bit -- TermSel DLine pulsing selection
ULPIEVBUSI :: Bit -- ULPI external VBUS indicator
ULPIEVBUSD :: Bit -- ULPI External VBUS Drive
ULPICSM :: Bit -- ULPI Clock SuspendM
ULPIAR :: Bit -- ULPI Auto-resume
ULPIFSLS :: Bit -- ULPI FS/LS select
_ :: Bit -- (Reserved)
PHYLPCS :: Bit -- PHY Low-power clock select
_ :: Bit -- (Reserved)
TRDT :: Bits 4 -- USB turnaround time
HNPCAP :: Bit -- HNP-capable
SRPCAP :: Bit -- SRP-capable
_ :: Bit -- (Reserved)
PHYSEL :: Bit -- USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
_ :: Bits 3 -- (Reserved)
TOCAL :: Bits 3 -- FS timeout calibration
GRSTCTL 0x10 - OTG_HS reset register
AHBIDL :: Bit -- AHB master idle
DMAREQ :: Bit -- DMA request signal
_ :: Bits 19 -- (Reserved)
TXFNUM :: Bits 5 -- TxFIFO number
TXFFLSH :: Bit -- TxFIFO flush
RXFFLSH :: Bit -- RxFIFO flush
_ :: Bit -- (Reserved)
FCRST :: Bit -- Host frame counter reset
HSRST :: Bit -- HCLK soft reset
CSRST :: Bit -- Core soft reset
GINTSTS 0x14 - OTG_HS core interrupt register
WKUINT :: Bit -- Resume/remote wakeup detected interrupt
SRQINT :: Bit -- Session request/new session detected interrupt
DISCINT :: Bit -- Disconnect detected interrupt
CIDSCHG :: Bit -- Connector ID status change
_ :: Bit -- (Reserved)
PTXFE :: Bit -- Periodic TxFIFO empty
HCINT :: Bit -- Host channels interrupt
HPRTINT :: Bit -- Host port interrupt
_ :: Bit -- (Reserved)
DATAFSUSP :: Bit -- Data fetch suspended
PXFR_INCOMPISOOUT :: Bit -- Incomplete periodic transfer
IISOIXFR :: Bit -- Incomplete isochronous IN transfer
OEPINT :: Bit -- OUT endpoint interrupt
IEPINT :: Bit -- IN endpoint interrupt
_ :: Bits 2 -- (Reserved)
EOPF :: Bit -- End of periodic frame interrupt
ISOODRP :: Bit -- Isochronous OUT packet dropped interrupt
ENUMDNE :: Bit -- Enumeration done
USBRST :: Bit -- USB reset
USBSUSP :: Bit -- USB suspend
ESUSP :: Bit -- Early suspend
_ :: Bits 2 -- (Reserved)
BOUTNAKEFF :: Bit -- Global OUT NAK effective
GINAKEFF :: Bit -- Global IN nonperiodic NAK effective
NPTXFE :: Bit -- Nonperiodic TxFIFO empty
RXFLVL :: Bit -- RxFIFO nonempty
SOF :: Bit -- Start of frame
OTGINT :: Bit -- OTG interrupt
MMIS :: Bit -- Mode mismatch interrupt
CMOD :: Bit -- Current mode of operation
GINTMSK 0x18 - OTG_HS interrupt mask register
WUIM :: Bit -- Resume/remote wakeup detected interrupt mask
SRQIM :: Bit -- Session request/new session detected interrupt mask
DISCINT :: Bit -- Disconnect detected interrupt mask
CIDSCHGM :: Bit -- Connector ID status change mask
_ :: Bit -- (Reserved)
PTXFEM :: Bit -- Periodic TxFIFO empty mask
HCIM :: Bit -- Host channels interrupt mask
PRTIM :: Bit -- Host port interrupt mask
_ :: Bit -- (Reserved)
FSUSPM :: Bit -- Data fetch suspended mask
PXFRM_IISOOXFRM :: Bit -- Incomplete periodic transfer mask
IISOIXFRM :: Bit -- Incomplete isochronous IN transfer mask
OEPINT :: Bit -- OUT endpoints interrupt mask
IEPINT :: Bit -- IN endpoints interrupt mask
EPMISM :: Bit -- Endpoint mismatch interrupt mask
_ :: Bit -- (Reserved)
EOPFM :: Bit -- End of periodic frame interrupt mask
ISOODRPM :: Bit -- Isochronous OUT packet dropped interrupt mask
ENUMDNEM :: Bit -- Enumeration done mask
USBRST :: Bit -- USB reset mask
USBSUSPM :: Bit -- USB suspend mask
ESUSPM :: Bit -- Early suspend mask
_ :: Bits 2 -- (Reserved)
GONAKEFFM :: Bit -- Global OUT NAK effective mask
GINAKEFFM :: Bit -- Global nonperiodic IN NAK effective mask
NPTXFEM :: Bit -- Nonperiodic TxFIFO empty mask
RXFLVLM :: Bit -- Receive FIFO nonempty mask
SOFM :: Bit -- Start of frame mask
OTGINT :: Bit -- OTG interrupt mask
MMISM :: Bit -- Mode mismatch interrupt mask
_ :: Bit -- (Reserved)
GRXSTSR_Host 0x1c - OTG_HS Receive status debug read register (host mode)
_ :: Bits 11 -- (Reserved)
PKTSTS :: Bits 4 -- Packet status
DPID :: Bits 2 -- Data PID
BCNT :: Bits 11 -- Byte count
CHNUM :: Bits 4 -- Channel number
GRXSTSR_Device 0x1c - OTG_HS Receive status debug read register (peripheral mode mode)
_ :: Bits 7 -- (Reserved)
FRMNUM :: Bits 4 -- Frame number
PKTSTS :: Bits 4 -- Packet status
DPID :: Bits 2 -- Data PID
BCNT :: Bits 11 -- Byte count
EPNUM :: Bits 4 -- Endpoint number
GRXSTSP_Host 0x20 - OTG_HS status read and pop register (host mode)
_ :: Bits 11 -- (Reserved)
PKTSTS :: Bits 4 -- Packet status
DPID :: Bits 2 -- Data PID
BCNT :: Bits 11 -- Byte count
CHNUM :: Bits 4 -- Channel number
GRXSTSP_Device 0x20 - OTG_HS status read and pop register (peripheral mode)
_ :: Bits 7 -- (Reserved)
FRMNUM :: Bits 4 -- Frame number
PKTSTS :: Bits 4 -- Packet status
DPID :: Bits 2 -- Data PID
BCNT :: Bits 11 -- Byte count
EPNUM :: Bits 4 -- Endpoint number
GRXFSIZ 0x24 - OTG_HS Receive FIFO size register
_ :: Bits 16 -- (Reserved)
RXFD :: Bits 16 -- RxFIFO depth
HNPTXFSIZ 0x28 - OTG_HS nonperiodic transmit FIFO size register (host mode)
NPTXFD :: Bits 16 -- Nonperiodic TxFIFO depth
NPTXFSA :: Bits 16 -- Nonperiodic transmit RAM start address
DIEPTXF0 0x28 - Endpoint 0 transmit FIFO size (peripheral mode)
TX0FD :: Bits 16 -- Endpoint 0 TxFIFO depth
TX0FSA :: Bits 16 -- Endpoint 0 transmit RAM start address
HNPTXSTS 0x2c - OTG_HS nonperiodic transmit FIFO/queue status register
_ :: Bit -- (Reserved)
NPTXQTOP :: Bits 7 -- Top of the nonperiodic transmit request queue
NPTQXSAV :: Bits 8 -- Nonperiodic transmit request queue space available
NPTXFSAV :: Bits 16 -- Nonperiodic TxFIFO space available
GCCFG 0x38 - OTG_HS general core configuration register
_ :: Bits 10 -- (Reserved)
NOVBUSSENS :: Bit -- VBUS sensing disable option
SOFOUTEN :: Bit -- SOF output enable
VBUSBSEN :: Bit -- Enable the VBUS sensing device
VBUSASEN :: Bit -- Enable the VBUS sensing device
I2CPADEN :: Bit -- Enable I2C bus connection for the external I2C PHY interface
PWRDWN :: Bit -- Power down
_ :: Bits 16 -- (Reserved)
CID 0x3c - OTG_HS core ID register
PRODUCT_ID :: Bits 32 -- Product ID field
HPTXFSIZ 0x100 - OTG_HS Host periodic transmit FIFO size register
PTXFD :: Bits 16 -- Host periodic TxFIFO depth
PTXSA :: Bits 16 -- Host periodic TxFIFO start address
DIEPTXF1 0x104 - OTG_HS device IN endpoint transmit FIFO size register
INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth
INEPTXSA :: Bits 16 -- IN endpoint FIFOx transmit RAM start address
DIEPTXF2 0x108 - OTG_HS device IN endpoint transmit FIFO size register
INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth
INEPTXSA :: Bits 16 -- IN endpoint FIFOx transmit RAM start address
DIEPTXF3 0x10c - OTG_HS device IN endpoint transmit FIFO size register
INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth
INEPTXSA :: Bits 16 -- IN endpoint FIFOx transmit RAM start address
DIEPTXF4 0x110 - OTG_HS device IN endpoint transmit FIFO size register
INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth
INEPTXSA :: Bits 16 -- IN endpoint FIFOx transmit RAM start address
DIEPTXF5 0x114 - OTG_HS device IN endpoint transmit FIFO size register
INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth
INEPTXSA :: Bits 16 -- IN endpoint FIFOx transmit RAM start address
OTG_HS_HOST 0x40040400 USB on the go high speed
HCFG 0x0 - OTG_HS host configuration register
_ :: Bits 29 -- (Reserved)
FSLSS :: Bit -- FS- and LS-only support
FSLSPCS :: Bits 2 -- FS/LS PHY clock select
HFIR 0x4 - OTG_HS Host frame interval register
_ :: Bits 16 -- (Reserved)
FRIVL :: Bits 16 -- Frame interval
HFNUM 0x8 - OTG_HS host frame number/frame time remaining register
FTREM :: Bits 16 -- Frame time remaining
FRNUM :: Bits 16 -- Frame number
HPTXSTS 0x10 - OTG_HS_Host periodic transmit FIFO/queue status register
PTXQTOP :: Bits 8 -- Top of the periodic transmit request queue
PTXQSAV :: Bits 8 -- Periodic transmit request queue space available
PTXFSAVL :: Bits 16 -- Periodic transmit data FIFO space available
HAINT 0x14 - OTG_HS Host all channels interrupt register
_ :: Bits 16 -- (Reserved)
HAINT :: Bits 16 -- Channel interrupts
HAINTMSK 0x18 - OTG_HS host all channels interrupt mask register
_ :: Bits 16 -- (Reserved)
HAINTM :: Bits 16 -- Channel interrupt mask
HPRT 0x40 - OTG_HS host port control and status register
_ :: Bits 13 -- (Reserved)
PSPD :: Bits 2 -- Port speed
PTCTL :: Bits 4 -- Port test control
PPWR :: Bit -- Port power
PLSTS :: Bits 2 -- Port line status
_ :: Bit -- (Reserved)
PRST :: Bit -- Port reset
PSUSP :: Bit -- Port suspend
PRES :: Bit -- Port resume
POCCHNG :: Bit -- Port overcurrent change
POCA :: Bit -- Port overcurrent active
PENCHNG :: Bit -- Port enable/disable change
PENA :: Bit -- Port enable
PCDET :: Bit -- Port connect detected
PCSTS :: Bit -- Port connect status
CHAR 0x100 - OTG_HS host channel-0 characteristics register
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MC :: Bits 2 -- Multi Count (MC) / Error Count (EC)
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
SPLT 0x104 - OTG_HS host channel-0 split control register
SPLITEN :: Bit -- Split enable
_ :: Bits 14 -- (Reserved)
COMPLSPLT :: Bit -- Do complete split
XACTPOS :: Bits 2 -- XACTPOS
HUBADDR :: Bits 7 -- Hub address
PRTADDR :: Bits 7 -- Port address
INT 0x108 - OTG_HS host channel-11 interrupt register
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
NYET :: Bit -- Response received interrupt
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
AHBERR :: Bit -- AHB error
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x10c - OTG_HS host channel-11 interrupt mask register
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
AHBERR :: Bit -- AHB error
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x110 - OTG_HS host channel-11 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x114 - OTG_HS host channel-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
CHAR 0x120 - OTG_HS host channel-0 characteristics register
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MC :: Bits 2 -- Multi Count (MC) / Error Count (EC)
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
SPLT 0x124 - OTG_HS host channel-0 split control register
SPLITEN :: Bit -- Split enable
_ :: Bits 14 -- (Reserved)
COMPLSPLT :: Bit -- Do complete split
XACTPOS :: Bits 2 -- XACTPOS
HUBADDR :: Bits 7 -- Hub address
PRTADDR :: Bits 7 -- Port address
INT 0x128 - OTG_HS host channel-11 interrupt register
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
NYET :: Bit -- Response received interrupt
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
AHBERR :: Bit -- AHB error
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x12c - OTG_HS host channel-11 interrupt mask register
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
AHBERR :: Bit -- AHB error
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x130 - OTG_HS host channel-11 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x134 - OTG_HS host channel-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
CHAR 0x140 - OTG_HS host channel-0 characteristics register
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MC :: Bits 2 -- Multi Count (MC) / Error Count (EC)
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
SPLT 0x144 - OTG_HS host channel-0 split control register
SPLITEN :: Bit -- Split enable
_ :: Bits 14 -- (Reserved)
COMPLSPLT :: Bit -- Do complete split
XACTPOS :: Bits 2 -- XACTPOS
HUBADDR :: Bits 7 -- Hub address
PRTADDR :: Bits 7 -- Port address
INT 0x148 - OTG_HS host channel-11 interrupt register
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
NYET :: Bit -- Response received interrupt
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
AHBERR :: Bit -- AHB error
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x14c - OTG_HS host channel-11 interrupt mask register
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
AHBERR :: Bit -- AHB error
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x150 - OTG_HS host channel-11 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x154 - OTG_HS host channel-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
CHAR 0x160 - OTG_HS host channel-0 characteristics register
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MC :: Bits 2 -- Multi Count (MC) / Error Count (EC)
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
SPLT 0x164 - OTG_HS host channel-0 split control register
SPLITEN :: Bit -- Split enable
_ :: Bits 14 -- (Reserved)
COMPLSPLT :: Bit -- Do complete split
XACTPOS :: Bits 2 -- XACTPOS
HUBADDR :: Bits 7 -- Hub address
PRTADDR :: Bits 7 -- Port address
INT 0x168 - OTG_HS host channel-11 interrupt register
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
NYET :: Bit -- Response received interrupt
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
AHBERR :: Bit -- AHB error
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x16c - OTG_HS host channel-11 interrupt mask register
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
AHBERR :: Bit -- AHB error
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x170 - OTG_HS host channel-11 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x174 - OTG_HS host channel-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
CHAR 0x180 - OTG_HS host channel-0 characteristics register
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MC :: Bits 2 -- Multi Count (MC) / Error Count (EC)
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
SPLT 0x184 - OTG_HS host channel-0 split control register
SPLITEN :: Bit -- Split enable
_ :: Bits 14 -- (Reserved)
COMPLSPLT :: Bit -- Do complete split
XACTPOS :: Bits 2 -- XACTPOS
HUBADDR :: Bits 7 -- Hub address
PRTADDR :: Bits 7 -- Port address
INT 0x188 - OTG_HS host channel-11 interrupt register
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
NYET :: Bit -- Response received interrupt
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
AHBERR :: Bit -- AHB error
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x18c - OTG_HS host channel-11 interrupt mask register
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
AHBERR :: Bit -- AHB error
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x190 - OTG_HS host channel-11 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x194 - OTG_HS host channel-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
CHAR 0x1a0 - OTG_HS host channel-0 characteristics register
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MC :: Bits 2 -- Multi Count (MC) / Error Count (EC)
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
SPLT 0x1a4 - OTG_HS host channel-0 split control register
SPLITEN :: Bit -- Split enable
_ :: Bits 14 -- (Reserved)
COMPLSPLT :: Bit -- Do complete split
XACTPOS :: Bits 2 -- XACTPOS
HUBADDR :: Bits 7 -- Hub address
PRTADDR :: Bits 7 -- Port address
INT 0x1a8 - OTG_HS host channel-11 interrupt register
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
NYET :: Bit -- Response received interrupt
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
AHBERR :: Bit -- AHB error
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x1ac - OTG_HS host channel-11 interrupt mask register
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
AHBERR :: Bit -- AHB error
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x1b0 - OTG_HS host channel-11 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x1b4 - OTG_HS host channel-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
CHAR 0x1c0 - OTG_HS host channel-0 characteristics register
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MC :: Bits 2 -- Multi Count (MC) / Error Count (EC)
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
SPLT 0x1c4 - OTG_HS host channel-0 split control register
SPLITEN :: Bit -- Split enable
_ :: Bits 14 -- (Reserved)
COMPLSPLT :: Bit -- Do complete split
XACTPOS :: Bits 2 -- XACTPOS
HUBADDR :: Bits 7 -- Hub address
PRTADDR :: Bits 7 -- Port address
INT 0x1c8 - OTG_HS host channel-11 interrupt register
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
NYET :: Bit -- Response received interrupt
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
AHBERR :: Bit -- AHB error
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x1cc - OTG_HS host channel-11 interrupt mask register
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
AHBERR :: Bit -- AHB error
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x1d0 - OTG_HS host channel-11 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x1d4 - OTG_HS host channel-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
CHAR 0x1e0 - OTG_HS host channel-0 characteristics register
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MC :: Bits 2 -- Multi Count (MC) / Error Count (EC)
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
SPLT 0x1e4 - OTG_HS host channel-0 split control register
SPLITEN :: Bit -- Split enable
_ :: Bits 14 -- (Reserved)
COMPLSPLT :: Bit -- Do complete split
XACTPOS :: Bits 2 -- XACTPOS
HUBADDR :: Bits 7 -- Hub address
PRTADDR :: Bits 7 -- Port address
INT 0x1e8 - OTG_HS host channel-11 interrupt register
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
NYET :: Bit -- Response received interrupt
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
AHBERR :: Bit -- AHB error
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x1ec - OTG_HS host channel-11 interrupt mask register
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
AHBERR :: Bit -- AHB error
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x1f0 - OTG_HS host channel-11 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x1f4 - OTG_HS host channel-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
CHAR 0x200 - OTG_HS host channel-0 characteristics register
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MC :: Bits 2 -- Multi Count (MC) / Error Count (EC)
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
SPLT 0x204 - OTG_HS host channel-0 split control register
SPLITEN :: Bit -- Split enable
_ :: Bits 14 -- (Reserved)
COMPLSPLT :: Bit -- Do complete split
XACTPOS :: Bits 2 -- XACTPOS
HUBADDR :: Bits 7 -- Hub address
PRTADDR :: Bits 7 -- Port address
INT 0x208 - OTG_HS host channel-11 interrupt register
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
NYET :: Bit -- Response received interrupt
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
AHBERR :: Bit -- AHB error
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x20c - OTG_HS host channel-11 interrupt mask register
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
AHBERR :: Bit -- AHB error
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x210 - OTG_HS host channel-11 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x214 - OTG_HS host channel-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
CHAR 0x220 - OTG_HS host channel-0 characteristics register
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MC :: Bits 2 -- Multi Count (MC) / Error Count (EC)
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
SPLT 0x224 - OTG_HS host channel-0 split control register
SPLITEN :: Bit -- Split enable
_ :: Bits 14 -- (Reserved)
COMPLSPLT :: Bit -- Do complete split
XACTPOS :: Bits 2 -- XACTPOS
HUBADDR :: Bits 7 -- Hub address
PRTADDR :: Bits 7 -- Port address
INT 0x228 - OTG_HS host channel-11 interrupt register
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
NYET :: Bit -- Response received interrupt
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
AHBERR :: Bit -- AHB error
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x22c - OTG_HS host channel-11 interrupt mask register
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
AHBERR :: Bit -- AHB error
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x230 - OTG_HS host channel-11 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x234 - OTG_HS host channel-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
CHAR 0x240 - OTG_HS host channel-0 characteristics register
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MC :: Bits 2 -- Multi Count (MC) / Error Count (EC)
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
SPLT 0x244 - OTG_HS host channel-0 split control register
SPLITEN :: Bit -- Split enable
_ :: Bits 14 -- (Reserved)
COMPLSPLT :: Bit -- Do complete split
XACTPOS :: Bits 2 -- XACTPOS
HUBADDR :: Bits 7 -- Hub address
PRTADDR :: Bits 7 -- Port address
INT 0x248 - OTG_HS host channel-11 interrupt register
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
NYET :: Bit -- Response received interrupt
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
AHBERR :: Bit -- AHB error
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x24c - OTG_HS host channel-11 interrupt mask register
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
AHBERR :: Bit -- AHB error
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x250 - OTG_HS host channel-11 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x254 - OTG_HS host channel-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
CHAR 0x260 - OTG_HS host channel-0 characteristics register
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MC :: Bits 2 -- Multi Count (MC) / Error Count (EC)
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
SPLT 0x264 - OTG_HS host channel-0 split control register
SPLITEN :: Bit -- Split enable
_ :: Bits 14 -- (Reserved)
COMPLSPLT :: Bit -- Do complete split
XACTPOS :: Bits 2 -- XACTPOS
HUBADDR :: Bits 7 -- Hub address
PRTADDR :: Bits 7 -- Port address
INT 0x268 - OTG_HS host channel-11 interrupt register
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
NYET :: Bit -- Response received interrupt
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
AHBERR :: Bit -- AHB error
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x26c - OTG_HS host channel-11 interrupt mask register
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
AHBERR :: Bit -- AHB error
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x270 - OTG_HS host channel-11 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x274 - OTG_HS host channel-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
OTG_HS_DEVICE 0x40040800 USB on the go high speed
DCFG 0x0 - OTG_HS device configuration register
_ :: Bits 6 -- (Reserved)
PERSCHIVL :: Bits 2 -- Periodic scheduling interval
_ :: Bits 11 -- (Reserved)
PFIVL :: Bits 2 -- Periodic (micro)frame interval
DAD :: Bits 7 -- Device address
_ :: Bit -- (Reserved)
NZLSOHSK :: Bit -- Nonzero-length status OUT handshake
DSPD :: Bits 2 -- Device speed
DCTL 0x4 - OTG_HS device control register
_ :: Bits 20 -- (Reserved)
POPRGDNE :: Bit -- Power-on programming done
CGONAK :: Bit -- Clear global OUT NAK
SGONAK :: Bit -- Set global OUT NAK
CGINAK :: Bit -- Clear global IN NAK
SGINAK :: Bit -- Set global IN NAK
TCTL :: Bits 3 -- Test control
GONSTS :: Bit -- Global OUT NAK status
GINSTS :: Bit -- Global IN NAK status
SDIS :: Bit -- Soft disconnect
RWUSIG :: Bit -- Remote wakeup signaling
DSTS 0x8 - OTG_HS device status register
_ :: Bits 10 -- (Reserved)
FNSOF :: Bits 14 -- Frame number of the received SOF
_ :: Bits 4 -- (Reserved)
EERR :: Bit -- Erratic error
ENUMSPD :: Bits 2 -- Enumerated speed
SUSPSTS :: Bit -- Suspend status
DIEPMSK 0x10 - OTG_HS device IN endpoint common interrupt mask register
_ :: Bits 22 -- (Reserved)
BIM :: Bit -- BNA interrupt mask
TXFURM :: Bit -- FIFO underrun mask
_ :: Bit -- (Reserved)
INEPNEM :: Bit -- IN endpoint NAK effective mask
INEPNMM :: Bit -- IN token received with EP mismatch mask
ITTXFEMSK :: Bit -- IN token received when TxFIFO empty mask
TOM :: Bit -- Timeout condition mask (nonisochronous endpoints)
_ :: Bit -- (Reserved)
EPDM :: Bit -- Endpoint disabled interrupt mask
XFRCM :: Bit -- Transfer completed interrupt mask
DOEPMSK 0x14 - OTG_HS device OUT endpoint common interrupt mask register
_ :: Bits 22 -- (Reserved)
BOIM :: Bit -- BNA interrupt mask
OPEM :: Bit -- OUT packet error mask
_ :: Bit -- (Reserved)
B2BSTUP :: Bit -- Back-to-back SETUP packets received mask
_ :: Bit -- (Reserved)
OTEPDM :: Bit -- OUT token received when endpoint disabled mask
STUPM :: Bit -- SETUP phase done mask
_ :: Bit -- (Reserved)
EPDM :: Bit -- Endpoint disabled interrupt mask
XFRCM :: Bit -- Transfer completed interrupt mask
DAINT 0x18 - OTG_HS device all endpoints interrupt register
OEPINT :: Bits 16 -- OUT endpoint interrupt bits
IEPINT :: Bits 16 -- IN endpoint interrupt bits
DAINTMSK 0x1c - OTG_HS all endpoints interrupt mask register
OEPM :: Bits 16 -- OUT EP interrupt mask bits
IEPM :: Bits 16 -- IN EP interrupt mask bits
DVBUSDIS 0x28 - OTG_HS device VBUS discharge time register
_ :: Bits 16 -- (Reserved)
VBUSDT :: Bits 16 -- Device VBUS discharge time
DVBUSPULSE 0x2c - OTG_HS device VBUS pulsing time register
_ :: Bits 20 -- (Reserved)
DVBUSP :: Bits 12 -- Device VBUS pulsing time
DTHRCTL 0x30 - OTG_HS Device threshold control register
_ :: Bits 4 -- (Reserved)
ARPEN :: Bit -- Arbiter parking enable
_ :: Bit -- (Reserved)
RXTHRLEN :: Bits 9 -- Receive threshold length
RXTHREN :: Bit -- Receive threshold enable
_ :: Bits 5 -- (Reserved)
TXTHRLEN :: Bits 9 -- Transmit threshold length
ISOTHREN :: Bit -- ISO IN endpoint threshold enable
NONISOTHREN :: Bit -- Nonisochronous IN endpoints threshold enable
DIEPEMPMSK 0x34 - OTG_HS device IN endpoint FIFO empty interrupt mask register
_ :: Bits 16 -- (Reserved)
INEPTXFEM :: Bits 16 -- IN EP Tx FIFO empty interrupt mask bits
DEACHINT 0x38 - OTG_HS device each endpoint interrupt register
_ :: Bits 14 -- (Reserved)
OEP1INT :: Bit -- OUT endpoint 1 interrupt bit
_ :: Bits 15 -- (Reserved)
IEP1INT :: Bit -- IN endpoint 1interrupt bit
_ :: Bit -- (Reserved)
DEACHINTMSK 0x3c - OTG_HS device each endpoint interrupt register mask
_ :: Bits 14 -- (Reserved)
OEP1INTM :: Bit -- OUT Endpoint 1 interrupt mask bit
_ :: Bits 15 -- (Reserved)
IEP1INTM :: Bit -- IN Endpoint 1 interrupt mask bit
_ :: Bit -- (Reserved)
DIEPEACHMSK1 0x44 - OTG_HS device each in endpoint-1 interrupt register
_ :: Bits 18 -- (Reserved)
NAKM :: Bit -- NAK interrupt mask
_ :: Bits 3 -- (Reserved)
BIM :: Bit -- BNA interrupt mask
TXFURM :: Bit -- FIFO underrun mask
_ :: Bit -- (Reserved)
INEPNEM :: Bit -- IN endpoint NAK effective mask
INEPNMM :: Bit -- IN token received with EP mismatch mask
ITTXFEMSK :: Bit -- IN token received when TxFIFO empty mask
TOM :: Bit -- Timeout condition mask (nonisochronous endpoints)
_ :: Bit -- (Reserved)
EPDM :: Bit -- Endpoint disabled interrupt mask
XFRCM :: Bit -- Transfer completed interrupt mask
DOEPEACHMSK1 0x84 - OTG_HS device each OUT endpoint-1 interrupt register
_ :: Bits 17 -- (Reserved)
NYETM :: Bit -- NYET interrupt mask
NAKM :: Bit -- NAK interrupt mask
BERRM :: Bit -- Bubble error interrupt mask
_ :: Bits 2 -- (Reserved)
BIM :: Bit -- BNA interrupt mask
TXFURM :: Bit -- OUT packet error mask
_ :: Bit -- (Reserved)
INEPNEM :: Bit -- IN endpoint NAK effective mask
INEPNMM :: Bit -- IN token received with EP mismatch mask
ITTXFEMSK :: Bit -- IN token received when TxFIFO empty mask
TOM :: Bit -- Timeout condition mask
_ :: Bit -- (Reserved)
EPDM :: Bit -- Endpoint disabled interrupt mask
XFRCM :: Bit -- Transfer completed interrupt mask
CTL 0x100 - OTG device endpoint-0 control register
EPENA :: Bit -- Endpoint enable
EPDIS :: Bit -- Endpoint disable
SODDFRM :: Bit -- Set odd frame
SD0PID_SEVNFRM :: Bit -- Set DATA0 PID
SNAK :: Bit -- Set NAK
CNAK :: Bit -- Clear NAK
TXFNUM :: Bits 4 -- TxFIFO number
STALL :: Bit -- STALL handshake
_ :: Bit -- (Reserved)
EPTYP :: Bits 2 -- Endpoint type
NAKSTS :: Bit -- NAK status
EONUM_DPID :: Bit -- Even/odd frame
USBAEP :: Bit -- USB active endpoint
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x108 - OTG device endpoint-0 interrupt register
_ :: Bits 18 -- (Reserved)
NAK :: Bit -- NAK interrupt
BERR :: Bit -- Babble error interrupt
PKTDRPSTS :: Bit -- Packet dropped status
_ :: Bit -- (Reserved)
BNA :: Bit -- Buffer not available interrupt
TXFIFOUDRN :: Bit -- Transmit Fifo Underrun
TXFE :: Bit -- Transmit FIFO empty
INEPNE :: Bit -- IN endpoint NAK effective
_ :: Bit -- (Reserved)
ITTXFE :: Bit -- IN token received when TxFIFO is empty
TOC :: Bit -- Timeout condition
_ :: Bit -- (Reserved)
EPDISD :: Bit -- Endpoint disabled interrupt
XFRC :: Bit -- Transfer completed interrupt
TSIZ 0x110 - OTG_HS device IN endpoint 0 transfer size register
_ :: Bits 11 -- (Reserved)
PKTCNT :: Bits 2 -- Packet count
_ :: Bits 12 -- (Reserved)
XFRSIZ :: Bits 7 -- Transfer size
DMA 0x114 - OTG_HS device endpoint-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
TXFSTS 0x118 - OTG_HS device IN endpoint transmit FIFO status register
_ :: Bits 16 -- (Reserved)
INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space avail
CTL 0x120 - OTG device endpoint-1 control register
EPENA :: Bit -- Endpoint enable
EPDIS :: Bit -- Endpoint disable
SODDFRM :: Bit -- Set odd frame
SD0PID_SEVNFRM :: Bit -- Set DATA0 PID
SNAK :: Bit -- Set NAK
CNAK :: Bit -- Clear NAK
TXFNUM :: Bits 4 -- TxFIFO number
STALL :: Bit -- STALL handshake
_ :: Bit -- (Reserved)
EPTYP :: Bits 2 -- Endpoint type
NAKSTS :: Bit -- NAK status
EONUM_DPID :: Bit -- Even/odd frame
USBAEP :: Bit -- USB active endpoint
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x128 - OTG device endpoint-1 interrupt register
_ :: Bits 18 -- (Reserved)
NAK :: Bit -- NAK interrupt
BERR :: Bit -- Babble error interrupt
PKTDRPSTS :: Bit -- Packet dropped status
_ :: Bit -- (Reserved)
BNA :: Bit -- Buffer not available interrupt
TXFIFOUDRN :: Bit -- Transmit Fifo Underrun
TXFE :: Bit -- Transmit FIFO empty
INEPNE :: Bit -- IN endpoint NAK effective
_ :: Bit -- (Reserved)
ITTXFE :: Bit -- IN token received when TxFIFO is empty
TOC :: Bit -- Timeout condition
_ :: Bit -- (Reserved)
EPDISD :: Bit -- Endpoint disabled interrupt
XFRC :: Bit -- Transfer completed interrupt
TSIZ 0x130 - OTG_HS device endpoint transfer size register
_ :: Bit -- (Reserved)
MCNT :: Bits 2 -- Multi count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x134 - OTG_HS device endpoint-1 DMA address register
DMAADDR :: Bits 32 -- DMA address
TXFSTS 0x138 - OTG_HS device IN endpoint transmit FIFO status register
_ :: Bits 16 -- (Reserved)
INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space avail
CTL 0x140 - OTG device endpoint-1 control register
EPENA :: Bit -- Endpoint enable
EPDIS :: Bit -- Endpoint disable
SODDFRM :: Bit -- Set odd frame
SD0PID_SEVNFRM :: Bit -- Set DATA0 PID
SNAK :: Bit -- Set NAK
CNAK :: Bit -- Clear NAK
TXFNUM :: Bits 4 -- TxFIFO number
STALL :: Bit -- STALL handshake
_ :: Bit -- (Reserved)
EPTYP :: Bits 2 -- Endpoint type
NAKSTS :: Bit -- NAK status
EONUM_DPID :: Bit -- Even/odd frame
USBAEP :: Bit -- USB active endpoint
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x148 - OTG device endpoint-1 interrupt register
_ :: Bits 18 -- (Reserved)
NAK :: Bit -- NAK interrupt
BERR :: Bit -- Babble error interrupt
PKTDRPSTS :: Bit -- Packet dropped status
_ :: Bit -- (Reserved)
BNA :: Bit -- Buffer not available interrupt
TXFIFOUDRN :: Bit -- Transmit Fifo Underrun
TXFE :: Bit -- Transmit FIFO empty
INEPNE :: Bit -- IN endpoint NAK effective
_ :: Bit -- (Reserved)
ITTXFE :: Bit -- IN token received when TxFIFO is empty
TOC :: Bit -- Timeout condition
_ :: Bit -- (Reserved)
EPDISD :: Bit -- Endpoint disabled interrupt
XFRC :: Bit -- Transfer completed interrupt
TSIZ 0x150 - OTG_HS device endpoint transfer size register
_ :: Bit -- (Reserved)
MCNT :: Bits 2 -- Multi count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x154 - OTG_HS device endpoint-1 DMA address register
DMAADDR :: Bits 32 -- DMA address
TXFSTS 0x158 - OTG_HS device IN endpoint transmit FIFO status register
_ :: Bits 16 -- (Reserved)
INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space avail
CTL 0x160 - OTG device endpoint-1 control register
EPENA :: Bit -- Endpoint enable
EPDIS :: Bit -- Endpoint disable
SODDFRM :: Bit -- Set odd frame
SD0PID_SEVNFRM :: Bit -- Set DATA0 PID
SNAK :: Bit -- Set NAK
CNAK :: Bit -- Clear NAK
TXFNUM :: Bits 4 -- TxFIFO number
STALL :: Bit -- STALL handshake
_ :: Bit -- (Reserved)
EPTYP :: Bits 2 -- Endpoint type
NAKSTS :: Bit -- NAK status
EONUM_DPID :: Bit -- Even/odd frame
USBAEP :: Bit -- USB active endpoint
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x168 - OTG device endpoint-1 interrupt register
_ :: Bits 18 -- (Reserved)
NAK :: Bit -- NAK interrupt
BERR :: Bit -- Babble error interrupt
PKTDRPSTS :: Bit -- Packet dropped status
_ :: Bit -- (Reserved)
BNA :: Bit -- Buffer not available interrupt
TXFIFOUDRN :: Bit -- Transmit Fifo Underrun
TXFE :: Bit -- Transmit FIFO empty
INEPNE :: Bit -- IN endpoint NAK effective
_ :: Bit -- (Reserved)
ITTXFE :: Bit -- IN token received when TxFIFO is empty
TOC :: Bit -- Timeout condition
_ :: Bit -- (Reserved)
EPDISD :: Bit -- Endpoint disabled interrupt
XFRC :: Bit -- Transfer completed interrupt
TSIZ 0x170 - OTG_HS device endpoint transfer size register
_ :: Bit -- (Reserved)
MCNT :: Bits 2 -- Multi count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x174 - OTG_HS device endpoint-1 DMA address register
DMAADDR :: Bits 32 -- DMA address
TXFSTS 0x178 - OTG_HS device IN endpoint transmit FIFO status register
_ :: Bits 16 -- (Reserved)
INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space avail
CTL 0x180 - OTG device endpoint-1 control register
EPENA :: Bit -- Endpoint enable
EPDIS :: Bit -- Endpoint disable
SODDFRM :: Bit -- Set odd frame
SD0PID_SEVNFRM :: Bit -- Set DATA0 PID
SNAK :: Bit -- Set NAK
CNAK :: Bit -- Clear NAK
TXFNUM :: Bits 4 -- TxFIFO number
STALL :: Bit -- STALL handshake
_ :: Bit -- (Reserved)
EPTYP :: Bits 2 -- Endpoint type
NAKSTS :: Bit -- NAK status
EONUM_DPID :: Bit -- Even/odd frame
USBAEP :: Bit -- USB active endpoint
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x188 - OTG device endpoint-1 interrupt register
_ :: Bits 18 -- (Reserved)
NAK :: Bit -- NAK interrupt
BERR :: Bit -- Babble error interrupt
PKTDRPSTS :: Bit -- Packet dropped status
_ :: Bit -- (Reserved)
BNA :: Bit -- Buffer not available interrupt
TXFIFOUDRN :: Bit -- Transmit Fifo Underrun
TXFE :: Bit -- Transmit FIFO empty
INEPNE :: Bit -- IN endpoint NAK effective
_ :: Bit -- (Reserved)
ITTXFE :: Bit -- IN token received when TxFIFO is empty
TOC :: Bit -- Timeout condition
_ :: Bit -- (Reserved)
EPDISD :: Bit -- Endpoint disabled interrupt
XFRC :: Bit -- Transfer completed interrupt
TSIZ 0x190 - OTG_HS device endpoint transfer size register
_ :: Bit -- (Reserved)
MCNT :: Bits 2 -- Multi count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x194 - OTG_HS device endpoint-1 DMA address register
DMAADDR :: Bits 32 -- DMA address
TXFSTS 0x198 - OTG_HS device IN endpoint transmit FIFO status register
_ :: Bits 16 -- (Reserved)
INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space avail
CTL 0x1a0 - OTG device endpoint-1 control register
EPENA :: Bit -- Endpoint enable
EPDIS :: Bit -- Endpoint disable
SODDFRM :: Bit -- Set odd frame
SD0PID_SEVNFRM :: Bit -- Set DATA0 PID
SNAK :: Bit -- Set NAK
CNAK :: Bit -- Clear NAK
TXFNUM :: Bits 4 -- TxFIFO number
STALL :: Bit -- STALL handshake
_ :: Bit -- (Reserved)
EPTYP :: Bits 2 -- Endpoint type
NAKSTS :: Bit -- NAK status
EONUM_DPID :: Bit -- Even/odd frame
USBAEP :: Bit -- USB active endpoint
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x1a8 - OTG device endpoint-1 interrupt register
_ :: Bits 18 -- (Reserved)
NAK :: Bit -- NAK interrupt
BERR :: Bit -- Babble error interrupt
PKTDRPSTS :: Bit -- Packet dropped status
_ :: Bit -- (Reserved)
BNA :: Bit -- Buffer not available interrupt
TXFIFOUDRN :: Bit -- Transmit Fifo Underrun
TXFE :: Bit -- Transmit FIFO empty
INEPNE :: Bit -- IN endpoint NAK effective
_ :: Bit -- (Reserved)
ITTXFE :: Bit -- IN token received when TxFIFO is empty
TOC :: Bit -- Timeout condition
_ :: Bit -- (Reserved)
EPDISD :: Bit -- Endpoint disabled interrupt
XFRC :: Bit -- Transfer completed interrupt
TSIZ 0x1b0 - OTG_HS device endpoint transfer size register
_ :: Bit -- (Reserved)
MCNT :: Bits 2 -- Multi count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x1b4 - OTG_HS device endpoint-1 DMA address register
DMAADDR :: Bits 32 -- DMA address
TXFSTS 0x1b8 - OTG_HS device IN endpoint transmit FIFO status register
_ :: Bits 16 -- (Reserved)
INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space avail
CTL 0x300 - OTG_HS device control OUT endpoint 0 control register
EPENA :: Bit -- Endpoint enable
EPDIS :: Bit -- Endpoint disable
_ :: Bits 2 -- (Reserved)
SNAK :: Bit -- Set NAK
CNAK :: Bit -- Clear NAK
_ :: Bits 4 -- (Reserved)
STALL :: Bit -- STALL handshake
SNPM :: Bit -- Snoop mode
EPTYP :: Bits 2 -- Endpoint type
NAKSTS :: Bit -- NAK status
_ :: Bit -- (Reserved)
USBAEP :: Bit -- USB active endpoint
_ :: Bits 13 -- (Reserved)
MPSIZ :: Bits 2 -- Maximum packet size
INT 0x308 - OTG_HS device endpoint-0 interrupt register
_ :: Bits 17 -- (Reserved)
NYET :: Bit -- NYET interrupt
_ :: Bits 7 -- (Reserved)
B2BSTUP :: Bit -- Back-to-back SETUP packets received
_ :: Bit -- (Reserved)
OTEPDIS :: Bit -- OUT token received when endpoint disabled
STUP :: Bit -- SETUP phase done
_ :: Bit -- (Reserved)
EPDISD :: Bit -- Endpoint disabled interrupt
XFRC :: Bit -- Transfer completed interrupt
TSIZ 0x310 - OTG_HS device endpoint-1 transfer size register
_ :: Bit -- (Reserved)
STUPCNT :: Bits 2 -- SETUP packet count
_ :: Bits 9 -- (Reserved)
PKTCNT :: Bit -- Packet count
_ :: Bits 12 -- (Reserved)
XFRSIZ :: Bits 7 -- Transfer size
DMA 0x314 - OTG_HS device endpoint-0 DMA address register
DMAADDR :: Bits 32 -- DMA address
CTL 0x320 - OTG device endpoint-1 control register
EPENA :: Bit -- Endpoint enable
EPDIS :: Bit -- Endpoint disable
SODDFRM :: Bit -- Set odd frame
SD0PID_SEVNFRM :: Bit -- Set DATA0 PID/Set even frame
SNAK :: Bit -- Set NAK
CNAK :: Bit -- Clear NAK
_ :: Bits 4 -- (Reserved)
STALL :: Bit -- STALL handshake
SNPM :: Bit -- Snoop mode
EPTYP :: Bits 2 -- Endpoint type
NAKSTS :: Bit -- NAK status
EONUM_DPID :: Bit -- Even odd frame/Endpoint data PID
USBAEP :: Bit -- USB active endpoint
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x328 - OTG_HS device endpoint-1 interrupt register
_ :: Bits 17 -- (Reserved)
NYET :: Bit -- NYET interrupt
_ :: Bits 7 -- (Reserved)
B2BSTUP :: Bit -- Back-to-back SETUP packets received
_ :: Bit -- (Reserved)
OTEPDIS :: Bit -- OUT token received when endpoint disabled
STUP :: Bit -- SETUP phase done
_ :: Bit -- (Reserved)
EPDISD :: Bit -- Endpoint disabled interrupt
XFRC :: Bit -- Transfer completed interrupt
TSIZ 0x330 - OTG_HS device endpoint-2 transfer size register
_ :: Bit -- (Reserved)
RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x334 - OTG_HS device endpoint-1 DMA address register
DMAADDR :: Bits 32 -- DMA address
CTL 0x340 - OTG device endpoint-1 control register
EPENA :: Bit -- Endpoint enable
EPDIS :: Bit -- Endpoint disable
SODDFRM :: Bit -- Set odd frame
SD0PID_SEVNFRM :: Bit -- Set DATA0 PID/Set even frame
SNAK :: Bit -- Set NAK
CNAK :: Bit -- Clear NAK
_ :: Bits 4 -- (Reserved)
STALL :: Bit -- STALL handshake
SNPM :: Bit -- Snoop mode
EPTYP :: Bits 2 -- Endpoint type
NAKSTS :: Bit -- NAK status
EONUM_DPID :: Bit -- Even odd frame/Endpoint data PID
USBAEP :: Bit -- USB active endpoint
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x348 - OTG_HS device endpoint-1 interrupt register
_ :: Bits 17 -- (Reserved)
NYET :: Bit -- NYET interrupt
_ :: Bits 7 -- (Reserved)
B2BSTUP :: Bit -- Back-to-back SETUP packets received
_ :: Bit -- (Reserved)
OTEPDIS :: Bit -- OUT token received when endpoint disabled
STUP :: Bit -- SETUP phase done
_ :: Bit -- (Reserved)
EPDISD :: Bit -- Endpoint disabled interrupt
XFRC :: Bit -- Transfer completed interrupt
TSIZ 0x350 - OTG_HS device endpoint-2 transfer size register
_ :: Bit -- (Reserved)
RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x354 - OTG_HS device endpoint-1 DMA address register
DMAADDR :: Bits 32 -- DMA address
CTL 0x360 - OTG device endpoint-1 control register
EPENA :: Bit -- Endpoint enable
EPDIS :: Bit -- Endpoint disable
SODDFRM :: Bit -- Set odd frame
SD0PID_SEVNFRM :: Bit -- Set DATA0 PID/Set even frame
SNAK :: Bit -- Set NAK
CNAK :: Bit -- Clear NAK
_ :: Bits 4 -- (Reserved)
STALL :: Bit -- STALL handshake
SNPM :: Bit -- Snoop mode
EPTYP :: Bits 2 -- Endpoint type
NAKSTS :: Bit -- NAK status
EONUM_DPID :: Bit -- Even odd frame/Endpoint data PID
USBAEP :: Bit -- USB active endpoint
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x368 - OTG_HS device endpoint-1 interrupt register
_ :: Bits 17 -- (Reserved)
NYET :: Bit -- NYET interrupt
_ :: Bits 7 -- (Reserved)
B2BSTUP :: Bit -- Back-to-back SETUP packets received
_ :: Bit -- (Reserved)
OTEPDIS :: Bit -- OUT token received when endpoint disabled
STUP :: Bit -- SETUP phase done
_ :: Bit -- (Reserved)
EPDISD :: Bit -- Endpoint disabled interrupt
XFRC :: Bit -- Transfer completed interrupt
TSIZ 0x370 - OTG_HS device endpoint-2 transfer size register
_ :: Bit -- (Reserved)
RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x374 - OTG_HS device endpoint-1 DMA address register
DMAADDR :: Bits 32 -- DMA address
CTL 0x380 - OTG device endpoint-1 control register
EPENA :: Bit -- Endpoint enable
EPDIS :: Bit -- Endpoint disable
SODDFRM :: Bit -- Set odd frame
SD0PID_SEVNFRM :: Bit -- Set DATA0 PID/Set even frame
SNAK :: Bit -- Set NAK
CNAK :: Bit -- Clear NAK
_ :: Bits 4 -- (Reserved)
STALL :: Bit -- STALL handshake
SNPM :: Bit -- Snoop mode
EPTYP :: Bits 2 -- Endpoint type
NAKSTS :: Bit -- NAK status
EONUM_DPID :: Bit -- Even odd frame/Endpoint data PID
USBAEP :: Bit -- USB active endpoint
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x388 - OTG_HS device endpoint-1 interrupt register
_ :: Bits 17 -- (Reserved)
NYET :: Bit -- NYET interrupt
_ :: Bits 7 -- (Reserved)
B2BSTUP :: Bit -- Back-to-back SETUP packets received
_ :: Bit -- (Reserved)
OTEPDIS :: Bit -- OUT token received when endpoint disabled
STUP :: Bit -- SETUP phase done
_ :: Bit -- (Reserved)
EPDISD :: Bit -- Endpoint disabled interrupt
XFRC :: Bit -- Transfer completed interrupt
TSIZ 0x390 - OTG_HS device endpoint-2 transfer size register
_ :: Bit -- (Reserved)
RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x394 - OTG_HS device endpoint-1 DMA address register
DMAADDR :: Bits 32 -- DMA address
CTL 0x3a0 - OTG device endpoint-1 control register
EPENA :: Bit -- Endpoint enable
EPDIS :: Bit -- Endpoint disable
SODDFRM :: Bit -- Set odd frame
SD0PID_SEVNFRM :: Bit -- Set DATA0 PID/Set even frame
SNAK :: Bit -- Set NAK
CNAK :: Bit -- Clear NAK
_ :: Bits 4 -- (Reserved)
STALL :: Bit -- STALL handshake
SNPM :: Bit -- Snoop mode
EPTYP :: Bits 2 -- Endpoint type
NAKSTS :: Bit -- NAK status
EONUM_DPID :: Bit -- Even odd frame/Endpoint data PID
USBAEP :: Bit -- USB active endpoint
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x3a8 - OTG_HS device endpoint-1 interrupt register
_ :: Bits 17 -- (Reserved)
NYET :: Bit -- NYET interrupt
_ :: Bits 7 -- (Reserved)
B2BSTUP :: Bit -- Back-to-back SETUP packets received
_ :: Bit -- (Reserved)
OTEPDIS :: Bit -- OUT token received when endpoint disabled
STUP :: Bit -- SETUP phase done
_ :: Bit -- (Reserved)
EPDISD :: Bit -- Endpoint disabled interrupt
XFRC :: Bit -- Transfer completed interrupt
TSIZ 0x3b0 - OTG_HS device endpoint-2 transfer size register
_ :: Bit -- (Reserved)
RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
DMA 0x3b4 - OTG_HS device endpoint-1 DMA address register
DMAADDR :: Bits 32 -- DMA address
OTG_HS_PWRCLK 0x40040e00 USB on the go high speed
PCGCCTL 0x0 - Power and clock gating control register
_ :: Bits 27 -- (Reserved)
PHYSUSP :: Bit -- PHY suspended
_ :: Bits 2 -- (Reserved)
GATEHCLK :: Bit -- Gate HCLK
STPPCLK :: Bit -- Stop PHY clock
OTG_FS_GLOBAL 0x50000000 USB on the go full speed
GOTGCTL 0x0 - OTG_FS control and status register (OTG_FS_GOTGCTL)
_ :: Bits 12 -- (Reserved)
BSVLD :: Bit -- B-session valid
ASVLD :: Bit -- A-session valid
DBCT :: Bit -- Long/short debounce time
CIDSTS :: Bit -- Connector ID status
_ :: Bits 4 -- (Reserved)
DHNPEN :: Bit -- Device HNP enabled
HSHNPEN :: Bit -- Host set HNP enable
HNPRQ :: Bit -- HNP request
HNGSCS :: Bit -- Host negotiation success
_ :: Bits 6 -- (Reserved)
SRQ :: Bit -- Session request
SRQSCS :: Bit -- Session request success
GOTGINT 0x4 - OTG_FS interrupt register (OTG_FS_GOTGINT)
_ :: Bits 12 -- (Reserved)
DBCDNE :: Bit -- Debounce done
ADTOCHG :: Bit -- A-device timeout change
HNGDET :: Bit -- Host negotiation detected
_ :: Bits 7 -- (Reserved)
HNSSCHG :: Bit -- Host negotiation success status change
SRSSCHG :: Bit -- Session request success status change
_ :: Bits 5 -- (Reserved)
SEDET :: Bit -- Session end detected
_ :: Bits 2 -- (Reserved)
GAHBCFG 0x8 - OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
_ :: Bits 23 -- (Reserved)
PTXFELVL :: Bit -- Periodic TxFIFO empty level
TXFELVL :: Bit -- TxFIFO empty level
_ :: Bits 6 -- (Reserved)
GINT :: Bit -- Global interrupt mask
GUSBCFG 0xc - OTG_FS USB configuration register (OTG_FS_GUSBCFG)
CTXPKT :: Bit -- Corrupt Tx packet
FDMOD :: Bit -- Force device mode
FHMOD :: Bit -- Force host mode
_ :: Bits 15 -- (Reserved)
TRDT :: Bits 4 -- USB turnaround time
HNPCAP :: Bit -- HNP-capable
SRPCAP :: Bit -- SRP-capable
_ :: Bit -- (Reserved)
PHYSEL :: Bit -- Full Speed serial transceiver select
_ :: Bits 3 -- (Reserved)
TOCAL :: Bits 3 -- FS timeout calibration
GRSTCTL 0x10 - OTG_FS reset register (OTG_FS_GRSTCTL)
AHBIDL :: Bit -- AHB master idle
_ :: Bits 20 -- (Reserved)
TXFNUM :: Bits 5 -- TxFIFO number
TXFFLSH :: Bit -- TxFIFO flush
RXFFLSH :: Bit -- RxFIFO flush
_ :: Bit -- (Reserved)
FCRST :: Bit -- Host frame counter reset
HSRST :: Bit -- HCLK soft reset
CSRST :: Bit -- Core soft reset
GINTSTS 0x14 - OTG_FS core interrupt register (OTG_FS_GINTSTS)
WKUPINT :: Bit -- Resume/remote wakeup detected interrupt
SRQINT :: Bit -- Session request/new session detected interrupt
DISCINT :: Bit -- Disconnect detected interrupt
CIDSCHG :: Bit -- Connector ID status change
_ :: Bit -- (Reserved)
PTXFE :: Bit -- Periodic TxFIFO empty
HCINT :: Bit -- Host channels interrupt
HPRTINT :: Bit -- Host port interrupt
_ :: Bits 2 -- (Reserved)
IPXFR_INCOMPISOOUT :: Bit -- Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)
IISOIXFR :: Bit -- Incomplete isochronous IN transfer
OEPINT :: Bit -- OUT endpoint interrupt
IEPINT :: Bit -- IN endpoint interrupt
_ :: Bits 2 -- (Reserved)
EOPF :: Bit -- End of periodic frame interrupt
ISOODRP :: Bit -- Isochronous OUT packet dropped interrupt
ENUMDNE :: Bit -- Enumeration done
USBRST :: Bit -- USB reset
USBSUSP :: Bit -- USB suspend
ESUSP :: Bit -- Early suspend
_ :: Bits 2 -- (Reserved)
GOUTNAKEFF :: Bit -- Global OUT NAK effective
GINAKEFF :: Bit -- Global IN non-periodic NAK effective
NPTXFE :: Bit -- Non-periodic TxFIFO empty
RXFLVL :: Bit -- RxFIFO non-empty
SOF :: Bit -- Start of frame
OTGINT :: Bit -- OTG interrupt
MMIS :: Bit -- Mode mismatch interrupt
CMOD :: Bit -- Current mode of operation
GINTMSK 0x18 - OTG_FS interrupt mask register (OTG_FS_GINTMSK)
WUIM :: Bit -- Resume/remote wakeup detected interrupt mask
SRQIM :: Bit -- Session request/new session detected interrupt mask
DISCINT :: Bit -- Disconnect detected interrupt mask
CIDSCHGM :: Bit -- Connector ID status change mask
_ :: Bit -- (Reserved)
PTXFEM :: Bit -- Periodic TxFIFO empty mask
HCIM :: Bit -- Host channels interrupt mask
PRTIM :: Bit -- Host port interrupt mask
_ :: Bits 2 -- (Reserved)
IPXFRM_IISOOXFRM :: Bit -- Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)
IISOIXFRM :: Bit -- Incomplete isochronous IN transfer mask
OEPINT :: Bit -- OUT endpoints interrupt mask
IEPINT :: Bit -- IN endpoints interrupt mask
EPMISM :: Bit -- Endpoint mismatch interrupt mask
_ :: Bit -- (Reserved)
EOPFM :: Bit -- End of periodic frame interrupt mask
ISOODRPM :: Bit -- Isochronous OUT packet dropped interrupt mask
ENUMDNEM :: Bit -- Enumeration done mask
USBRST :: Bit -- USB reset mask
USBSUSPM :: Bit -- USB suspend mask
ESUSPM :: Bit -- Early suspend mask
_ :: Bits 2 -- (Reserved)
GONAKEFFM :: Bit -- Global OUT NAK effective mask
GINAKEFFM :: Bit -- Global non-periodic IN NAK effective mask
NPTXFEM :: Bit -- Non-periodic TxFIFO empty mask
RXFLVLM :: Bit -- Receive FIFO non-empty mask
SOFM :: Bit -- Start of frame mask
OTGINT :: Bit -- OTG interrupt mask
MMISM :: Bit -- Mode mismatch interrupt mask
_ :: Bit -- (Reserved)
GRXSTSR_Device 0x1c - OTG_FS Receive status debug read(Device mode)
_ :: Bits 7 -- (Reserved)
FRMNUM :: Bits 4 -- Frame number
PKTSTS :: Bits 4 -- Packet status
DPID :: Bits 2 -- Data PID
BCNT :: Bits 11 -- Byte count
EPNUM :: Bits 4 -- Endpoint number
GRXSTSR_Host 0x1c - OTG status debug read (host mode)
_ :: Bits 11 -- (Reserved)
PKTSTS :: Bits 4 -- Packet status
DPID :: Bits 2 -- Data PID
BCNT :: Bits 11 -- Byte count
CHNUM :: Bits 4 -- Channel number
GRXSTSP_Device 0x20 - OTG status read and pop (device mode)
_ :: Bits 7 -- (Reserved)
FRMNUM :: Bits 4 -- Frame number
PKTSTS :: Bits 4 -- Packet status
DPID :: Bits 2 -- Data PID
BCNT :: Bits 11 -- Byte count
EPNUM :: Bits 4 -- Endpoint number
GRXSTSP_Host 0x20 - OTG status read and pop (host mode)
_ :: Bits 11 -- (Reserved)
PKTSTS :: Bits 4 -- Packet status
DPID :: Bits 2 -- Data PID
BCNT :: Bits 11 -- Byte count
CHNUM :: Bits 4 -- Channel number
GRXFSIZ 0x24 - OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
_ :: Bits 16 -- (Reserved)
RXFD :: Bits 16 -- RxFIFO depth
DIEPTXF0 0x28 - OTG_FS non-periodic transmit FIFO size register (Device mode)
TX0FD :: Bits 16 -- Endpoint 0 TxFIFO depth
TX0FSA :: Bits 16 -- Endpoint 0 transmit RAM start address
HNPTXFSIZ 0x28 - OTG_FS non-periodic transmit FIFO size register (Host mode)
NPTXFD :: Bits 16 -- Non-periodic TxFIFO depth
NPTXFSA :: Bits 16 -- Non-periodic transmit RAM start address
GNPTXSTS 0x2c - OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)
_ :: Bit -- (Reserved)
NPTXQTOP :: Bits 7 -- Top of the non-periodic transmit request queue
NPTQXSAV :: Bits 8 -- Non-periodic transmit request queue space available
NPTXFSAV :: Bits 16 -- Non-periodic TxFIFO space available
GCCFG 0x38 - OTG_FS general core configuration register (OTG_FS_GCCFG)
_ :: Bits 10 -- (Reserved)
NOVBUSSENS :: Bit -- Vbus sensing disable option
SOFOUTEN :: Bit -- SOF output enable
VBUSBSEN :: Bit -- Enable the VBUS sensing device
VBUSASEN :: Bit -- Enable the VBUS sensing device
_ :: Bit -- (Reserved)
PWRDWN :: Bit -- Power down
_ :: Bits 16 -- (Reserved)
CID 0x3c - core ID register
PRODUCT_ID :: Bits 32 -- Product ID field
HPTXFSIZ 0x100 - OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
PTXFSIZ :: Bits 16 -- Host periodic TxFIFO depth
PTXSA :: Bits 16 -- Host periodic TxFIFO start address
DIEPTXF1 0x104 - OTF_FS device IN endpoint transmit FIFO size register
INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth
INEPTXSA :: Bits 16 -- IN endpoint FIFO2 transmit RAM start address
DIEPTXF2 0x108 - OTF_FS device IN endpoint transmit FIFO size register
INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth
INEPTXSA :: Bits 16 -- IN endpoint FIFO2 transmit RAM start address
DIEPTXF3 0x10c - OTF_FS device IN endpoint transmit FIFO size register
INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth
INEPTXSA :: Bits 16 -- IN endpoint FIFO2 transmit RAM start address
DIEPTXF4 0x110 - OTF_FS device IN endpoint transmit FIFO size register
INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth
INEPTXSA :: Bits 16 -- IN endpoint FIFO2 transmit RAM start address
DIEPTXF5 0x114 - OTF_FS device IN endpoint transmit FIFO size register
INEPTXFD :: Bits 16 -- IN endpoint TxFIFO depth
INEPTXSA :: Bits 16 -- IN endpoint FIFO2 transmit RAM start address
OTG_FS_HOST 0x50000400 USB on the go full speed
HCFG 0x0 - OTG_FS host configuration register (OTG_FS_HCFG)
_ :: Bits 29 -- (Reserved)
FSLSS :: Bit -- FS- and LS-only support
FSLSPCS :: Bits 2 -- FS/LS PHY clock select
HFIR 0x4 - OTG_FS Host frame interval register
_ :: Bits 16 -- (Reserved)
FRIVL :: Bits 16 -- Frame interval
HFNUM 0x8 - OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)
FTREM :: Bits 16 -- Frame time remaining
FRNUM :: Bits 16 -- Frame number
HPTXSTS 0x10 - OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
PTXQTOP :: Bits 8 -- Top of the periodic transmit request queue
PTXQSAV :: Bits 8 -- Periodic transmit request queue space available
PTXFSAVL :: Bits 16 -- Periodic transmit data FIFO space available
HAINT 0x14 - OTG_FS Host all channels interrupt register
_ :: Bits 16 -- (Reserved)
HAINT :: Bits 16 -- Channel interrupts
HAINTMSK 0x18 - OTG_FS host all channels interrupt mask register
_ :: Bits 16 -- (Reserved)
HAINTM :: Bits 16 -- Channel interrupt mask
HPRT 0x40 - OTG_FS host port control and status register (OTG_FS_HPRT)
_ :: Bits 13 -- (Reserved)
PSPD :: Bits 2 -- Port speed
PTCTL :: Bits 4 -- Port test control
PPWR :: Bit -- Port power
PLSTS :: Bits 2 -- Port line status
_ :: Bit -- (Reserved)
PRST :: Bit -- Port reset
PSUSP :: Bit -- Port suspend
PRES :: Bit -- Port resume
POCCHNG :: Bit -- Port overcurrent change
POCA :: Bit -- Port overcurrent active
PENCHNG :: Bit -- Port enable/disable change
PENA :: Bit -- Port enable
PCDET :: Bit -- Port connect detected
PCSTS :: Bit -- Port connect status
CHAR 0x100 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MCNT :: Bits 2 -- Multicount
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x108 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
_ :: Bit -- (Reserved)
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
_ :: Bit -- (Reserved)
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x10c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
_ :: Bit -- (Reserved)
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x110 - OTG_FS host channel-0 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CHAR 0x120 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MCNT :: Bits 2 -- Multicount
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x128 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
_ :: Bit -- (Reserved)
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
_ :: Bit -- (Reserved)
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x12c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
_ :: Bit -- (Reserved)
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x130 - OTG_FS host channel-0 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CHAR 0x140 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MCNT :: Bits 2 -- Multicount
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x148 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
_ :: Bit -- (Reserved)
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
_ :: Bit -- (Reserved)
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x14c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
_ :: Bit -- (Reserved)
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x150 - OTG_FS host channel-0 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CHAR 0x160 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MCNT :: Bits 2 -- Multicount
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x168 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
_ :: Bit -- (Reserved)
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
_ :: Bit -- (Reserved)
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x16c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
_ :: Bit -- (Reserved)
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x170 - OTG_FS host channel-0 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CHAR 0x180 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MCNT :: Bits 2 -- Multicount
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x188 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
_ :: Bit -- (Reserved)
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
_ :: Bit -- (Reserved)
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x18c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
_ :: Bit -- (Reserved)
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x190 - OTG_FS host channel-0 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CHAR 0x1a0 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MCNT :: Bits 2 -- Multicount
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x1a8 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
_ :: Bit -- (Reserved)
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
_ :: Bit -- (Reserved)
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x1ac - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
_ :: Bit -- (Reserved)
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x1b0 - OTG_FS host channel-0 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CHAR 0x1c0 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MCNT :: Bits 2 -- Multicount
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x1c8 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
_ :: Bit -- (Reserved)
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
_ :: Bit -- (Reserved)
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x1cc - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
_ :: Bit -- (Reserved)
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x1d0 - OTG_FS host channel-0 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CHAR 0x1e0 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MCNT :: Bits 2 -- Multicount
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x1e8 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
_ :: Bit -- (Reserved)
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
_ :: Bit -- (Reserved)
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x1ec - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
_ :: Bit -- (Reserved)
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x1f0 - OTG_FS host channel-0 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CHAR 0x200 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MCNT :: Bits 2 -- Multicount
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x208 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
_ :: Bit -- (Reserved)
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
_ :: Bit -- (Reserved)
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x20c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
_ :: Bit -- (Reserved)
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x210 - OTG_FS host channel-0 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CHAR 0x220 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MCNT :: Bits 2 -- Multicount
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x228 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
_ :: Bit -- (Reserved)
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
_ :: Bit -- (Reserved)
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x22c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
_ :: Bit -- (Reserved)
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x230 - OTG_FS host channel-0 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CHAR 0x240 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MCNT :: Bits 2 -- Multicount
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x248 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
_ :: Bit -- (Reserved)
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
_ :: Bit -- (Reserved)
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x24c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
_ :: Bit -- (Reserved)
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x250 - OTG_FS host channel-0 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CHAR 0x260 - OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
CHENA :: Bit -- Channel enable
CHDIS :: Bit -- Channel disable
ODDFRM :: Bit -- Odd frame
DAD :: Bits 7 -- Device address
MCNT :: Bits 2 -- Multicount
EPTYP :: Bits 2 -- Endpoint type
LSDEV :: Bit -- Low-speed device
_ :: Bit -- (Reserved)
EPDIR :: Bit -- Endpoint direction
EPNUM :: Bits 4 -- Endpoint number
MPSIZ :: Bits 11 -- Maximum packet size
INT 0x268 - OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
_ :: Bits 21 -- (Reserved)
DTERR :: Bit -- Data toggle error
FRMOR :: Bit -- Frame overrun
BBERR :: Bit -- Babble error
TXERR :: Bit -- Transaction error
_ :: Bit -- (Reserved)
ACK :: Bit -- ACK response received/transmitted interrupt
NAK :: Bit -- NAK response received interrupt
STALL :: Bit -- STALL response received interrupt
_ :: Bit -- (Reserved)
CHH :: Bit -- Channel halted
XFRC :: Bit -- Transfer completed
INTMSK 0x26c - OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
_ :: Bits 21 -- (Reserved)
DTERRM :: Bit -- Data toggle error mask
FRMORM :: Bit -- Frame overrun mask
BBERRM :: Bit -- Babble error mask
TXERRM :: Bit -- Transaction error mask
NYET :: Bit -- response received interrupt mask
ACKM :: Bit -- ACK response received/transmitted interrupt mask
NAKM :: Bit -- NAK response received interrupt mask
STALLM :: Bit -- STALL response received interrupt mask
_ :: Bit -- (Reserved)
CHHM :: Bit -- Channel halted mask
XFRCM :: Bit -- Transfer completed mask
TSIZ 0x270 - OTG_FS host channel-0 transfer size register
_ :: Bit -- (Reserved)
DPID :: Bits 2 -- Data PID
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
OTG_FS_DEVICE 0x50000800 USB on the go full speed
DCFG 0x0 - OTG_FS device configuration register (OTG_FS_DCFG)
_ :: Bits 19 -- (Reserved)
PFIVL :: Bits 2 -- Periodic frame interval
DAD :: Bits 7 -- Device address
_ :: Bit -- (Reserved)
NZLSOHSK :: Bit -- Non-zero-length status OUT handshake
DSPD :: Bits 2 -- Device speed
DCTL 0x4 - OTG_FS device control register (OTG_FS_DCTL)
_ :: Bits 20 -- (Reserved)
POPRGDNE :: Bit -- Power-on programming done
CGONAK :: Bit -- Clear global OUT NAK
SGONAK :: Bit -- Set global OUT NAK
CGINAK :: Bit -- Clear global IN NAK
SGINAK :: Bit -- Set global IN NAK
TCTL :: Bits 3 -- Test control
GONSTS :: Bit -- Global OUT NAK status
GINSTS :: Bit -- Global IN NAK status
SDIS :: Bit -- Soft disconnect
RWUSIG :: Bit -- Remote wakeup signaling
DSTS 0x8 - OTG_FS device status register (OTG_FS_DSTS)
_ :: Bits 10 -- (Reserved)
FNSOF :: Bits 14 -- Frame number of the received SOF
_ :: Bits 4 -- (Reserved)
EERR :: Bit -- Erratic error
ENUMSPD :: Bits 2 -- Enumerated speed
SUSPSTS :: Bit -- Suspend status
DIEPMSK 0x10 - OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
_ :: Bits 25 -- (Reserved)
INEPNEM :: Bit -- IN endpoint NAK effective mask
INEPNMM :: Bit -- IN token received with EP mismatch mask
ITTXFEMSK :: Bit -- IN token received when TxFIFO empty mask
TOM :: Bit -- Timeout condition mask (Non-isochronous endpoints)
_ :: Bit -- (Reserved)
EPDM :: Bit -- Endpoint disabled interrupt mask
XFRCM :: Bit -- Transfer completed interrupt mask
DOEPMSK 0x14 - OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
_ :: Bits 27 -- (Reserved)
OTEPDM :: Bit -- OUT token received when endpoint disabled mask
STUPM :: Bit -- SETUP phase done mask
_ :: Bit -- (Reserved)
EPDM :: Bit -- Endpoint disabled interrupt mask
XFRCM :: Bit -- Transfer completed interrupt mask
DAINT 0x18 - OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
OEPINT :: Bits 16 -- OUT endpoint interrupt bits
IEPINT :: Bits 16 -- IN endpoint interrupt bits
DAINTMSK 0x1c - OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
OEPM :: Bits 16 -- OUT EP interrupt mask bits
IEPM :: Bits 16 -- IN EP interrupt mask bits
DVBUSDIS 0x28 - OTG_FS device VBUS discharge time register
_ :: Bits 16 -- (Reserved)
VBUSDT :: Bits 16 -- Device VBUS discharge time
DVBUSPULSE 0x2c - OTG_FS device VBUS pulsing time register
_ :: Bits 20 -- (Reserved)
DVBUSP :: Bits 12 -- Device VBUS pulsing time
DIEPEMPMSK 0x34 - OTG_FS device IN endpoint FIFO empty interrupt mask register
_ :: Bits 16 -- (Reserved)
INEPTXFEM :: Bits 16 -- IN EP Tx FIFO empty interrupt mask bits
CTL 0x100 - OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
EPENA :: Bit -- Endpoint enable
EPDIS :: Bit -- Endpoint disable
_ :: Bits 2 -- (Reserved)
SNAK :: Bit -- Set NAK
CNAK :: Bit -- Clear NAK
TXFNUM :: Bits 4 -- TxFIFO number
STALL :: Bit -- STALL handshake
_ :: Bit -- (Reserved)
EPTYP :: Bits 2 -- Endpoint type
NAKSTS :: Bit -- NAK status
_ :: Bit -- (Reserved)
USBAEP :: Bit -- USB active endpoint
_ :: Bits 13 -- (Reserved)
MPSIZ :: Bits 2 -- Maximum packet size
INT 0x108 - device endpoint-x interrupt register
_ :: Bits 24 -- (Reserved)
TXFE :: Bit -- TXFE
INEPNE :: Bit -- INEPNE
_ :: Bit -- (Reserved)
ITTXFE :: Bit -- ITTXFE
TOC :: Bit -- TOC
_ :: Bit -- (Reserved)
EPDISD :: Bit -- EPDISD
XFRC :: Bit -- XFRC
TSIZ 0x110 - device endpoint-0 transfer size register
_ :: Bits 11 -- (Reserved)
PKTCNT :: Bits 2 -- Packet count
_ :: Bits 12 -- (Reserved)
XFRSIZ :: Bits 7 -- Transfer size
TXFSTS 0x118 - OTG_FS device IN endpoint transmit FIFO status register
_ :: Bits 16 -- (Reserved)
INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space available
CTL 0x120 - OTG device endpoint-1 control register
EPENA :: Bit -- EPENA
EPDIS :: Bit -- EPDIS
SODDFRM_SD1PID :: Bit -- SODDFRM/SD1PID
SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM
SNAK :: Bit -- SNAK
CNAK :: Bit -- CNAK
TXFNUM :: Bits 4 -- TXFNUM
STALL :: Bit -- STALL handshake
_ :: Bit -- (Reserved)
EPTYP :: Bits 2 -- EPTYP
NAKSTS :: Bit -- NAKSTS
EONUM_DPID :: Bit -- EONUM/DPID
USBAEP :: Bit -- USBAEP
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- MPSIZ
INT 0x128 - device endpoint-1 interrupt register
_ :: Bits 24 -- (Reserved)
TXFE :: Bit -- TXFE
INEPNE :: Bit -- INEPNE
_ :: Bit -- (Reserved)
ITTXFE :: Bit -- ITTXFE
TOC :: Bit -- TOC
_ :: Bit -- (Reserved)
EPDISD :: Bit -- EPDISD
XFRC :: Bit -- XFRC
TSIZ 0x130 - device endpoint-1 transfer size register
_ :: Bit -- (Reserved)
MCNT :: Bits 2 -- Multi count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
TXFSTS 0x138 - OTG_FS device IN endpoint transmit FIFO status register
_ :: Bits 16 -- (Reserved)
INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space available
CTL 0x140 - OTG device endpoint-1 control register
EPENA :: Bit -- EPENA
EPDIS :: Bit -- EPDIS
SODDFRM_SD1PID :: Bit -- SODDFRM/SD1PID
SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM
SNAK :: Bit -- SNAK
CNAK :: Bit -- CNAK
TXFNUM :: Bits 4 -- TXFNUM
STALL :: Bit -- STALL handshake
_ :: Bit -- (Reserved)
EPTYP :: Bits 2 -- EPTYP
NAKSTS :: Bit -- NAKSTS
EONUM_DPID :: Bit -- EONUM/DPID
USBAEP :: Bit -- USBAEP
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- MPSIZ
INT 0x148 - device endpoint-1 interrupt register
_ :: Bits 24 -- (Reserved)
TXFE :: Bit -- TXFE
INEPNE :: Bit -- INEPNE
_ :: Bit -- (Reserved)
ITTXFE :: Bit -- ITTXFE
TOC :: Bit -- TOC
_ :: Bit -- (Reserved)
EPDISD :: Bit -- EPDISD
XFRC :: Bit -- XFRC
TSIZ 0x150 - device endpoint-1 transfer size register
_ :: Bit -- (Reserved)
MCNT :: Bits 2 -- Multi count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
TXFSTS 0x158 - OTG_FS device IN endpoint transmit FIFO status register
_ :: Bits 16 -- (Reserved)
INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space available
CTL 0x160 - OTG device endpoint-1 control register
EPENA :: Bit -- EPENA
EPDIS :: Bit -- EPDIS
SODDFRM_SD1PID :: Bit -- SODDFRM/SD1PID
SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM
SNAK :: Bit -- SNAK
CNAK :: Bit -- CNAK
TXFNUM :: Bits 4 -- TXFNUM
STALL :: Bit -- STALL handshake
_ :: Bit -- (Reserved)
EPTYP :: Bits 2 -- EPTYP
NAKSTS :: Bit -- NAKSTS
EONUM_DPID :: Bit -- EONUM/DPID
USBAEP :: Bit -- USBAEP
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- MPSIZ
INT 0x168 - device endpoint-1 interrupt register
_ :: Bits 24 -- (Reserved)
TXFE :: Bit -- TXFE
INEPNE :: Bit -- INEPNE
_ :: Bit -- (Reserved)
ITTXFE :: Bit -- ITTXFE
TOC :: Bit -- TOC
_ :: Bit -- (Reserved)
EPDISD :: Bit -- EPDISD
XFRC :: Bit -- XFRC
TSIZ 0x170 - device endpoint-1 transfer size register
_ :: Bit -- (Reserved)
MCNT :: Bits 2 -- Multi count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
TXFSTS 0x178 - OTG_FS device IN endpoint transmit FIFO status register
_ :: Bits 16 -- (Reserved)
INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space available
CTL 0x180 - OTG device endpoint-1 control register
EPENA :: Bit -- EPENA
EPDIS :: Bit -- EPDIS
SODDFRM_SD1PID :: Bit -- SODDFRM/SD1PID
SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM
SNAK :: Bit -- SNAK
CNAK :: Bit -- CNAK
TXFNUM :: Bits 4 -- TXFNUM
STALL :: Bit -- STALL handshake
_ :: Bit -- (Reserved)
EPTYP :: Bits 2 -- EPTYP
NAKSTS :: Bit -- NAKSTS
EONUM_DPID :: Bit -- EONUM/DPID
USBAEP :: Bit -- USBAEP
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- MPSIZ
INT 0x188 - device endpoint-1 interrupt register
_ :: Bits 24 -- (Reserved)
TXFE :: Bit -- TXFE
INEPNE :: Bit -- INEPNE
_ :: Bit -- (Reserved)
ITTXFE :: Bit -- ITTXFE
TOC :: Bit -- TOC
_ :: Bit -- (Reserved)
EPDISD :: Bit -- EPDISD
XFRC :: Bit -- XFRC
TSIZ 0x190 - device endpoint-1 transfer size register
_ :: Bit -- (Reserved)
MCNT :: Bits 2 -- Multi count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
TXFSTS 0x198 - OTG_FS device IN endpoint transmit FIFO status register
_ :: Bits 16 -- (Reserved)
INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space available
CTL 0x1a0 - OTG device endpoint-1 control register
EPENA :: Bit -- EPENA
EPDIS :: Bit -- EPDIS
SODDFRM_SD1PID :: Bit -- SODDFRM/SD1PID
SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM
SNAK :: Bit -- SNAK
CNAK :: Bit -- CNAK
TXFNUM :: Bits 4 -- TXFNUM
STALL :: Bit -- STALL handshake
_ :: Bit -- (Reserved)
EPTYP :: Bits 2 -- EPTYP
NAKSTS :: Bit -- NAKSTS
EONUM_DPID :: Bit -- EONUM/DPID
USBAEP :: Bit -- USBAEP
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- MPSIZ
INT 0x1a8 - device endpoint-1 interrupt register
_ :: Bits 24 -- (Reserved)
TXFE :: Bit -- TXFE
INEPNE :: Bit -- INEPNE
_ :: Bit -- (Reserved)
ITTXFE :: Bit -- ITTXFE
TOC :: Bit -- TOC
_ :: Bit -- (Reserved)
EPDISD :: Bit -- EPDISD
XFRC :: Bit -- XFRC
TSIZ 0x1b0 - device endpoint-1 transfer size register
_ :: Bit -- (Reserved)
MCNT :: Bits 2 -- Multi count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
TXFSTS 0x1b8 - OTG_FS device IN endpoint transmit FIFO status register
_ :: Bits 16 -- (Reserved)
INEPTFSAV :: Bits 16 -- IN endpoint TxFIFO space available
CTL 0x300 - device endpoint-0 control register
EPENA :: Bit -- EPENA
EPDIS :: Bit -- EPDIS
_ :: Bits 2 -- (Reserved)
SNAK :: Bit -- SNAK
CNAK :: Bit -- CNAK
_ :: Bits 4 -- (Reserved)
STALL :: Bit -- STALL handshake
SNPM :: Bit -- SNPM
EPTYP :: Bits 2 -- EPTYP
NAKSTS :: Bit -- NAKSTS
_ :: Bit -- (Reserved)
USBAEP :: Bit -- USBAEP
_ :: Bits 13 -- (Reserved)
MPSIZ :: Bits 2 -- MPSIZ
INT 0x308 - device endpoint-0 interrupt register
_ :: Bits 25 -- (Reserved)
B2BSTUP :: Bit -- B2BSTUP
_ :: Bit -- (Reserved)
OTEPDIS :: Bit -- OTEPDIS
STUP :: Bit -- STUP
_ :: Bit -- (Reserved)
EPDISD :: Bit -- EPDISD
XFRC :: Bit -- XFRC
TSIZ 0x310 - device OUT endpoint-0 transfer size register
_ :: Bit -- (Reserved)
STUPCNT :: Bits 2 -- SETUP packet count
_ :: Bits 9 -- (Reserved)
PKTCNT :: Bit -- Packet count
_ :: Bits 12 -- (Reserved)
XFRSIZ :: Bits 7 -- Transfer size
CTL 0x320 - device endpoint-1 control register
EPENA :: Bit -- EPENA
EPDIS :: Bit -- EPDIS
SODDFRM :: Bit -- SODDFRM
SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM
SNAK :: Bit -- SNAK
CNAK :: Bit -- CNAK
_ :: Bits 4 -- (Reserved)
STALL :: Bit -- STALL handshake
SNPM :: Bit -- SNPM
EPTYP :: Bits 2 -- EPTYP
NAKSTS :: Bit -- NAKSTS
EONUM_DPID :: Bit -- EONUM/DPID
USBAEP :: Bit -- USBAEP
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- MPSIZ
INT 0x328 - device endpoint-1 interrupt register
_ :: Bits 25 -- (Reserved)
B2BSTUP :: Bit -- B2BSTUP
_ :: Bit -- (Reserved)
OTEPDIS :: Bit -- OTEPDIS
STUP :: Bit -- STUP
_ :: Bit -- (Reserved)
EPDISD :: Bit -- EPDISD
XFRC :: Bit -- XFRC
TSIZ 0x330 - device OUT endpoint-1 transfer size register
_ :: Bit -- (Reserved)
RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CTL 0x340 - device endpoint-1 control register
EPENA :: Bit -- EPENA
EPDIS :: Bit -- EPDIS
SODDFRM :: Bit -- SODDFRM
SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM
SNAK :: Bit -- SNAK
CNAK :: Bit -- CNAK
_ :: Bits 4 -- (Reserved)
STALL :: Bit -- STALL handshake
SNPM :: Bit -- SNPM
EPTYP :: Bits 2 -- EPTYP
NAKSTS :: Bit -- NAKSTS
EONUM_DPID :: Bit -- EONUM/DPID
USBAEP :: Bit -- USBAEP
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- MPSIZ
INT 0x348 - device endpoint-1 interrupt register
_ :: Bits 25 -- (Reserved)
B2BSTUP :: Bit -- B2BSTUP
_ :: Bit -- (Reserved)
OTEPDIS :: Bit -- OTEPDIS
STUP :: Bit -- STUP
_ :: Bit -- (Reserved)
EPDISD :: Bit -- EPDISD
XFRC :: Bit -- XFRC
TSIZ 0x350 - device OUT endpoint-1 transfer size register
_ :: Bit -- (Reserved)
RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CTL 0x360 - device endpoint-1 control register
EPENA :: Bit -- EPENA
EPDIS :: Bit -- EPDIS
SODDFRM :: Bit -- SODDFRM
SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM
SNAK :: Bit -- SNAK
CNAK :: Bit -- CNAK
_ :: Bits 4 -- (Reserved)
STALL :: Bit -- STALL handshake
SNPM :: Bit -- SNPM
EPTYP :: Bits 2 -- EPTYP
NAKSTS :: Bit -- NAKSTS
EONUM_DPID :: Bit -- EONUM/DPID
USBAEP :: Bit -- USBAEP
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- MPSIZ
INT 0x368 - device endpoint-1 interrupt register
_ :: Bits 25 -- (Reserved)
B2BSTUP :: Bit -- B2BSTUP
_ :: Bit -- (Reserved)
OTEPDIS :: Bit -- OTEPDIS
STUP :: Bit -- STUP
_ :: Bit -- (Reserved)
EPDISD :: Bit -- EPDISD
XFRC :: Bit -- XFRC
TSIZ 0x370 - device OUT endpoint-1 transfer size register
_ :: Bit -- (Reserved)
RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CTL 0x380 - device endpoint-1 control register
EPENA :: Bit -- EPENA
EPDIS :: Bit -- EPDIS
SODDFRM :: Bit -- SODDFRM
SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM
SNAK :: Bit -- SNAK
CNAK :: Bit -- CNAK
_ :: Bits 4 -- (Reserved)
STALL :: Bit -- STALL handshake
SNPM :: Bit -- SNPM
EPTYP :: Bits 2 -- EPTYP
NAKSTS :: Bit -- NAKSTS
EONUM_DPID :: Bit -- EONUM/DPID
USBAEP :: Bit -- USBAEP
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- MPSIZ
INT 0x388 - device endpoint-1 interrupt register
_ :: Bits 25 -- (Reserved)
B2BSTUP :: Bit -- B2BSTUP
_ :: Bit -- (Reserved)
OTEPDIS :: Bit -- OTEPDIS
STUP :: Bit -- STUP
_ :: Bit -- (Reserved)
EPDISD :: Bit -- EPDISD
XFRC :: Bit -- XFRC
TSIZ 0x390 - device OUT endpoint-1 transfer size register
_ :: Bit -- (Reserved)
RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
CTL 0x3a0 - device endpoint-1 control register
EPENA :: Bit -- EPENA
EPDIS :: Bit -- EPDIS
SODDFRM :: Bit -- SODDFRM
SD0PID_SEVNFRM :: Bit -- SD0PID/SEVNFRM
SNAK :: Bit -- SNAK
CNAK :: Bit -- CNAK
_ :: Bits 4 -- (Reserved)
STALL :: Bit -- STALL handshake
SNPM :: Bit -- SNPM
EPTYP :: Bits 2 -- EPTYP
NAKSTS :: Bit -- NAKSTS
EONUM_DPID :: Bit -- EONUM/DPID
USBAEP :: Bit -- USBAEP
_ :: Bits 4 -- (Reserved)
MPSIZ :: Bits 11 -- MPSIZ
INT 0x3a8 - device endpoint-1 interrupt register
_ :: Bits 25 -- (Reserved)
B2BSTUP :: Bit -- B2BSTUP
_ :: Bit -- (Reserved)
OTEPDIS :: Bit -- OTEPDIS
STUP :: Bit -- STUP
_ :: Bit -- (Reserved)
EPDISD :: Bit -- EPDISD
XFRC :: Bit -- XFRC
TSIZ 0x3b0 - device OUT endpoint-1 transfer size register
_ :: Bit -- (Reserved)
RXDPID_STUPCNT :: Bits 2 -- Received data PID/SETUP packet count
PKTCNT :: Bits 10 -- Packet count
XFRSIZ :: Bits 19 -- Transfer size
OTG_FS_PWRCLK 0x50000e00 USB on the go full speed
PCGCCTL 0x0 - OTG_FS power and clock gating control register
_ :: Bits 27 -- (Reserved)
PHYSUSP :: Bit -- PHY Suspended
_ :: Bits 2 -- (Reserved)
GATEHCLK :: Bit -- Gate HCLK
STPPCLK :: Bit -- Stop PHY clock
DCMI 0x50050000 Digital camera interface
CR 0x0 - control register 1
_ :: Bits 17 -- (Reserved)
ENABLE :: Bit -- DCMI enable
_ :: Bits 2 -- (Reserved)
EDM :: Bits 2 -- Extended data mode
FCRC :: Bits 2 -- Frame capture rate control
VSPOL :: Bit -- Vertical synchronization polarity
HSPOL :: Bit -- Horizontal synchronization polarity
PCKPOL :: Bit -- Pixel clock polarity
ESS :: Bit -- Embedded synchronization select
JPEG :: Bit -- JPEG format
CROP :: Bit -- Crop feature
CM :: Bit -- Capture mode
CAPTURE :: Bit -- Capture enable
SR 0x4 - status register
_ :: Bits 29 -- (Reserved)
FNE :: Bit -- FIFO not empty
VSYNC :: Bit -- VSYNC
HSYNC :: Bit -- HSYNC
RIS 0x8 - raw interrupt status register
_ :: Bits 27 -- (Reserved)
LINE_RIS :: Bit -- Line raw interrupt status
VSYNC_RIS :: Bit -- VSYNC raw interrupt status
ERR_RIS :: Bit -- Synchronization error raw interrupt status
OVR_RIS :: Bit -- Overrun raw interrupt status
FRAME_RIS :: Bit -- Capture complete raw interrupt status
IER 0xc - interrupt enable register
_ :: Bits 27 -- (Reserved)
LINE_IE :: Bit -- Line interrupt enable
VSYNC_IE :: Bit -- VSYNC interrupt enable
ERR_IE :: Bit -- Synchronization error interrupt enable
OVR_IE :: Bit -- Overrun interrupt enable
FRAME_IE :: Bit -- Capture complete interrupt enable
MIS 0x10 - masked interrupt status register
_ :: Bits 27 -- (Reserved)
LINE_MIS :: Bit -- Line masked interrupt status
VSYNC_MIS :: Bit -- VSYNC masked interrupt status
ERR_MIS :: Bit -- Synchronization error masked interrupt status
OVR_MIS :: Bit -- Overrun masked interrupt status
FRAME_MIS :: Bit -- Capture complete masked interrupt status
ICR 0x14 - interrupt clear register
_ :: Bits 27 -- (Reserved)
LINE_ISC :: Bit -- line interrupt status clear
VSYNC_ISC :: Bit -- Vertical synch interrupt status clear
ERR_ISC :: Bit -- Synchronization error interrupt status clear
OVR_ISC :: Bit -- Overrun interrupt status clear
FRAME_ISC :: Bit -- Capture complete interrupt status clear
ESCR 0x18 - embedded synchronization code register
FEC :: Bits 8 -- Frame end delimiter code
LEC :: Bits 8 -- Line end delimiter code
LSC :: Bits 8 -- Line start delimiter code
FSC :: Bits 8 -- Frame start delimiter code
ESUR 0x1c - embedded synchronization unmask register
FEU :: Bits 8 -- Frame end delimiter unmask
LEU :: Bits 8 -- Line end delimiter unmask
LSU :: Bits 8 -- Line start delimiter unmask
FSU :: Bits 8 -- Frame start delimiter unmask
CWSTRT 0x20 - crop window start
_ :: Bits 3 -- (Reserved)
VST :: Bits 13 -- Vertical start line count
_ :: Bits 2 -- (Reserved)
HOFFCNT :: Bits 14 -- Horizontal offset count
CWSIZE 0x24 - crop window size
_ :: Bits 2 -- (Reserved)
VLINE :: Bits 14 -- Vertical line count
_ :: Bits 2 -- (Reserved)
CAPCNT :: Bits 14 -- Capture count
DR 0x28 - data register
Byte3 :: Bits 8 -- Data byte 3
Byte2 :: Bits 8 -- Data byte 2
Byte1 :: Bits 8 -- Data byte 1
Byte0 :: Bits 8 -- Data byte 0
CRYP 0x50060000 Cryptographic processor
CR 0x0 - control register
_ :: Bits 12 -- (Reserved)
ALGOMODE3 :: Bit -- ALGOMODE
_ :: Bit -- (Reserved)
GCM_CCMPH :: Bits 2 -- GCM_CCMPH
CRYPEN :: Bit -- Cryptographic processor enable
FFLUSH :: Bit -- FIFO flush
_ :: Bits 4 -- (Reserved)
KEYSIZE :: Bits 2 -- Key size selection (AES mode only)
DATATYPE :: Bits 2 -- Data type selection
ALGOMODE0 :: Bits 3 -- Algorithm mode
ALGODIR :: Bit -- Algorithm direction
_ :: Bits 2 -- (Reserved)
SR 0x4 - status register
_ :: Bits 27 -- (Reserved)
BUSY :: Bit -- Busy bit
OFFU :: Bit -- Output FIFO full
OFNE :: Bit -- Output FIFO not empty
IFNF :: Bit -- Input FIFO not full
IFEM :: Bit -- Input FIFO empty
DIN 0x8 - data input register
DATAIN :: Bits 32 -- Data input
DOUT 0xc - data output register
DATAOUT :: Bits 32 -- Data output
DMACR 0x10 - DMA control register
_ :: Bits 30 -- (Reserved)
DOEN :: Bit -- DMA output enable
DIEN :: Bit -- DMA input enable
IMSCR 0x14 - interrupt mask set/clear register
_ :: Bits 30 -- (Reserved)
OUTIM :: Bit -- Output FIFO service interrupt mask
INIM :: Bit -- Input FIFO service interrupt mask
RISR 0x18 - raw interrupt status register
_ :: Bits 30 -- (Reserved)
OUTRIS :: Bit -- Output FIFO service raw interrupt status
INRIS :: Bit -- Input FIFO service raw interrupt status
MISR 0x1c - masked interrupt status register
_ :: Bits 30 -- (Reserved)
OUTMIS :: Bit -- Output FIFO service masked interrupt status
INMIS :: Bit -- Input FIFO service masked interrupt status
KLR 0x20 - key registers
b2 :: Bits 32 -- b224
KRR 0x24 - key registers
b :: Bits 32 -- b192
KLR 0x28 - key registers
b2 :: Bits 32 -- b224
KRR 0x2c - key registers
b :: Bits 32 -- b192
KLR 0x30 - key registers
b2 :: Bits 32 -- b224
KRR 0x34 - key registers
b :: Bits 32 -- b192
KLR 0x38 - key registers
b2 :: Bits 32 -- b224
KRR 0x3c - key registers
b :: Bits 32 -- b192
IVLR 0x40 - initialization vector registers
IV :: Bits 32 -- IV31
IVRR 0x44 - initialization vector registers
IV :: Bits 32 -- IV63
IVLR 0x48 - initialization vector registers
IV :: Bits 32 -- IV31
IVRR 0x4c - initialization vector registers
IV :: Bits 32 -- IV63
CSGCMCCM0R 0x50 - context swap register
CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R
CSGCMCCM1R 0x54 - context swap register
CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R
CSGCMCCM2R 0x58 - context swap register
CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R
CSGCMCCM3R 0x5c - context swap register
CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R
CSGCMCCM4R 0x60 - context swap register
CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R
CSGCMCCM5R 0x64 - context swap register
CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R
CSGCMCCM6R 0x68 - context swap register
CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R
CSGCMCCM7R 0x6c - context swap register
CSGCMCCM0R :: Bits 32 -- CSGCMCCM0R
CSGCM0R 0x70 - context swap register
CSGCMR :: Bits 32 -- CSGCM0R
CSGCM1R 0x74 - context swap register
CSGCMR :: Bits 32 -- CSGCM0R
CSGCM2R 0x78 - context swap register
CSGCMR :: Bits 32 -- CSGCM0R
CSGCM3R 0x7c - context swap register
CSGCMR :: Bits 32 -- CSGCM0R
CSGCM4R 0x80 - context swap register
CSGCMR :: Bits 32 -- CSGCM0R
CSGCM5R 0x84 - context swap register
CSGCMR :: Bits 32 -- CSGCM0R
CSGCM6R 0x88 - context swap register
CSGCMR :: Bits 32 -- CSGCM0R
CSGCM7R 0x8c - context swap register
CSGCMR :: Bits 32 -- CSGCM0R
HASH 0x50060400 Hash processor
CR 0x0 - control register
_ :: Bits 13 -- (Reserved)
ALGO1 :: Bit -- ALGO
_ :: Bit -- (Reserved)
LKEY :: Bit -- Long key selection
_ :: Bits 2 -- (Reserved)
MDMAT :: Bit -- Multiple DMA Transfers
DINNE :: Bit -- DIN not empty
NBW :: Bits 4 -- Number of words already pushed
ALGO0 :: Bit -- Algorithm selection
MODE :: Bit -- Mode selection
DATATYPE :: Bits 2 -- Data type selection
DMAE :: Bit -- DMA enable
INIT :: Bit -- Initialize message digest calculation
_ :: Bits 2 -- (Reserved)
DIN 0x4 - data input register
DATAIN :: Bits 32 -- Data input
STR 0x8 - start register
_ :: Bits 23 -- (Reserved)
DCAL :: Bit -- Digest calculation
_ :: Bits 3 -- (Reserved)
NBLW :: Bits 5 -- Number of valid bits in the last word of the message
HR0 0xc - digest registers
H :: Bits 32 -- H0
HR1 0x10 - digest registers
H :: Bits 32 -- H0
HR2 0x14 - digest registers
H :: Bits 32 -- H0
HR3 0x18 - digest registers
H :: Bits 32 -- H0
HR4 0x1c - digest registers
H :: Bits 32 -- H0
IMR 0x20 - interrupt enable register
_ :: Bits 30 -- (Reserved)
DCIE :: Bit -- Digest calculation completion interrupt enable
DINIE :: Bit -- Data input interrupt enable
SR 0x24 - status register
_ :: Bits 28 -- (Reserved)
BUSY :: Bit -- Busy bit
DMAS :: Bit -- DMA Status
DCIS :: Bit -- Digest calculation completion interrupt status
DINIS :: Bit -- Data input interrupt status
CSR0 0xf8 - context swap registers
CSR :: Bits 32 -- CSR0
CSR1 0xfc - context swap registers
CSR :: Bits 32 -- CSR0
CSR2 0x100 - context swap registers
CSR :: Bits 32 -- CSR0
CSR3 0x104 - context swap registers
CSR :: Bits 32 -- CSR0
CSR4 0x108 - context swap registers
CSR :: Bits 32 -- CSR0
CSR5 0x10c - context swap registers
CSR :: Bits 32 -- CSR0
CSR6 0x110 - context swap registers
CSR :: Bits 32 -- CSR0
CSR7 0x114 - context swap registers
CSR :: Bits 32 -- CSR0
CSR8 0x118 - context swap registers
CSR :: Bits 32 -- CSR0
CSR9 0x11c - context swap registers
CSR :: Bits 32 -- CSR0
CSR10 0x120 - context swap registers
CSR :: Bits 32 -- CSR0
CSR11 0x124 - context swap registers
CSR :: Bits 32 -- CSR0
CSR12 0x128 - context swap registers
CSR :: Bits 32 -- CSR0
CSR13 0x12c - context swap registers
CSR :: Bits 32 -- CSR0
CSR14 0x130 - context swap registers
CSR :: Bits 32 -- CSR0
CSR15 0x134 - context swap registers
CSR :: Bits 32 -- CSR0
CSR16 0x138 - context swap registers
CSR :: Bits 32 -- CSR0
CSR17 0x13c - context swap registers
CSR :: Bits 32 -- CSR0
CSR18 0x140 - context swap registers
CSR :: Bits 32 -- CSR0
CSR19 0x144 - context swap registers
CSR :: Bits 32 -- CSR0
CSR20 0x148 - context swap registers
CSR :: Bits 32 -- CSR0
CSR21 0x14c - context swap registers
CSR :: Bits 32 -- CSR0
CSR22 0x150 - context swap registers
CSR :: Bits 32 -- CSR0
CSR23 0x154 - context swap registers
CSR :: Bits 32 -- CSR0
CSR24 0x158 - context swap registers
CSR :: Bits 32 -- CSR0
CSR25 0x15c - context swap registers
CSR :: Bits 32 -- CSR0
CSR26 0x160 - context swap registers
CSR :: Bits 32 -- CSR0
CSR27 0x164 - context swap registers
CSR :: Bits 32 -- CSR0
CSR28 0x168 - context swap registers
CSR :: Bits 32 -- CSR0
CSR29 0x16c - context swap registers
CSR :: Bits 32 -- CSR0
CSR30 0x170 - context swap registers
CSR :: Bits 32 -- CSR0
CSR31 0x174 - context swap registers
CSR :: Bits 32 -- CSR0
CSR32 0x178 - context swap registers
CSR :: Bits 32 -- CSR0
CSR33 0x17c - context swap registers
CSR :: Bits 32 -- CSR0
CSR34 0x180 - context swap registers
CSR :: Bits 32 -- CSR0
CSR35 0x184 - context swap registers
CSR :: Bits 32 -- CSR0
CSR36 0x188 - context swap registers
CSR :: Bits 32 -- CSR0
CSR37 0x18c - context swap registers
CSR :: Bits 32 -- CSR0
CSR38 0x190 - context swap registers
CSR :: Bits 32 -- CSR0
CSR39 0x194 - context swap registers
CSR :: Bits 32 -- CSR0
CSR40 0x198 - context swap registers
CSR :: Bits 32 -- CSR0
CSR41 0x19c - context swap registers
CSR :: Bits 32 -- CSR0
CSR42 0x1a0 - context swap registers
CSR :: Bits 32 -- CSR0
CSR43 0x1a4 - context swap registers
CSR :: Bits 32 -- CSR0
CSR44 0x1a8 - context swap registers
CSR :: Bits 32 -- CSR0
CSR45 0x1ac - context swap registers
CSR :: Bits 32 -- CSR0
CSR46 0x1b0 - context swap registers
CSR :: Bits 32 -- CSR0
CSR47 0x1b4 - context swap registers
CSR :: Bits 32 -- CSR0
CSR48 0x1b8 - context swap registers
CSR :: Bits 32 -- CSR0
CSR49 0x1bc - context swap registers
CSR :: Bits 32 -- CSR0
CSR50 0x1c0 - context swap registers
CSR :: Bits 32 -- CSR0
CSR51 0x1c4 - context swap registers
CSR :: Bits 32 -- CSR0
CSR52 0x1c8 - context swap registers
CSR :: Bits 32 -- CSR0
CSR53 0x1cc - context swap registers
CSR :: Bits 32 -- CSR0
HASH_HR0 0x310 - HASH digest register 0
H :: Bits 32 -- H0
HASH_HR1 0x314 - HASH digest register 1
H :: Bits 32 -- H0
HASH_HR2 0x318 - HASH digest register 2
H :: Bits 32 -- H0
HASH_HR3 0x31c - HASH digest register 3
H :: Bits 32 -- H0
HASH_HR4 0x320 - HASH digest register 4
H :: Bits 32 -- H0
HASH_HR5 0x324 - HASH digest register 5
H :: Bits 32 -- H0
HASH_HR6 0x328 - HASH digest register 6
H :: Bits 32 -- H0
HASH_HR7 0x32c - HASH digest register 7
H :: Bits 32 -- H0
RNG 0x50060800 Random number generator
CR 0x0 - control register
_ :: Bits 28 -- (Reserved)
IE :: Bit -- Interrupt enable
RNGEN :: Bit -- Random number generator enable
_ :: Bits 2 -- (Reserved)
SR 0x4 - status register
_ :: Bits 25 -- (Reserved)
SEIS :: Bit -- Seed error interrupt status
CEIS :: Bit -- Clock error interrupt status
_ :: Bits 2 -- (Reserved)
SECS :: Bit -- Seed error current status
CECS :: Bit -- Clock error current status
DRDY :: Bit -- Data ready
DR 0x8 - data register
RNDATA :: Bits 32 -- Random data
FSMC 0xa0000000 Flexible static memory controller
BCR1 0x0 - SRAM/NOR-Flash chip-select control register 1
_ :: Bits 12 -- (Reserved)
CBURSTRW :: Bit -- CBURSTRW
CPSIZE :: Bits 3 -- CRAM page size
ASYNCWAIT :: Bit -- ASYNCWAIT
EXTMOD :: Bit -- EXTMOD
WAITEN :: Bit -- WAITEN
WREN :: Bit -- WREN
WAITCFG :: Bit -- WAITCFG
WRAPMOD :: Bit -- WRAPMOD
WAITPOL :: Bit -- WAITPOL
BURSTEN :: Bit -- BURSTEN
_ :: Bit -- (Reserved)
FACCEN :: Bit -- FACCEN
MWID :: Bits 2 -- MWID
MTYP :: Bits 2 -- MTYP
MUXEN :: Bit -- MUXEN
MBKEN :: Bit -- MBKEN
BTR1 0x4 - SRAM/NOR-Flash chip-select timing register 1
_ :: Bits 2 -- (Reserved)
ACCMOD :: Bits 2 -- ACCMOD
DATLAT :: Bits 4 -- DATLAT
CLKDIV :: Bits 4 -- CLKDIV
BUSTURN :: Bits 4 -- BUSTURN
DATAST :: Bits 8 -- DATAST
ADDHLD :: Bits 4 -- ADDHLD
ADDSET :: Bits 4 -- ADDSET
BCR2 0x8 - SRAM/NOR-Flash chip-select control register 2
_ :: Bits 12 -- (Reserved)
CBURSTRW :: Bit -- CBURSTRW
CPSIZE :: Bits 3 -- CRAM page size
ASYNCWAIT :: Bit -- ASYNCWAIT
EXTMOD :: Bit -- EXTMOD
WAITEN :: Bit -- WAITEN
WREN :: Bit -- WREN
WAITCFG :: Bit -- WAITCFG
WRAPMOD :: Bit -- WRAPMOD
WAITPOL :: Bit -- WAITPOL
BURSTEN :: Bit -- BURSTEN
_ :: Bit -- (Reserved)
FACCEN :: Bit -- FACCEN
MWID :: Bits 2 -- MWID
MTYP :: Bits 2 -- MTYP
MUXEN :: Bit -- MUXEN
MBKEN :: Bit -- MBKEN
BTR2 0xc - SRAM/NOR-Flash chip-select timing register 1
_ :: Bits 2 -- (Reserved)
ACCMOD :: Bits 2 -- ACCMOD
DATLAT :: Bits 4 -- DATLAT
CLKDIV :: Bits 4 -- CLKDIV
BUSTURN :: Bits 4 -- BUSTURN
DATAST :: Bits 8 -- DATAST
ADDHLD :: Bits 4 -- ADDHLD
ADDSET :: Bits 4 -- ADDSET
BCR3 0x10 - SRAM/NOR-Flash chip-select control register 2
_ :: Bits 12 -- (Reserved)
CBURSTRW :: Bit -- CBURSTRW
CPSIZE :: Bits 3 -- CRAM page size
ASYNCWAIT :: Bit -- ASYNCWAIT
EXTMOD :: Bit -- EXTMOD
WAITEN :: Bit -- WAITEN
WREN :: Bit -- WREN
WAITCFG :: Bit -- WAITCFG
WRAPMOD :: Bit -- WRAPMOD
WAITPOL :: Bit -- WAITPOL
BURSTEN :: Bit -- BURSTEN
_ :: Bit -- (Reserved)
FACCEN :: Bit -- FACCEN
MWID :: Bits 2 -- MWID
MTYP :: Bits 2 -- MTYP
MUXEN :: Bit -- MUXEN
MBKEN :: Bit -- MBKEN
BTR3 0x14 - SRAM/NOR-Flash chip-select timing register 1
_ :: Bits 2 -- (Reserved)
ACCMOD :: Bits 2 -- ACCMOD
DATLAT :: Bits 4 -- DATLAT
CLKDIV :: Bits 4 -- CLKDIV
BUSTURN :: Bits 4 -- BUSTURN
DATAST :: Bits 8 -- DATAST
ADDHLD :: Bits 4 -- ADDHLD
ADDSET :: Bits 4 -- ADDSET
BCR4 0x18 - SRAM/NOR-Flash chip-select control register 2
_ :: Bits 12 -- (Reserved)
CBURSTRW :: Bit -- CBURSTRW
CPSIZE :: Bits 3 -- CRAM page size
ASYNCWAIT :: Bit -- ASYNCWAIT
EXTMOD :: Bit -- EXTMOD
WAITEN :: Bit -- WAITEN
WREN :: Bit -- WREN
WAITCFG :: Bit -- WAITCFG
WRAPMOD :: Bit -- WRAPMOD
WAITPOL :: Bit -- WAITPOL
BURSTEN :: Bit -- BURSTEN
_ :: Bit -- (Reserved)
FACCEN :: Bit -- FACCEN
MWID :: Bits 2 -- MWID
MTYP :: Bits 2 -- MTYP
MUXEN :: Bit -- MUXEN
MBKEN :: Bit -- MBKEN
BTR4 0x1c - SRAM/NOR-Flash chip-select timing register 1
_ :: Bits 2 -- (Reserved)
ACCMOD :: Bits 2 -- ACCMOD
DATLAT :: Bits 4 -- DATLAT
CLKDIV :: Bits 4 -- CLKDIV
BUSTURN :: Bits 4 -- BUSTURN
DATAST :: Bits 8 -- DATAST
ADDHLD :: Bits 4 -- ADDHLD
ADDSET :: Bits 4 -- ADDSET
PCR2 0x60 - PC Card/NAND Flash control register 2
_ :: Bits 12 -- (Reserved)
ECCPS :: Bits 3 -- ECCPS
TAR :: Bits 4 -- TAR
TCLR :: Bits 4 -- TCLR
_ :: Bits 2 -- (Reserved)
ECCEN :: Bit -- ECCEN
PWID :: Bits 2 -- PWID
PTYP :: Bit -- PTYP
PBKEN :: Bit -- PBKEN
PWAITEN :: Bit -- PWAITEN
_ :: Bit -- (Reserved)
SR2 0x64 - FIFO status and interrupt register 2
_ :: Bits 25 -- (Reserved)
FEMPT :: Bit -- FEMPT
IFEN :: Bit -- IFEN
ILEN :: Bit -- ILEN
IREN :: Bit -- IREN
IFS :: Bit -- IFS
ILS :: Bit -- ILS
IRS :: Bit -- IRS
PMEM2 0x68 - Common memory space timing register 2
MEMHIZ :: Bits 8 -- MEMHIZx
MEMHOLD :: Bits 8 -- MEMHOLDx
MEMWAIT :: Bits 8 -- MEMWAITx
MEMSET :: Bits 8 -- MEMSETx
PATT2 0x6c - Attribute memory space timing register 2
ATTHIZ :: Bits 8 -- ATTHIZx
ATTHOLD :: Bits 8 -- ATTHOLDx
ATTWAIT :: Bits 8 -- ATTWAITx
ATTSET :: Bits 8 -- ATTSETx
ECCR2 0x74 - ECC result register 2
ECC :: Bits 32 -- ECCx
PCR3 0x80 - PC Card/NAND Flash control register 2
_ :: Bits 12 -- (Reserved)
ECCPS :: Bits 3 -- ECCPS
TAR :: Bits 4 -- TAR
TCLR :: Bits 4 -- TCLR
_ :: Bits 2 -- (Reserved)
ECCEN :: Bit -- ECCEN
PWID :: Bits 2 -- PWID
PTYP :: Bit -- PTYP
PBKEN :: Bit -- PBKEN
PWAITEN :: Bit -- PWAITEN
_ :: Bit -- (Reserved)
SR3 0x84 - FIFO status and interrupt register 2
_ :: Bits 25 -- (Reserved)
FEMPT :: Bit -- FEMPT
IFEN :: Bit -- IFEN
ILEN :: Bit -- ILEN
IREN :: Bit -- IREN
IFS :: Bit -- IFS
ILS :: Bit -- ILS
IRS :: Bit -- IRS
PMEM3 0x88 - Common memory space timing register 3
MEMHIZ :: Bits 8 -- MEMHIZx
MEMHOLD :: Bits 8 -- MEMHOLDx
MEMWAIT :: Bits 8 -- MEMWAITx
MEMSET :: Bits 8 -- MEMSETx
PATT3 0x8c - Attribute memory space timing register 3
ATTHIZ :: Bits 8 -- ATTHIZx
ATTHOLD :: Bits 8 -- ATTHOLDx
ATTWAIT :: Bits 8 -- ATTWAITx
ATTSET :: Bits 8 -- ATTSETx
ECCR3 0x94 - ECC result register 3
ECC :: Bits 32 -- ECCx
PCR4 0xa0 - PC Card/NAND Flash control register 2
_ :: Bits 12 -- (Reserved)
ECCPS :: Bits 3 -- ECCPS
TAR :: Bits 4 -- TAR
TCLR :: Bits 4 -- TCLR
_ :: Bits 2 -- (Reserved)
ECCEN :: Bit -- ECCEN
PWID :: Bits 2 -- PWID
PTYP :: Bit -- PTYP
PBKEN :: Bit -- PBKEN
PWAITEN :: Bit -- PWAITEN
_ :: Bit -- (Reserved)
SR4 0xa4 - FIFO status and interrupt register 2
_ :: Bits 25 -- (Reserved)
FEMPT :: Bit -- FEMPT
IFEN :: Bit -- IFEN
ILEN :: Bit -- ILEN
IREN :: Bit -- IREN
IFS :: Bit -- IFS
ILS :: Bit -- ILS
IRS :: Bit -- IRS
PMEM4 0xa8 - Common memory space timing register 4
MEMHIZ :: Bits 8 -- MEMHIZx
MEMHOLD :: Bits 8 -- MEMHOLDx
MEMWAIT :: Bits 8 -- MEMWAITx
MEMSET :: Bits 8 -- MEMSETx
PATT4 0xac - Attribute memory space timing register 4
ATTHIZ :: Bits 8 -- ATTHIZx
ATTHOLD :: Bits 8 -- ATTHOLDx
ATTWAIT :: Bits 8 -- ATTWAITx
ATTSET :: Bits 8 -- ATTSETx
PIO4 0xb0 - I/O space timing register 4
IOHIZx :: Bits 8 -- IOHIZx
IOHOLDx :: Bits 8 -- IOHOLDx
IOWAITx :: Bits 8 -- IOWAITx
IOSETx :: Bits 8 -- IOSETx
BWTR1 0x104 - SRAM/NOR-Flash write timing registers 1
_ :: Bits 2 -- (Reserved)
ACCMOD :: Bits 2 -- ACCMOD
DATLAT :: Bits 4 -- DATLAT
CLKDIV :: Bits 4 -- CLKDIV
BUSTURN :: Bits 4 -- Bus turnaround phase duration
DATAST :: Bits 8 -- DATAST
ADDHLD :: Bits 4 -- ADDHLD
ADDSET :: Bits 4 -- ADDSET
BWTR2 0x10c - SRAM/NOR-Flash write timing registers 1
_ :: Bits 2 -- (Reserved)
ACCMOD :: Bits 2 -- ACCMOD
DATLAT :: Bits 4 -- DATLAT
CLKDIV :: Bits 4 -- CLKDIV
BUSTURN :: Bits 4 -- Bus turnaround phase duration
DATAST :: Bits 8 -- DATAST
ADDHLD :: Bits 4 -- ADDHLD
ADDSET :: Bits 4 -- ADDSET
BWTR3 0x114 - SRAM/NOR-Flash write timing registers 1
_ :: Bits 2 -- (Reserved)
ACCMOD :: Bits 2 -- ACCMOD
DATLAT :: Bits 4 -- DATLAT
CLKDIV :: Bits 4 -- CLKDIV
BUSTURN :: Bits 4 -- Bus turnaround phase duration
DATAST :: Bits 8 -- DATAST
ADDHLD :: Bits 4 -- ADDHLD
ADDSET :: Bits 4 -- ADDSET
BWTR4 0x11c - SRAM/NOR-Flash write timing registers 1
_ :: Bits 2 -- (Reserved)
ACCMOD :: Bits 2 -- ACCMOD
DATLAT :: Bits 4 -- DATLAT
CLKDIV :: Bits 4 -- CLKDIV
BUSTURN :: Bits 4 -- Bus turnaround phase duration
DATAST :: Bits 8 -- DATAST
ADDHLD :: Bits 4 -- ADDHLD
ADDSET :: Bits 4 -- ADDSET
SCB_ACTRL 0xe000e008 System control block ACTLR
ACTRL 0x0 - Auxiliary control register
_ :: Bits 22 -- (Reserved)
DISOOFP :: Bit -- DISOOFP
DISFPCA :: Bit -- DISFPCA
_ :: Bits 5 -- (Reserved)
DISFOLD :: Bit -- DISFOLD
DISDEFWBUF :: Bit -- DISDEFWBUF
DISMCYCINT :: Bit -- DISMCYCINT
STK 0xe000e010 SysTick timer
CTRL 0x0 - SysTick control and status register
_ :: Bits 15 -- (Reserved)
COUNTFLAG :: Bit -- COUNTFLAG
_ :: Bits 13 -- (Reserved)
CLKSOURCE :: Bit -- Clock source selection
TICKINT :: Bit -- SysTick exception request enable
ENABLE :: Bit -- Counter enable
LOAD 0x4 - SysTick reload value register
_ :: Bits 8 -- (Reserved)
RELOAD :: Bits 24 -- RELOAD value
VAL 0x8 - SysTick current value register
_ :: Bits 8 -- (Reserved)
CURRENT :: Bits 24 -- Current counter value
CALIB 0xc - SysTick calibration value register
NOREF :: Bit -- NOREF flag. Reads as zero
SKEW :: Bit -- SKEW flag: Indicates whether the TENMS value is exact
_ :: Bits 6 -- (Reserved)
TENMS :: Bits 24 -- Calibration value
NVIC 0xe000e100 Nested Vectored Interrupt Controller
ISER0 0x0 - Interrupt Set-Enable Register
SETENA :: Bits 32 -- SETENA
ISER1 0x4 - Interrupt Set-Enable Register
SETENA :: Bits 32 -- SETENA
ISER2 0x8 - Interrupt Set-Enable Register
SETENA :: Bits 32 -- SETENA
ICER0 0x80 - Interrupt Clear-Enable Register
CLRENA :: Bits 32 -- CLRENA
ICER1 0x84 - Interrupt Clear-Enable Register
CLRENA :: Bits 32 -- CLRENA
ICER2 0x88 - Interrupt Clear-Enable Register
CLRENA :: Bits 32 -- CLRENA
ISPR0 0x100 - Interrupt Set-Pending Register
SETPEND :: Bits 32 -- SETPEND
ISPR1 0x104 - Interrupt Set-Pending Register
SETPEND :: Bits 32 -- SETPEND
ISPR2 0x108 - Interrupt Set-Pending Register
SETPEND :: Bits 32 -- SETPEND
ICPR0 0x180 - Interrupt Clear-Pending Register
CLRPEND :: Bits 32 -- CLRPEND
ICPR1 0x184 - Interrupt Clear-Pending Register
CLRPEND :: Bits 32 -- CLRPEND
ICPR2 0x188 - Interrupt Clear-Pending Register
CLRPEND :: Bits 32 -- CLRPEND
IABR0 0x200 - Interrupt Active Bit Register
ACTIVE :: Bits 32 -- ACTIVE
IABR1 0x204 - Interrupt Active Bit Register
ACTIVE :: Bits 32 -- ACTIVE
IABR2 0x208 - Interrupt Active Bit Register
ACTIVE :: Bits 32 -- ACTIVE
IPR0 0x300 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR1 0x304 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR2 0x308 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR3 0x30c - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR4 0x310 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR5 0x314 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR6 0x318 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR7 0x31c - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR8 0x320 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR9 0x324 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR10 0x328 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR11 0x32c - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR12 0x330 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR13 0x334 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR14 0x338 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR15 0x33c - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR16 0x340 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR17 0x344 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR18 0x348 - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
IPR19 0x34c - Interrupt Priority Register
IPR_N3 :: Bits 8 -- IPR_N3
IPR_N2 :: Bits 8 -- IPR_N2
IPR_N1 :: Bits 8 -- IPR_N1
IPR_N0 :: Bits 8 -- IPR_N0
SCB 0xe000ed00 System control block
CPUID 0x0 - CPUID base register
Implementer :: Bits 8 -- Implementer code
Variant :: Bits 4 -- Variant number
Constant :: Bits 4 -- Reads as 0xF
PartNo :: Bits 12 -- Part number of the processor
Revision :: Bits 4 -- Revision number
ICSR 0x4 - Interrupt control and state register
NMIPENDSET :: Bit -- NMI set-pending bit.
_ :: Bits 2 -- (Reserved)
PENDSVSET :: Bit -- PendSV set-pending bit
PENDSVCLR :: Bit -- PendSV clear-pending bit
PENDSTSET :: Bit -- SysTick exception set-pending bit
PENDSTCLR :: Bit -- SysTick exception clear-pending bit
_ :: Bits 2 -- (Reserved)
ISRPENDING :: Bit -- Interrupt pending flag
_ :: Bits 3 -- (Reserved)
VECTPENDING :: Bits 7 -- Pending vector
RETTOBASE :: Bit -- Return to base level
_ :: Bits 2 -- (Reserved)
VECTACTIVE :: Bits 9 -- Active vector
VTOR 0x8 - Vector table offset register
_ :: Bits 2 -- (Reserved)
TBLOFF :: Bits 21 -- Vector table base offset field
_ :: Bits 9 -- (Reserved)
AIRCR 0xc - Application interrupt and reset control register
VECTKEYSTAT :: Bits 16 -- Register key
ENDIANESS :: Bit -- ENDIANESS
_ :: Bits 4 -- (Reserved)
PRIGROUP :: Bits 3 -- PRIGROUP
_ :: Bits 5 -- (Reserved)
SYSRESETREQ :: Bit -- SYSRESETREQ
VECTCLRACTIVE :: Bit -- VECTCLRACTIVE
VECTRESET :: Bit -- VECTRESET
SCR 0x10 - System control register
_ :: Bits 27 -- (Reserved)
SEVEONPEND :: Bit -- Send Event on Pending bit
_ :: Bit -- (Reserved)
SLEEPDEEP :: Bit -- SLEEPDEEP
SLEEPONEXIT :: Bit -- SLEEPONEXIT
_ :: Bit -- (Reserved)
CCR 0x14 - Configuration and control register
_ :: Bits 22 -- (Reserved)
STKALIGN :: Bit -- STKALIGN
BFHFNMIGN :: Bit -- BFHFNMIGN
_ :: Bits 3 -- (Reserved)
DIV_0_TRP :: Bit -- DIV_0_TRP
UNALIGN__TRP :: Bit -- UNALIGN_ TRP
_ :: Bit -- (Reserved)
USERSETMPEND :: Bit -- USERSETMPEND
NONBASETHRDENA :: Bit -- Configures how the processor enters Thread mode
SHPR1 0x18 - System handler priority registers
_ :: Bits 8 -- (Reserved)
PRI_6 :: Bits 8 -- Priority of system handler 6
PRI_5 :: Bits 8 -- Priority of system handler 5
PRI_4 :: Bits 8 -- Priority of system handler 4
SHPR2 0x1c - System handler priority registers
PRI_11 :: Bits 8 -- Priority of system handler 11
_ :: Bits 24 -- (Reserved)
SHPR3 0x20 - System handler priority registers
PRI_15 :: Bits 8 -- Priority of system handler 15
PRI_14 :: Bits 8 -- Priority of system handler 14
_ :: Bits 16 -- (Reserved)
SHCRS 0x24 - System handler control and state register
_ :: Bits 13 -- (Reserved)
USGFAULTENA :: Bit -- Usage fault enable bit
BUSFAULTENA :: Bit -- Bus fault enable bit
MEMFAULTENA :: Bit -- Memory management fault enable bit
SVCALLPENDED :: Bit -- SVC call pending bit
BUSFAULTPENDED :: Bit -- Bus fault exception pending bit
MEMFAULTPENDED :: Bit -- Memory management fault exception pending bit
USGFAULTPENDED :: Bit -- Usage fault exception pending bit
SYSTICKACT :: Bit -- SysTick exception active bit
PENDSVACT :: Bit -- PendSV exception active bit
_ :: Bit -- (Reserved)
MONITORACT :: Bit -- Debug monitor active bit
SVCALLACT :: Bit -- SVC call active bit
_ :: Bits 3 -- (Reserved)
USGFAULTACT :: Bit -- Usage fault exception active bit
_ :: Bit -- (Reserved)
BUSFAULTACT :: Bit -- Bus fault exception active bit
MEMFAULTACT :: Bit -- Memory management fault exception active bit
CFSR_UFSR_BFSR_MMFSR 0x28 - Configurable fault status register
_ :: Bits 6 -- (Reserved)
DIVBYZERO :: Bit -- Divide by zero usage fault
UNALIGNED :: Bit -- Unaligned access usage fault
_ :: Bits 4 -- (Reserved)
NOCP :: Bit -- No coprocessor usage fault.
INVPC :: Bit -- Invalid PC load usage fault
INVSTATE :: Bit -- Invalid state usage fault
UNDEFINSTR :: Bit -- Undefined instruction usage fault
BFARVALID :: Bit -- Bus Fault Address Register (BFAR) valid flag
_ :: Bit -- (Reserved)
LSPERR :: Bit -- Bus fault on floating-point lazy state preservation
STKERR :: Bit -- Bus fault on stacking for exception entry
UNSTKERR :: Bit -- Bus fault on unstacking for a return from exception
IMPRECISERR :: Bit -- Imprecise data bus error
PRECISERR :: Bit -- Precise data bus error
IBUSERR :: Bit -- Instruction bus error
MMARVALID :: Bit -- Memory Management Fault Address Register (MMAR) valid flag
_ :: Bit -- (Reserved)
MLSPERR :: Bit -- MLSPERR
MSTKERR :: Bit -- Memory manager fault on stacking for exception entry.
MUNSTKERR :: Bit -- Memory manager fault on unstacking for a return from exception
_ :: Bit -- (Reserved)
IACCVIOL :: Bit -- Instruction access violation flag
_ :: Bit -- (Reserved)
HFSR 0x2c - Hard fault status register
DEBUG_VT :: Bit -- Reserved for Debug use
FORCED :: Bit -- Forced hard fault
_ :: Bits 28 -- (Reserved)
VECTTBL :: Bit -- Vector table hard fault
_ :: Bit -- (Reserved)
MMFAR 0x34 - Memory management fault address register
MMFAR :: Bits 32 -- Memory management fault address
BFAR 0x38 - Bus fault address register
BFAR :: Bits 32 -- Bus fault address
AFSR 0x3c - Auxiliary fault status register
IMPDEF :: Bits 32 -- Implementation defined
FPU_CPACR 0xe000ed88 Floating point unit CPACR
CPACR 0x0 - Coprocessor access control register
_ :: Bits 8 -- (Reserved)
CP :: Bits 4 -- CP
_ :: Bits 20 -- (Reserved)
MPU 0xe000ed90 Memory protection unit
TYPER 0x0 - MPU type register
_ :: Bits 8 -- (Reserved)
IREGION :: Bits 8 -- Number of MPU instruction regions
DREGION :: Bits 8 -- Number of MPU data regions
_ :: Bits 7 -- (Reserved)
SEPARATE :: Bit -- Separate flag
CTRL 0x4 - MPU control register
_ :: Bits 29 -- (Reserved)
PRIVDEFENA :: Bit -- Enable priviliged software access to default memory map
HFNMIENA :: Bit -- Enables the operation of MPU during hard fault
ENABLE :: Bit -- Enables the MPU
RNR 0x8 - MPU region number register
_ :: Bits 24 -- (Reserved)
REGION :: Bits 8 -- MPU region
RBAR 0xc - MPU region base address register
ADDR :: Bits 27 -- Region base address field
VALID :: Bit -- MPU region number valid
REGION :: Bits 4 -- MPU region field
RASR 0x10 - MPU region attribute and size register
_ :: Bits 3 -- (Reserved)
XN :: Bit -- Instruction access disable bit
_ :: Bit -- (Reserved)
AP :: Bits 3 -- Access permission
_ :: Bits 2 -- (Reserved)
TEX :: Bits 3 -- memory attribute
S :: Bit -- Shareable memory attribute
C :: Bit -- memory attribute
B :: Bit -- memory attribute
SRD :: Bits 8 -- Subregion disable bits
_ :: Bits 2 -- (Reserved)
SIZE :: Bits 5 -- Size of the MPU protection region
ENABLE :: Bit -- Region enable bit.
NVIC_STIR 0xe000ef00 Nested vectored interrupt controller
STIR 0x0 - Software trigger interrupt register
_ :: Bits 23 -- (Reserved)
INTID :: Bits 9 -- Software generated interrupt ID
FPU 0xe000ef34 Floting point unit
FPCCR 0x0 - Floating-point context control register
ASPEN :: Bit -- ASPEN
LSPEN :: Bit -- LSPEN
_ :: Bits 21 -- (Reserved)
MONRDY :: Bit -- MONRDY
_ :: Bit -- (Reserved)
BFRDY :: Bit -- BFRDY
MMRDY :: Bit -- MMRDY
HFRDY :: Bit -- HFRDY
THREAD :: Bit -- THREAD
_ :: Bit -- (Reserved)
USER :: Bit -- USER
LSPACT :: Bit -- LSPACT
FPCAR 0x4 - Floating-point context address register
ADDRESS :: Bits 29 -- Location of unpopulated floating-point
_ :: Bits 3 -- (Reserved)
FPSCR 0x8 - Floating-point status control register
N :: Bit -- Negative condition code flag
Z :: Bit -- Zero condition code flag
C :: Bit -- Carry condition code flag
V :: Bit -- Overflow condition code flag
_ :: Bit -- (Reserved)
AHP :: Bit -- Alternative half-precision control bit
DN :: Bit -- Default NaN mode control bit
FZ :: Bit -- Flush-to-zero mode control bit:
RMode :: Bits 2 -- Rounding Mode control field
_ :: Bits 14 -- (Reserved)
IDC :: Bit -- Input denormal cumulative exception bit.
_ :: Bits 2 -- (Reserved)
IXC :: Bit -- Inexact cumulative exception bit
UFC :: Bit -- Underflow cumulative exception bit
OFC :: Bit -- Overflow cumulative exception bit
DZC :: Bit -- Division by zero cumulative exception bit.
IOC :: Bit -- Invalid operation cumulative exception bit
DBGMCU 0xe0042000 Debug support
IDCODE 0x0 - IDCODE
REV_ID :: Bits 16 -- REV_ID
_ :: Bits 4 -- (Reserved)
DEV_ID :: Bits 12 -- DEV_ID
CR 0x4 - Control Register
_ :: Bits 11 -- (Reserved)
DBG_TIM7_STOP :: Bit -- DBG_TIM7_STOP
DBG_TIM6_STOP :: Bit -- DBG_TIM6_STOP
DBG_TIM5_STOP :: Bit -- DBG_TIM5_STOP
DBG_TIM8_STOP :: Bit -- DBG_TIM8_STOP
DBG_I2C2_SMBUS_TIMEOUT :: Bit -- DBG_I2C2_SMBUS_TIMEOUT
_ :: Bits 8 -- (Reserved)
TRACE_MODE :: Bits 2 -- TRACE_MODE
TRACE_IOEN :: Bit -- TRACE_IOEN
_ :: Bits 2 -- (Reserved)
DBG_STANDBY :: Bit -- DBG_STANDBY
DBG_STOP :: Bit -- DBG_STOP
DBG_SLEEP :: Bit -- DBG_SLEEP
APB1_FZ 0x8 - Debug MCU APB1 Freeze registe
_ :: Bits 5 -- (Reserved)
DBG_CAN2_STOP :: Bit -- DBG_CAN2_STOP
DBG_CAN1_STOP :: Bit -- DBG_CAN1_STOP
_ :: Bit -- (Reserved)
DBG_J2C3SMBUS_TIMEOUT :: Bit -- DBG_J2C3SMBUS_TIMEOUT
DBG_J2C2_SMBUS_TIMEOUT :: Bit -- DBG_J2C2_SMBUS_TIMEOUT
DBG_J2C1_SMBUS_TIMEOUT :: Bit -- DBG_J2C1_SMBUS_TIMEOUT
_ :: Bits 8 -- (Reserved)
DBG_IWDG_STOP :: Bit -- DBG_IWDEG_STOP
DBG_WWDG_STOP :: Bit -- DBG_WWDG_STOP
_ :: Bits 2 -- (Reserved)
DBG_TIM14_STOP :: Bit -- DBG_TIM14_STOP
DBG_TIM13_STOP :: Bit -- DBG_TIM13_STOP
DBG_TIM12_STOP :: Bit -- DBG_TIM12_STOP
DBG_TIM7_STOP :: Bit -- DBG_TIM7_STOP
DBG_TIM6_STOP :: Bit -- DBG_TIM6_STOP
DBG_TIM5_STOP :: Bit -- DBG_TIM5_STOP
DBG_TIM4_STOP :: Bit -- DBG_TIM4_STOP
DBG_TIM3_STOP :: Bit -- DBG_TIM3 _STOP
DBG_TIM2_STOP :: Bit -- DBG_TIM2_STOP
APB2_FZ 0xc - Debug MCU APB2 Freeze registe
_ :: Bits 13 -- (Reserved)
DBG_TIM11_STOP :: Bit -- TIM11 counter stopped when core is halted
DBG_TIM10_STOP :: Bit -- TIM10 counter stopped when core is halted
DBG_TIM9_STOP :: Bit -- TIM9 counter stopped when core is halted
_ :: Bits 14 -- (Reserved)
DBG_TIM8_STOP :: Bit -- TIM8 counter stopped when core is halted
DBG_TIM1_STOP :: Bit -- TIM1 counter stopped when core is halted