clash-vhdl-0.7: primitives/CLaSH.Prelude.RAM.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.RAM.asyncRam#"
    , "type" :
"asyncRam# :: SClock wclk       -- ^ wclk, ARG[0]
           -> SClock rclk       -- ^ rclk, ARG[1]
           -> SNat n            -- ^ sz,   ARG[2]
           -> Signal' rclk Int  -- ^ rd,   ARG[3]
           -> Signal' wclk Bool -- ^ en,   ARG[4]
           -> Signal' wclk Int  -- ^ wr,   ARG[5]
           -> Signal' wclk a    -- ^ din,  ARG[6]
           -> Signal' rclk a"
    , "templateD" :
"-- asyncRam begin
~GENSYM[~COMPNAME_asyncRam][0] : block~IF ~VIVADO ~THEN
  type ~GENSYM[RamType][4] is array(natural range <>) of std_logic_vector(~SIZE[~TYP[6]]-1 downto 0);~ELSE
  type ~SYM[4] is array(natural range <>) of ~TYP[6];~FI
  signal ~GENSYM[RAM][1] : ~SYM[4](0 to ~LIT[2]-1);
  signal ~GENSYM[rd][2] : integer range 0 to ~LIT[2] - 1;
  signal ~GENSYM[wr][3] : integer range 0 to ~LIT[2] - 1;
begin
  ~SYM[2] <= to_integer(~ARG[3])
  -- pragma translate_off
                mod ~LIT[2]
  -- pragma translate_on
                ;

  ~SYM[3] <= to_integer(~ARG[5])
  -- pragma translate_off
                mod ~LIT[2]
  -- pragma translate_on
                ;

  ~GENSYM[asyncRam_sync][5] : process(~CLK[0])
  begin
    if rising_edge(~CLK[0]) then
      if ~ARG[4] then~IF ~VIVADO ~THEN
        ~SYM[1](~SYM[3]) <= ~TOBV[~ARG[6]][~TYP[6]];~ELSE
        ~SYM[1](~SYM[3]) <= ~ARG[6];~FI
      end if;
    end if;
  end process;~IF ~VIVADO ~THEN
  ~RESULT <= ~FROMBV[~SYM[1](~SYM[2])][~TYP[6]];~ELSE
  ~RESULT <= ~SYM[1](~SYM[2]);~FI
end block;
-- asyncRam end"
    }
  }
]