clash-vhdl-0.7: primitives/CLaSH.Prelude.BlockRam.File.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.BlockRam.File.blockRamFile#"
    , "type" :
"blockRamFile# :: KnownNat m                -- ARG[0]
               => SClock clk                -- clk,  ARG[1]
               -> SNat n                    -- sz,   ARG[2]
               -> FilePath                  -- file, ARG[3]
               -> Signal' clk Int           -- rd,   ARG[4]
               -> Signal' clk Bool          -- wren, ARG[5]
               -> Signal' clk Int           -- wr,   ARG[6]
               -> Signal' clk (BitVector m) -- din,  ARG[7]
               -> Signal' clk (BitVector m)"
    , "templateD" :
"-- blockRamFile begin
~GENSYM[~COMPNAME_blockRamFile][0] : block
  type ~GENSYM[RamType][6] is array(natural range <>) of bit_vector(~LIT[0]-1 downto 0);

  impure function ~GENSYM[InitRamFromFile][1] (RamFileName : in string) return ~SYM[6] is
    FILE RamFile : text open read_mode is RamFileName;
    variable RamFileLine : line;
    variable RAM : ~SYM[6](0 to ~LIT[2]-1);
  begin
    for i in RAM'range loop
      readline(RamFile,RamFileLine);
      read(RamFileLine,RAM(i));
    end loop;
    return RAM;
  end function;

  signal ~GENSYM[RAM][2] : ~SYM[6](0 to ~LIT[2]-1) := ~SYM[1](~FILE[~LIT[3]]);
  signal ~GENSYM[dout][3] : ~TYP[7];
  signal ~GENSYM[rd][4] : integer range 0 to ~LIT[2]-1;
  signal ~GENSYM[wr][5] : integer range 0 to ~LIT[2]-1;
begin
  ~SYM[4] <= to_integer(~ARG[4])
  -- pragma translate_off
                mod ~LIT[2]
  -- pragma translate_on
                ;

  ~SYM[5] <= to_integer(~ARG[6])
  -- pragma translate_off
                mod ~LIT[2]
  -- pragma translate_on
                ;

  ~GENSYM[blockRamFile_sync][7] : process(~CLK[1])
  begin
    if (rising_edge(~CLK[1])) then
      if ~ARG[5] then
        ~SYM[2](~SYM[5]) <= to_bitvector(~ARG[7]);
      end if;
      ~SYM[3] <= to_stdlogicvector(~SYM[2](~SYM[4]));
    end if;
  end process;

  ~RESULT <= ~SYM[3];
end block;
-- blockRamFile end"
    }
  }
]