clash-vhdl-0.6: primitives/CLaSH.Prelude.ROM.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.ROM.asyncRom#"
    , "type" :
"asyncRom# :: KnownNat n -- ^ ARG[0]
           => Vec n a    -- ^ ARG[1]
           -> Int        -- ^ ARG[2]
           -> a"
    , "templateD" :
"-- asyncRom begin
asyncRom_~SYM[0] : block
  signal ROM_~SYM[1]       : ~TYP[1];
  signal rom_index_~SYM[2] : integer range 0 to ~LIT[0]-1;
begin
  ROM_~SYM[1] <= ~ARG[1];

  rom_index~SYM[2] <= ~ARG[2]
  -- pragma translate_off
                      mod ~LIT[0]
  -- pragma translate_on
                      ;

  ~RESULT <= ROM_~SYM[1](rom_index_~SYM[2]);
end block;
-- asyncRom end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Prelude.ROM.rom#"
    , "type" :
"rom# :: KnownNat n      -- ARG[0]
      => SClock clk      -- clk,  ARG[1]
      -> Vec n a         -- init, ARG[2]
      -> Signal' clk Int -- rd,   ARG[3]
      -> Signal' clk a"
    , "templateD" :
"-- rom begin
rom_~COMPNAME_~SYM[0] : block
  signal ROM_~SYM[1]  : ~TYP[2];
  signal rd_~SYM[2]   : integer range 0 to ~LIT[0]-1;
  signal dout_~SYM[3] : ~TYPO;
begin
  ROM_~SYM[1] <= ~ARG[2];

  rd_~SYM[2] <= ~ARG[3]
  -- pragma translate_off
                mod ~LIT[0]
  -- pragma translate_on
                ;

  romSync : process (~CLK[1])
  begin
    if (rising_edge(~CLK[1])) then
      dout_~SYM[3] <= ROM_~SYM[1](rd_~SYM[2]);
    end if;
  end process;

  ~RESULT <= dout_~SYM[3];
end block;
-- rom end"
    }
  }
]