clash-vhdl-0.6: primitives/CLaSH.Prelude.RAM.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.RAM.asyncRam#"
    , "type" :
"asyncRam# :: SClock wclk       -- ^ wclk, ARG[0]
           -> SClock rclk       -- ^ rclk, ARG[1]
           -> SNat n            -- ^ sz,   ARG[2]
           -> Signal' wclk Int  -- ^ wr,   ARG[3]
           -> Signal' rclk Int  -- ^ rd,   ARG[4]
           -> Signal' wclk Bool -- ^ en,   ARG[5]
           -> Signal' wclk a    -- ^ din,  ARG[6]
           -> Signal' rclk a"
    , "templateD" :
"-- asyncRam begin
asyncRam_~COMPNAME_~SYM[0] : block
  type RamType is array(natural range <>) of ~TYP[6];
  signal RAM_~SYM[1] : RamType(0 to ~LIT[2]-1);
  signal wr_~SYM[2]  : integer range 0 to ~LIT[2] - 1;
  signal rd_~SYM[3]  : integer range 0 to ~LIT[2] - 1;
begin
  wr_~SYM[2] <= ~ARG[3]
  -- pragma translate_off
                mod ~LIT[2]
  -- pragma translate_on
                ;

  rd_~SYM[3] <= ~ARG[4]
  -- pragma translate_off
                mod ~LIT[2]
  -- pragma translate_on
                ;

  asyncRam_sync : process(~CLK[0])
  begin
    if rising_edge(~CLK[0]) then
      if ~ARG[5] then
        RAM_~SYM[1](wr_~SYM[2]) <= ~ARG[6];
      end if;
    end if;
  end process;

  ~RESULT <= RAM_~SYM[1](rd_~SYM[3]);
end block;
-- asyncRam end"
    }
  }
]