clash-vhdl-0.6: primitives/CLaSH.Prelude.BlockRam.File.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.BlockRam.File.blockRamFile#"
    , "type" :
"blockRamFile# :: KnownNat m                -- ARG[0]
               => SClock clk                -- clk,  ARG[1]
               -> SNat n                    -- sz,   ARG[2]
               -> FilePath                  -- file, ARG[3]
               -> Signal' clk Int           -- wr,   ARG[4]
               -> Signal' clk Int           -- rd,   ARG[5]
               -> Signal' clk Bool          -- wren, ARG[6]
               -> Signal' clk (BitVector m) -- din,  ARG[7]
               -> Signal' clk (BitVector m)"
    , "templateD" :
"-- blockRamFile begin
blockRamFile_~COMPNAME_~SYM[0] : block
  type RamType is array(natural range <>) of bit_vector(~LIT[0]-1 downto 0);

  impure function InitRamFromFile (RamFileName : in string) return RamType is
    FILE RamFile : text open read_mode is RamFileName;
    variable RamFileLine : line;
    variable RAM : RamType(0 to ~LIT[2]-1);
  begin
    for i in RAM'range loop
      readline(RamFile,RamFileLine);
      read(RamFileLine,RAM(i));
    end loop;
    return RAM;
  end function;

  signal RAM_~SYM[1]  : RamType(0 to ~LIT[2]-1) := InitRamFromFile(~FILE[~LIT[3]]);
  signal dout_~SYM[2] : ~TYP[7];
  signal wr_~SYM[3]   : integer range 0 to ~LIT[2]-1;
  signal rd_~SYM[4]   : integer range 0 to ~LIT[2]-1;
begin
  wr_~SYM[3] <= ~ARG[4]
  -- pragma translate_off
                mod ~LIT[2]
  -- pragma translate_on
                ;

  rd_~SYM[4] <= ~ARG[5]
  -- pragma translate_off
                mod ~LIT[2]
  -- pragma translate_on
                ;

  blockRamFile_sync : process(~CLK[1])
  begin
    if (rising_edge(~CLK[1])) then
      if ~ARG[6] then
        RAM_~SYM[1](to_integer(wr_~SYM[3])) <= to_bitvector(~ARG[7]);
      end if;

      dout_~SYM[2] <= to_stdlogicvector(RAM_~SYM[1](rd_~SYM[4]));
    end if;
  end process;

  ~RESULT <= dout_~SYM[2];
end block;
-- blockRamFile end"
    }
  }
]