clash-vhdl-0.6.8: primitives/CLaSH.Sized.Internal.BitVector.json

[ { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.size#"
    , "type"      : "size# :: KnownNat n => BitVector n -> Int"
    , "templateE" : "to_signed(~LIT[0],~SIZE[~TYPO])"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.maxIndex#"
    , "type"      : "maxIndex# :: KnownNat n => BitVector n -> Int"
    , "templateE" : "to_signed(~LIT[0] - 1,~SIZE[~TYPO])"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.high"
    , "type"      : "high :: Bit"
    , "templateE" : "std_logic_vector'(\"1\")"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.low"
    , "type"      : "low :: Bit"
    , "templateE" : "std_logic_vector'(\"0\")"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.++#"
    , "type"      : "(++#) :: KnownNat m => BitVector n -> BitVector m -> BitVector (n + m)"
    , "templateE" : "std_logic_vector'(std_logic_vector'(~ARG[1]) & std_logic_vector'(~ARG[2]))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.reduceAnd#"
    , "type"      : "reduceAnd# :: KnownNat n => BitVector n -> BitVector 1"
    , "templateD" :
"-- reduceAnd begin
~GENSYM[reduceAnd][0] : block
  function and_reduce (arg : std_logic_vector) return std_logic is
    variable upper, lower : std_logic;
    variable half         : integer;
    variable argi         : std_logic_vector (arg'length - 1 downto 0);
    variable result       : std_logic;
  begin
    if (arg'length < 1) then
      result := '1';
    else
      argi := arg;
      if (argi'length = 1) then
        result := argi(argi'left);
      else
        half   := (argi'length + 1) / 2; -- lsb-biased tree
        upper  := and_reduce (argi (argi'left downto half));
        lower  := and_reduce (argi (half - 1 downto argi'right));
        result := upper and lower;
      end if;
    end if;
    return result;
  end;
begin
  ~RESULT <= (0 => and_reduce(~ARG[1]));
end block;
-- reduceAnd end"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.reduceOr#"
    , "type"      : "reduceOr# :: BitVector n -> BitVector 1"
    , "templateD" :
"-- reduceOr begin
~GENSYM[reduceOr][0] : block
  function or_reduce (arg : std_logic_vector) return std_logic is
    variable upper, lower : std_logic;
    variable half         : integer;
    variable argi         : std_logic_vector (arg'length - 1 downto 0);
    variable result       : std_logic;
  begin
    if (arg'length < 1) then
      result := '0';
    else
      argi := arg;
      if (argi'length = 1) then
        result := argi(argi'left);
      else
        half   := (argi'length + 1) / 2; -- lsb-biased tree
        upper  := or_reduce (argi (argi'left downto half));
        lower  := or_reduce (argi (half - 1 downto argi'right));
        result := upper or lower;
      end if;
    end if;
    return result;
  end;
begin
  ~RESULT <= (0 => or_reduce(~ARG[0]));
end block;
-- reduceOr end"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.reduceXor#"
    , "type"      : "reduceXor# :: BitVector n -> BitVector 1"
    , "templateD" :
"-- reduceXor begin
~GENSYM[reduceXor][0] : block
  function xor_reduce (arg : std_logic_vector) return std_logic is
    variable upper, lower : std_logic;
    variable half         : integer;
    variable argi         : std_logic_vector (arg'length - 1 downto 0);
    variable result       : std_logic;
  begin
    if (arg'length < 1) then
      result := '0';
    else
      argi := arg;
      if (argi'length = 1) then
        result := argi(argi'left);
      else
        half   := (argi'length + 1) / 2; -- lsb-biased tree
        upper  := xor_reduce (argi (argi'left downto half));
        lower  := xor_reduce (argi (half - 1 downto argi'right));
        result := upper xor lower;
      end if;
    end if;
    return result;
  end;
begin
  ~RESULT <= (0 => xor_reduce(~ARG[0]));
end block;
-- reduceXor end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Sized.Internal.BitVector.index#"
    , "type" :
"index# :: KnownNat n  -- ARG[0]
        => BitVector n -- ARG[1]
        -> Int         -- ARG[2]
        -> Bit"
    , "templateD" :
"-- indexBitVector begin~IF ~ISVAR[1] ~THEN
~GENSYM[indexBitVector][0] : block
  signal ~GENSYM[vec_index][1] : integer range 0 to ~LIT[0]-1;
begin
  ~SYM[1] <= to_integer(~ARG[2])
  -- pragma translate_off
               mod ~LIT[0]
  -- pragma translate_on
               ;

  ~RESULT <= ~ARG[1](~SYM[1] downto ~SYM[1]);
end block;~ELSE
~SYM[0] : block
  signal ~GENSYM[bv][2] : ~TYP[1];
  signal ~SYM[1] : integer range 0 to ~LIT[0]-1;
begin
  ~SYM[2] <= ~ARG[1];
  ~SYM[1] <= to_integer(~ARG[2])
  -- pragma translate_off
               mod ~LIT[0]
  -- pragma translate_on
               ;

  ~RESULT <= ~SYM[2](~SYM[1] downto ~SYM[1]);
end block;~FI
-- indexBitVector end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Sized.Internal.BitVector.replaceBit#"
    , "type" :
"replaceBit# :: KnownNat n  -- ARG[0]
             => BitVector n -- ARG[1]
             -> Int         -- ARG[2]
             -> Bit         -- ARG[3]
             -> BitVector n"
    , "templateD" :
"-- replaceBit begin
~GENSYM[replaceBit][0] : block
  signal ~GENSYM[vec_index][1] : integer range 0 to ~LIT[0]-1;
begin
  ~SYM[1] <= to_integer(~ARG[2])
  -- pragma translate_off
               mod ~LIT[0]
  -- pragma translate_on
               ;

  process(~SYM[1]~VARS[1]~VARS[3])
    variable ~GENSYM[ivec][2] : ~TYP[1];
  begin
    ~SYM[2] := ~ARG[1];
    ~SYM[2](~SYM[1] downto ~SYM[1]) := ~ARG[3];
    ~RESULT <= ~SYM[2];
  end process;
end block;
-- replaceBit end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Sized.Internal.BitVector.setSlice#"
    , "type" :
"setSlice# :: BitVector (m + 1 + i) -- ARG[0]
           -> SNat m                -- ARG[1]
           -> SNat n                -- ARG[2]
           -> BitVector (m + 1 - n) -- ARG[3]
           -> BitVector (m + 1 + i)"
    , "templateD" :
"-- setSlice begin~IF ~ISVAR[0] ~THEN
~GENSYM[setSlice][0] : process(~ARG[0]~VARS[3])
  variable ~GENSYM[ivec][1] : ~TYP[0];
begin
  ~SYM[1] := ~ARG[0];
  ~SYM[1](~LIT[1] downto ~LIT[2]) := ~ARG[3];
  ~RESULT <= ~SYM[1];
end process;~ELSE
~SYM[0] : block
  signal ~GENSYM[bv][2] : ~TYP[0];
begin
  ~SYM[2] <= ~ARG[0];
  process(~SYM[2]~VARS[3])
    variable ~SYM[1] : ~TYP[0];
  begin
    ~SYM[1] := ~SYM[2];
    ~SYM[1](~LIT[1] downto ~LIT[2]) := ARG[3];
    ~RESULT <= ~SYM[1];
  end process;
end block;~FI
-- setSlice end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Sized.Internal.BitVector.slice#"
    , "type" :
"slice# :: BitVector (m + 1 + i) -- ARG[0]
        -> SNat m                -- ARG[1]
        -> SNat n                -- ARG[2]
        -> BitVector (m + 1 - n)"
    , "templateD" :
"-- slice begin~IF ~ISVAR[0] ~THEN
~RESULT <= ~ARG[0](~LIT[1] downto ~LIT[2]);~ELSE
~GENSYM[slice][0] : block
  signal ~GENSYM[bv][1] : ~TYP[0];
begin
  ~SYM[1] <= ~ARG[0];
  ~RESULT <= ~SYM[1](~LIT[1] downto ~LIT[2]);
end block;~FI
-- slice end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Sized.Internal.BitVector.split#"
    , "type" :
"split# :: KnownNat n        -- ARG[0]
        => BitVector (m + n) -- ARG[1]
        -> (BitVector m, BitVector n)"
    , "templateD" :
"-- split begin~IF ~ISVAR[1] ~THEN
~RESULT <= (~ARG[1](~ARG[1]'high downto ~LIT[0])
           ,~ARG[1](~LIT[0]-1 downto 0)
           );~ELSE
~GENSYM[split][0]: block
  signal ~GENSYM[bv][1] : ~TYP[1];
begin
  ~SYM[1] <= ~ARG[1];
  ~RESULT <= (~SYM[1](~SYM[1]'high downto ~LIT[0])
             ,~SYM[1](~LIT[0]-1 downto 0)
             );
end block;~FI
-- split end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Sized.Internal.BitVector.msb#"
    , "type" :
"msb# :: KnownNat n  -- ARG[0]
      => BitVector n -- ARG[1]
      -> Bit"
    , "templateD" :
"-- msb begin~IF ~LIT[0] ~THEN ~IF ~ISVAR[1] ~THEN
~RESULT <= ~ARG[1](~ARG[1]'high downto ~ARG[1]'high);~ELSE
~GENSYM[msb][0] : block
  signal ~GENSYM[bv][1] : ~TYP[1];
begin
  ~SYM[1] <= ~ARG[1];
  ~RESULT <= ~SYM[1](~SYM[1]'high downto ~SYM[1]'high);
end block;~FI~ELSE
~RESULT <= \"0\";~FI
-- msb end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Sized.Internal.BitVector.lsb#"
    , "type" :
"lsb# :: BitVector n -- ARG[0]
      -> Bit"
    , "templateD" :
"-- lsb begin~IF ~SIZE[~TYP[0]] ~THEN ~IF ~ISVAR[0] ~THEN
~RESULT <= ~ARG[0](0 downto 0);~ELSE
~GENSYM[lsb][0] : block
  signal ~GENSYM[bv][1] : ~TYP[0];
begin
  ~SYM[1] <= ~ARG[0];
  ~RESULT <= ~SYM[1](0 downto 0);
end block;~FI~ELSE
~RESULT <= \"0\";~FI
-- lsb end"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.eq#"
    , "type"      : "eq# :: BitVector n -> BitVector n -> Bool"
    , "templateE" : "~ARG[0] = ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.neq#"
    , "type"      : "neq# :: BitVector n -> BitVector n -> Bool"
    , "templateE" : "~ARG[0] /= ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.lt#"
    , "type"      : "lt# :: BitVector n -> BitVector n -> Bool"
    , "templateE" : "~ARG[0] < ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.ge#"
    , "type"      : "ge# :: BitVector n -> BitVector n -> Bool"
    , "templateE" : "~ARG[0] >= ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.gt#"
    , "type"      : "gt# :: BitVector n -> BitVector n -> Bool"
    , "templateE" : "~ARG[0] > ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.le#"
    , "type"      : "le# :: BitVector n -> BitVector n -> Bool"
    , "templateE" : "~ARG[0] <= ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.minBound#"
    , "type"      : "minBound# :: BitVector n"
    , "comment"   : "Generates incorrect VDHL for n=0"
    , "templateE" : "std_logic_vector'(~SIZE[~TYPO]-1 downto 0 => '0')"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.maxBound#"
    , "type"      : "maxBound# :: KnownNat n => BitVector n"
    , "comment"   : "Generates incorrect VDHL for n=0"
    , "templateE" : "std_logic_vector'(~LIT[0]-1 downto 0 => '1')"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.+#"
    , "type"      : "(+#) :: KnownNat n => BitVector n -> BitVector n -> BitVector n"
    , "templateE" : "std_logic_vector(unsigned(~ARG[1]) + unsigned(~ARG[2]))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.-#"
    , "type"      : "(-#) :: KnownNat n => BitVector n -> BitVector n -> BitVector n"
    , "templateE" : "std_logic_vector(unsigned(~ARG[1]) - unsigned(~ARG[2]))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.*#"
    , "type"      : "(*#) :: KnownNat n => BitVector n -> BitVector n -> BitVector n"
    , "templateE" : "std_logic_vector(resize(unsigned(~ARG[1]) * unsigned(~ARG[2]), ~LIT[0]))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.negate#"
    , "type"      : "negate# :: KnownNat n => BitVector n -> BitVector n"
    , "templateE" : "std_logic_vector(-(signed(~ARG[1])))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.fromInteger#"
    , "type"      : "fromInteger# :: KnownNat n => Integer -> BitVector n"
    , "templateE" : "std_logic_vector(resize(unsigned(std_logic_vector(~ARG[1])),~LIT[0]))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.plus#"
    , "type"      : "plus# :: KnownNat (Max m n + 1) => BitVector m -> BitVector n -> BitVector (Max m n + 1)"
    , "templateE" : "std_logic_vector(resize(unsigned(~ARG[1]),~LIT[0]) + resize(unsigned(~ARG[2]),~LIT[0]))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.minus#"
    , "type"      : "minus# :: KnownNat (Max m n + 1) => BitVector m -> BitVector n -> BitVector (Max m n + 1)"
    , "templateE" : "std_logic_vector(resize(unsigned(~ARG[1]),~LIT[0]) - resize(unsigned(~ARG[2]),~LIT[0]))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.times#"
    , "type"      : "times# :: KnownNat (m + n) => BitVector m -> BitVector n -> BitVector (m + n)"
    , "templateE" : "std_logic_vector(unsigned(~ARG[1]) * unsigned(~ARG[2]))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.quot#"
    , "type"      : "quot# :: BitVector n -> BitVector n -> BitVector n"
    , "templateE" : "std_logic_vector(unsigned(~ARG[1]) / unsigned(~ARG[2]))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.rem#"
    , "type"      : "rem# :: BitVector n -> BitVector n -> BitVector n"
    , "templateE" : "std_logic_vector(unsigned(~ARG[1]) rem unsigned(~ARG[2]))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.toInteger#"
    , "type"      : "toInteger# :: BitVector n -> Integer"
    , "templateE" : "signed(std_logic_vector(resize(unsigned(~ARG[0]),~SIZE[~TYPO])))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.and#"
    , "type"      : "and# :: BitVector n -> BitVector n -> BitVector n"
    , "templateE" : "~ARG[0] and ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.or#"
    , "type"      : "or# :: BitVector n -> BitVector n -> BitVector n"
    , "templateE" : "~ARG[0] or ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.xor#"
    , "type"      : "xor# :: BitVector n -> BitVector n -> BitVector n"
    , "templateE" : "~ARG[0] xor ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.complement#"
    , "type"      : "complement# :: KnownNat n => BitVector n -> BitVector n"
    , "templateE" : "not ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.shiftL#"
    , "type"      : "shiftL# :: KnownNat n => BitVector n -> Int -> BitVector n"
    , "templateE" : "std_logic_vector(shift_left(unsigned(~ARG[1]),to_integer(~ARG[2])))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.shiftR#"
    , "type"      : "shiftR# :: KnownNat n => BitVector n -> Int -> BitVector n"
    , "templateE" : "std_logic_vector(shift_right(unsigned(~ARG[1]),to_integer(~ARG[2])))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.rotateL#"
    , "type"      : "rotateL# :: KnownNat n => BitVector n -> Int -> BitVector n"
    , "templateE" : "std_logic_vector(rotate_left(unsigned(~ARG[1]),to_integer(~ARG[2])))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.rotateR#"
    , "type"      : "rotateR# :: KnownNat n => BitVector n -> Int -> BitVector n"
    , "templateE" : "std_logic_vector(rotate_right(unsigned(~ARG[1]),to_integer(~ARG[2])))"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Internal.BitVector.resize#"
    , "type"      : "resize# :: KnownNat m => BitVector n -> BitVector m"
    , "templateE" : "std_logic_vector(resize(unsigned(~ARG[1]),~LIT[0]))"
    }
  }
]