clash-vhdl-0.6.8: primitives/CLaSH.Signal.Internal.json

[ { "BlackBox" :
    { "name" : "CLaSH.Signal.Internal.register#"
    , "type" :
"register# :: SClock clk     -- ARG[0]
           -> a              -- ARG[1]
           -> Signal' clk a  -- ARG[2]
           -> Signal' clk a"
    , "templateD" :
"-- register begin
~GENSYM[~COMPNAME_register][0] : process(~CLK[0],~RST[0]~VARS[1])
begin
  if ~RST[0] = '0' then
    ~RESULT <= ~ARG[1];
  elsif rising_edge(~CLK[0]) then
    ~RESULT <= ~ARG[2];
  end if;
end process;
-- register end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Signal.Internal.regEn#"
    , "type" :
"regEn# :: SClock clk       -- ARG[0]
        -> a                -- ARG[1]
        -> Signal' clk Bool -- ARG[2]
        -> Signal' clk a    -- ARG[3]
        -> Signal' clk a"
    , "templateD" :
"-- regEn begin
~GENSYM[~COMPNAME_regEn][0] : process(~CLK[0],~RST[0]~VARS[1]~VARS[2])
begin
  if ~RST[0] = '0' then
    ~RESULT <= ~ARG[1];
  elsif rising_edge(~CLK[0]) then
    if ~ARG[2] then
      ~RESULT <= ~ARG[3];
    end if;
  end if;
end process;
-- regEn end"
    }
  }

, { "Primitive" :
    { "name"      : "CLaSH.Signal.Internal.signal#"
    , "primType"  : "Function"
    }
  }
, { "Primitive" :
    { "name"      : "CLaSH.Signal.Internal.mapSignal#"
    , "primType"  : "Function"
    }
  }
, { "Primitive" :
    { "name"      : "CLaSH.Signal.Internal.appSignal#"
    , "primType"  : "Function"
    }
  }
, { "Primitive" :
    { "name"      : "CLaSH.Signal.Internal.foldr#"
    , "primType"  : "Function"
    }
  }
, { "Primitive" :
    { "name"      : "CLaSH.Signal.Internal.traverse#"
    , "primType"  : "Function"
    }
  }
, { "Primitive" :
    { "name"      : "CLaSH.Signal.Internal.joinSignal#"
    , "primType"  : "Function"
    }
  }
]