clash-vhdl-0.6.8: primitives/CLaSH.Prelude.Testbench.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.Testbench.assert'"
    , "type" :
"assert' :: (Eq a,Show a) -- (ARG[0],ARG[1])
         => SClock t      -- ^ ARG[2]
         -> String        -- ^ ARG[3]
         -> Signal' t a   -- ^ Checked value (ARG[4])
         -> Signal' t a   -- ^ Expected value (ARG[5])
         -> Signal' t b   -- ^ Return valued (ARG[6])
         -> Signal' t b"
    , "templateD" :
"-- assert begin
~GENSYM[assert][0] : block
  -- pragma translate_off
  function ~GENSYM[slv2string][1] (slv : std_logic_vector) return STRING is
     variable result : string (1 to slv'length);
     variable res_l : string (1 to 3);
     variable r : integer;
   begin
     r := 1;
     for i in slv'range loop
        res_l := std_logic'image(slv(i));
        result(r) := res_l(2);
        r := r + 1;
     end loop;
     return result;
  end;
  signal ~GENSYM[actual][2] : ~TYP[4];
  signal ~GENSYM[expected][3] : ~TYP[5];
  -- pragma translate_on
begin
  -- pragma translate_off
  ~SYM[2] <= ~ARG[4];
  ~SYM[3] <= ~ARG[5];
  process(~CLK[2],~RST[2]) is
  begin
    if (rising_edge(~CLK[2]) or rising_edge(~RST[2])) then
      assert (~SYM[2] = ~SYM[3]) report (~LIT[3] & \", expected: \" & ~SYM[1](toSLV(~SYM[3])) & \", actual: \" & ~SYM[1](toSLV(~SYM[2]))) severity error;
    end if;
  end process;
  -- pragma translate_on
  ~RESULT <= ~ARG[6];
end block;
-- assert end"
    }
  }
]