clash-vhdl-0.6.8: primitives/CLaSH.Prelude.ROM.File.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.ROM.File.asyncRomFile#"
    , "type" :
"asyncRomFile# :: KnownNat m -- ARG[0]
               => SNat n     -- sz,   ARG[1]
               -> FilePath   -- file, ARG[2]
               -> Int        -- rd,   ARG[3]
               -> BitVector m"
    , "templateD" :
"-- asyncRomFile begin
~GENSYM[asyncROMFile][0] : block
  type ~GENSYM[RomType][4] is array(natural range <>) of bit_vector(~LIT[0]-1 downto 0);

  impure function ~GENSYM[InitRomFromFile][1] (RomFileName : in string) return ~SYM[4] is
    FILE RomFile : text open read_mode is RomFileName;
    variable RomFileLine : line;
    variable ROM : ~SYM[4](0 to ~LIT[1]-1);
  begin
    for i in ROM'range loop
      readline(RomFile,RomFileLine);
      read(RomFileLine,ROM(i));
    end loop;
    return ROM;
  end function;

  signal ~GENSYM[ROM][2] : ~SYM[4](0 to ~LIT[1]-1) := ~SYM[1](~FILE[~LIT[2]]);
  signal ~GENSYM[rd][3] : integer range 0 to ~LIT[1]-1;
begin
  ~SYM[3] <= to_integer(~ARG[3])
  -- pragma translate_off
                mod ~LIT[1]
  -- pragma translate_on
                ;

  ~RESULT <= to_stdlogicvector(~SYM[2](~SYM[3]));
end block;
-- asyncRomFile end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Prelude.ROM.File.romFile#"
    , "type" :
"romFile# :: KnownNat m      -- ARG[0]
          => SClock clk      -- clk,  ARG[1]
          -> SNat n          -- sz,   ARG[2]
          -> FilePath        -- file, ARG[3]
          -> Signal' clk Int -- rd,   ARG[4]
          -> Signal' clk (BitVector m)"
    , "templateD" :
"-- romFile begin
~GENSYM[~COMPNAME_romFile][0] : block
  type ~GENSYM[RomType][4] is array(natural range <>) of bit_vector(~LIT[0]-1 downto 0);

  impure function ~GENSYM[InitRomFromFile][1] (RomFileName : in string) return ~SYM[4] is
    FILE RomFile : text open read_mode is RomFileName;
    variable RomFileLine : line;
    variable ROM : ~SYM[4](0 to ~LIT[2]-1);
  begin
    for i in ROM'range loop
      readline(RomFile,RomFileLine);
      read(RomFileLine,ROM(i));
    end loop;
    return ROM;
  end function;

  signal ~GENSYM[ROM][2] : ~SYM[4](0 to ~LIT[2]-1) := ~SYM[1](~FILE[~LIT[3]]);
  signal ~GENSYM[rd][3] : integer range 0 to ~LIT[2]-1;
begin
  ~SYM[3] <= to_integer(~ARG[4])
  -- pragma translate_off
                mod ~LIT[2]
  -- pragma translate_on
                ;

  ~GENSYM[romFileSync][5] : process (~CLK[1])
  begin
    if (rising_edge(~CLK[1])) then
      ~RESULT <= to_stdlogicvector(~SYM[2](~SYM[3]));
    end if;
  end process;
end block;
-- romFile end"
    }
  }
]