clash-vhdl-0.6.6: primitives/CLaSH.Prelude.BlockRam.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.BlockRam.blockRam#"
    , "type" :
"blockRam# :: KnownNat n       -- ARG[0]
           => SClock clk       -- clk,  ARG[1]
           -> Vec n a          -- init, ARG[2]
           -> Signal' clk Int  -- wr,   ARG[3]
           -> Signal' clk Int  -- rd,   ARG[4]
           -> Signal' clk Bool -- wren, ARG[5]
           -> Signal' clk a    -- din,  ARG[6]
           -> Signal' clk a"
    , "templateD" :
"-- blockRam begin
blockRam_~COMPNAME_~SYM[0] : block
  type RamType is array(natural range <>) of std_logic_vector(~SIZE[~TYPO]-1 downto 0);

  function init_to_bv (arg : in ~TYP[2]) return RamType is
    variable RAM_init : RamType(0 to ~LENGTH[~TYP[2]]-1);
  begin
    for i in RAM_init'range loop
      RAM_init(i) := ~TOBV[arg(i)][6];
    end loop;
    return RAM_init;
  end function;

  signal RAM_~SYM[1]  : RamType (0 to ~LENGTH[~TYP[2]]-1) := init_to_bv(~LIT[2]);
  signal dout_~SYM[2] : std_logic_vector(~SIZE[~TYP[6]]-1 downto 0);
  signal wr_~SYM[3]   : integer range 0 to ~LIT[0] - 1;
  signal rd_~SYM[4]   : integer range 0 to ~LIT[0] - 1;
begin
  wr_~SYM[3] <= to_integer(~ARG[3])
  -- pragma translate_off
                mod ~LIT[0]
  -- pragma translate_on
                ;

  rd_~SYM[4] <= to_integer(~ARG[4])
  -- pragma translate_off
                mod ~LIT[0]
  -- pragma translate_on
                ;

  blockRam_sync : process(~CLK[1])
  begin
    if rising_edge(~CLK[1]) then
      if ~ARG[5] then
        RAM_~SYM[1](wr_~SYM[3]) <= ~TOBV[~ARG[6]][6];
      end if;
      dout_~SYM[2] <= RAM_~SYM[1](rd_~SYM[4]);
    end if;
  end process;

  ~RESULT <= ~FROMBVO[dout_~SYM[2]];
end block;
-- blockRam end"
    }
  }
]