clash-vhdl-0.5: primitives/CLaSH.Prelude.BlockRam.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.BlockRam.blockRam'"
    , "type" :
"blockRam' :: (KnownNat n, KnownNat m) -- (ARG[0],ARG[1])
           => SClock clk               -- clk,  ARG[2]
           -> Vec n a                  -- init, ARG[3]
           -> Signal' clk (Unsigned m) -- wr,   ARG[4]
           -> Signal' clk (Unsigned m) -- rd,   ARG[5]
           -> Signal' clk Bool         -- wren, ARG[6]
           -> Signal' clk a            -- din,  ARG[7]
           -> Signal' clk a"
    , "templateD" :
"blockram_~SYM[0] : block
  signal ~SYM[1] : ~TYP[3] := ~LIT[3]; -- ram
  signal ~SYM[2] : ~TYP[7]; -- inp
  signal ~SYM[3] : ~TYP[7]; -- outp
begin
  ~SYM[2] <= ~ARG[7];

  process(~CLK[2])
  begin
    if rising_edge(~CLK[2]) then
      if ~ARG[6] then
        ~SYM[1](to_integer(~ARG[4])) <= ~SYM[2];
      end if;
      ~SYM[3] <= ~SYM[1](to_integer(~ARG[5]));
    end if;
  end process;

  ~RESULT <= ~SYM[3];
end block;"
    }
  }
]