clash-verilog-0.7: primitives/CLaSH.Prelude.BlockRam.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.BlockRam.blockRam#"
    , "type" :
"blockRam# :: KnownNat n       -- ARG[0]
           => SClock clk       -- clk,  ARG[1]
           -> Vec n a          -- init, ARG[2]
           -> Signal' clk Int  -- rd,   ARG[3]
           -> Signal' clk Bool -- wren, ARG[4]
           -> Signal' clk Int  -- wr,   ARG[5]
           -> Signal' clk a    -- din,  ARG[6]
           -> Signal' clk a"
    , "templateD" :
"// blockRam begin
reg ~TYPO ~GENSYM[RAM][0] [0:~LIT[0]-1];
reg ~TYPO ~GENSYM[dout][1];

reg ~TYP[2] ~GENSYM[ram_init][2];
integer ~GENSYM[i][3];
initial begin
  ~SYM[2] = ~ARG[2];
  for (~SYM[3]=0; ~SYM[3] < ~LIT[0]; ~SYM[3] = ~SYM[3] + 1) begin
    ~SYM[0][~LIT[0]-1-~SYM[3]] = ~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
  end
end

always @(posedge ~CLK[1]) begin : ~GENSYM[~COMPNAME_blockRam][4]
  if (~ARG[4]) begin
    ~SYM[0][~ARG[5]] <= ~ARG[6];
  end
  ~SYM[1] <= ~SYM[0][~ARG[3]];
end

assign ~RESULT = ~SYM[1];
// blockRam end"
    }
  }
]