clash-verilog-0.6.6: primitives/CLaSH.Prelude.ROM.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.ROM.asyncRom#"
    , "type" :
"asyncRom# :: KnownNat n -- ^ ARG[0]
           => Vec n a    -- ^ ARG[1]
           -> Int        -- ^ ARG[2]
           -> a"
    , "templateD" :
"// asyncRom begin
wire ~TYPO ~GENSYM[ROM][0] [0:~LIT[0]-1];

wire ~TYP[1] ~GENSYM[romflat][1];
assign ~SYM[1] = ~ARG[1];
genvar ~GENSYM[i][2];
~GENERATE
for (~SYM[2]=0; ~SYM[2] < ~LIT[0]; ~SYM[2]=~SYM[2]+1) begin : ~GENSYM[mk_array][3]
  assign ~SYM[0][(~LIT[0]-1)-~SYM[2]] = ~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
end
~ENDGENERATE

assign ~RESULT = ~SYM[0][~ARG[2]];
// asyncRom end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Prelude.ROM.rom#"
    , "type" :
"rom# :: KnownNat n      -- ARG[0]
      => SClock clk      -- clk,  ARG[1]
      -> Vec n a         -- init, ARG[2]
      -> Signal' clk Int -- rd,   ARG[3]
      -> Signal' clk a"
    , "templateD" :
"// rom begin
reg ~TYPO ~GENSYM[ROM][0] [0:~LIT[0]-1];
reg ~TYPO ~GENSYM[dout][1];

reg ~TYP[2] ~GENSYM[rom_init][2];
integer ~GENSYM[i][3];
initial begin
  ~SYM[2] = ~ARG[2];
  for (~SYM[3]=0; ~SYM[3] < ~LIT[0]; ~SYM[3] = ~SYM[3] + 1) begin
    ~SYM[0][~LIT[0]-1-~SYM[3]] = ~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
  end
end

always @(posedge ~CLK[1]) begin : ~GENSYM[~COMPNAME_rom][4]
  ~SYM[1] <= ~SYM[0][~ARG[3]];
end

assign ~RESULT = ~SYM[1];
// rom end"
    }
  }
]