clash-verilog-0.5.7: primitives/CLaSH.Sized.Vector.json

[ { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.eq#"
    , "type"      : "eq# :: Eq a => Vec n a -> Vec n a -> Bool"
    , "templateE" : "~ARG[0] == ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.neq#"
    , "type"      : "neq# :: Eq a => Vec n a -> Vec n a -> Bool"
    , "templateE" : "~ARG[0] != ~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.head"
    , "type"      : "head :: Vec (n + 1) a -> a"
    , "templateD" :
"// head begin
wire ~SIGD[~SYM[0]][0];
assign ~SYM[0] = ~ARG[0];

assign ~RESULT = ~SYM[0][~SIZE[~TYP[0]]-1:~SIZE[~TYP[0]]-~SIZE[~TYPO]];
// head end"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.tail"
    , "type"      : "tail :: Vec (n + 1) a -> Vec n a"
    , "templateD" :
"// tail begin
wire ~SIGD[~SYM[0]][0];
assign ~SYM[0] = ~ARG[0];

assign ~RESULT = ~SYM[0][~SIZE[~TYPO]-1 : 0];
// tail end"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.last"
    , "type"      : "Vec (n + 1) a -> a"
    , "templateD" :
"// last begin
wire ~SIGD[~SYM[0]][0];
assign ~SYM[0] = ~ARG[0];

assign ~RESULT = ~SYM[0][~SIZE[~TYPO]-1:0];
// last end"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.init"
    , "type"      : "Vec (n + 1) a -> Vec n a"
    , "templateD" :
"// init begin
wire ~SIGD[~SYM[0]][0];
assign ~SYM[0] = ~ARG[0];

assign ~RESULT = ~SYM[0][~SIZE[~TYP[0]]-1 : ~SIZE[~TYPEL[~TYP[0]]]];
// init end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Sized.Vector.select"
    , "type" :
"select :: (CmpNat (i + s) (s * n) ~ GT) -- ARG[0]
        => SNat f                        -- ARG[1]
        -> SNat s                        -- ARG[2]
        -> SNat n                        -- ARG[3]
        -> Vec i a                       -- ARG[4]
        -> Vec n a"
    , "templateD" :
"// select begin
wire ~SIGD[~SYM[0]][4];
assign ~SYM[0] = ~ARG[4];

wire ~TYPEL[~TYPO] ~SYM[1] [0:~LENGTH[~TYP[4]]-1];
genvar ~SYM[2];
~GENERATE
for (~SYM[2]=0; ~SYM[2] < ~LENGTH[~TYP[4]]; ~SYM[2]=~SYM[2]+1) begin : array_~SYM[3]
  assign ~SYM[1][(~LENGTH[~TYP[4]]-1)-~SYM[2]] = ~SYM[0][~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]];
end
~ENDGENERATE

genvar ~SYM[4];
~GENERATE
for (~SYM[4]=0; ~SYM[4] < ~LIT[3]; ~SYM[4] = ~SYM[4] + 1) begin : select_~SYM[5]
  assign ~RESULT[(~LIT[3]-1-~SYM[4])*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[1][~LIT[1] + (~LIT[2] * ~SYM[4])];
end
~ENDGENERATE
// select end"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.++"
    , "type"      : "(++) :: Vec n a -> Vec m a -> Vec (n + m) a"
    , "templateE" : "{~ARG[0],~ARG[1]}"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.concat"
    , "type"      : "concat :: Vec n (Vec m a) -> Vec (n * m) a"
    , "templateE" : "~ARG[0]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.splitAt"
    , "type"      : "splitAt :: SNat m -> Vec (m + n) a -> (Vec m a, Vec n a)"
    , "templateE" : "~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Sized.Vector.unconcat"
    , "type" :
 "unconcat :: KnownNat n     -- ARG[0]
           => SNat m         -- ARG[1]
           -> Vec (n * m) a  -- ARG[2]
           -> Vec n (Vec m a)"
    , "templateE" : "~ARG[2]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.merge"
    , "type"      : "merge :: Vec n a -> Vec n a -> Vec (n + n) a"
    , "templateD" :
"// merge begin
wire ~SIGD[~SYM[0]][0];
wire ~SIGD[~SYM[1]][1];
assign ~SYM[0] = ~ARG[0];
assign ~SYM[1] = ~ARG[1];

genvar ~SYM[2];
~GENERATE
for (~SYM[2] = 0; ~SYM[2] < ~LENGTH[~TYP[0]]; ~SYM[2] = ~SYM[2] + 1) begin : merge_~SYM[3]
  assign ~RESULT[(2*~SYM[2]+1)*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[0][~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]];
  assign ~RESULT[(2*~SYM[2])*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]]   = ~SYM[1][~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]];
end
~ENDGENERATE
// merge end"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.map"
    , "type"      : "map :: (a -> b) -> Vec n a -> Vec n b"
    , "templateD" :
"// map begin
wire ~SIGD[~SYM[0]][1];
assign ~SYM[0] = ~ARG[1];

genvar ~SYM[1];
~GENERATE
for (~SYM[1]=0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : map_~SYM[2]
  ~INST 0
    ~OUTPUT <= ~RESULT[~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]]~ ~TYPEL[~TYPO]~
    ~INPUT  <= ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]]~ ~TYPEL[~TYP[1]]~
  ~INST
end
~ENDGENERATE
// map end"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.zipWith"
    , "type"      : "zipWith :: (a -> b -> c) -> Vec n a -> Vec n b -> Vec n c"
    , "templateD" :
"// zipWith start
wire ~SIGD[~SYM[0]][1];
wire ~SIGD[~SYM[1]][2];
assign ~SYM[0] = ~ARG[1];
assign ~SYM[1] = ~ARG[2];

genvar ~SYM[2];
~GENERATE
for (~SYM[2] = 0; ~SYM[2] < ~LENGTH[~TYPO]; ~SYM[2] = ~SYM[2] + 1) begin : zipWith_~SYM[2]
  ~INST 0
    ~OUTPUT <= ~RESULT[~SYM[2]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]]~ ~TYPEL[~TYPO]~
    ~INPUT  <= ~SYM[0][~SYM[2]*~SIZE[~TYPEL[~TYP[1]]]+:~SIZE[~TYPEL[~TYP[1]]]]~ ~TYPEL[~TYP[1]]~
    ~INPUT  <= ~SYM[1][~SYM[2]*~SIZE[~TYPEL[~TYP[2]]]+:~SIZE[~TYPEL[~TYP[2]]]]~ ~TYPEL[~TYP[2]]~
  ~INST
end
~ENDGENERATE
// zipWith end"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.index_int"
    , "type"      : "index_integer :: KnownNat n => Vec n a -> Int -> a"
    , "templateD" :
"// indexVec begin
wire ~TYPO vec_~SYM[0] [0:~LIT[0]-1];

wire ~TYP[1] vecflat_~SYM[1];
assign vecflat_~SYM[1] = ~ARG[1];
genvar ~SYM[2];
~GENERATE
for (~SYM[2]=0; ~SYM[2] < ~LIT[0]; ~SYM[2]=~SYM[2]+1) begin : array_~SYM[3]
  assign vec_~SYM[0][(~LIT[0]-1)-~SYM[2]] = vecflat_~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
end
~ENDGENERATE

assign ~RESULT = vec_~SYM[0][~ARG[2]];
// indexVec end"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.replace_int"
    , "type"      : "replace_int :: KnownNat n => Vec n a -> Int -> a -> Vec n a"
    , "templateD" :
"// replaceVec start
wire ~TYP[1] vecflat_~SYM[0];
assign vecflat_~SYM[0] = ~ARG[1];

reg ~TYP[3] vec_~SYM[1] [0:~LIT[0]-1];
integer ~SYM[2];
always @(*) begin
  for (~SYM[2]=0;~SYM[2]<~LIT[0];~SYM[2]=~SYM[2]+1) begin
    vec_~SYM[1][~LIT[0]-1-~SYM[2]] = vecflat_~SYM[0][~SYM[2]*~SIZE[~TYP[3]]+:~SIZE[~TYP[3]]];
  end
  vec_~SYM[1][~ARG[2]] = ~ARG[3];
end

genvar ~SYM[3];
~GENERATE
for (~SYM[3]=0;~SYM[3]<~LIT[0];~SYM[3]=~SYM[3]+1) begin : vec_~SYM[4]
  assign ~RESULT[~SYM[3]*~SIZE[~TYP[3]]+:~SIZE[~TYP[3]]] = vec_~SYM[1][(~LIT[0]-1)-~SYM[3]];
end
~ENDGENERATE
// replaceVec end"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.maxIndex"
    , "type"      : "maxIndex :: KnownNat n => Vec n a -> Integer"
    , "templateE" : "~LIT[0] - 1"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.length"
    , "type"      : "length :: KnownNat n => Vec n a -> Integer"
    , "templateE" : "~LIT[0]"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.replicate"
    , "type"      : "replicate :: SNat n -> a -> Vec n a"
    , "templateE" : "{~LIT[0] {~ARG[1]}}"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.reverse"
    , "type"      : "reverse :: Vec n a -> Vec n a"
    , "templateD" :
"// reverse begin
wire ~SIGD[~SYM[0]][0];
assign ~SYM[0] = ~ARG[0];

genvar ~SYM[1];
~GENERATE
for (~SYM[1] = 0; ~SYM[1] < ~LENGTH[~TYPO]; ~SYM[1] = ~SYM[1] + 1) begin : reverse_~SYM[2]
  assign ~RESULT[(~LENGTH[~TYPO] - 1 - ~SYM[1])*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]] = ~SYM[0][~SYM[1]*~SIZE[~TYPEL[~TYPO]]+:~SIZE[~TYPEL[~TYPO]]];
end
~ENDGENERATE
// reverse end"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Sized.Vector.lazyV"
    , "type"      : "lazyV :: KnownNat n => Vec n a -> Vec n a"
    , "templateE" : "~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Sized.Vector.concatBitVector#"
    , "type" :
"concatBitVector# :: KnownNat m           -- ARG[0]
                  => Vec n (BitVector m)  -- ARG[1]
                  -> BitVector (n * m)"
    , "templateE" : "~ARG[1]"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Sized.Vector.unconcatBitVector#"
    , "type" :
"unconcatBitVector# :: (KnownNat n, KnownNat m) -- (ARG[0],ARG[1])
                    => BitVector (n * m)        -- ARG[2]
                    -> Vec n (BitVector m)"
    , "templateE" : "~ARG[2]"
    }
  }
]