clash-verilog-0.5.6: primitives/CLaSH.Prelude.ROM.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.ROM.asyncRom#"
    , "type" :
"asyncRom# :: KnownNat n -- ^ ARG[0]
           => Vec n a    -- ^ ARG[1]
           -> Int        -- ^ ARG[2]
           -> a"
    , "templateD" :
"// asyncRom begin
wire ~TYPO ROM_~SYM[0] [0:~LIT[0]-1];

wire ~TYP[1] romflat_~SYM[1];
assign romflat_~SYM[1] = ~ARG[1];
genvar ~SYM[2];
for (~SYM[2]=0; ~SYM[2] < ~LIT[0]; ~SYM[2]=~SYM[2]+1) begin : array_~SYM[3]
  assign ROM_~SYM[0][(~LIT[0]-1)-~SYM[2]] = romflat_~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
end

assign ~RESULT = ROM_~SYM[0][~ARG[2]];
// asyncRom end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Prelude.ROM.rom#"
    , "type" :
"rom# :: KnownNat n      -- ARG[0]
      => SClock clk      -- clk,  ARG[1]
      -> Vec n a         -- init, ARG[2]
      -> Signal' clk Int -- rd,   ARG[3]
      -> Signal' clk a"
    , "templateD" :
"// rom begin
reg ~TYPO ROM_~SYM[0] [0:~LIT[0]-1];
reg ~TYPO dout_~SYM[1];

reg ~TYP[2] rom_init_~SYM[2];
integer ~SYM[3];
initial begin
  rom_init_~SYM[2] = ~ARG[2];
  for (~SYM[3]=0; ~SYM[3] < ~LIT[0]; ~SYM[3] = ~SYM[3] + 1) begin
    ROM_~SYM[0][~LIT[0]-1-~SYM[3]] = rom_init_~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
  end
end

always @(posedge ~CLK[1]) begin : blockRam_~COMPNAME_~SYM[4]
  dout_~SYM[1] <= ROM_~SYM[0][~ARG[3]];
end

assign ~RESULT = dout_~SYM[1];
// rom end"
    }
  }
]