clash-verilog-0.5.5: primitives/CLaSH.Prelude.BlockRam.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.BlockRam.blockRam'"
    , "type" :
"blockRam' :: (KnownNat n, KnownNat m) -- (ARG[0],ARG[1])
           => SClock clk               -- clk,  ARG[2]
           -> Vec n a                  -- init, ARG[3]
           -> Signal' clk (Unsigned m) -- wr,   ARG[4]
           -> Signal' clk (Unsigned m) -- rd,   ARG[5]
           -> Signal' clk Bool         -- wren, ARG[6]
           -> Signal' clk a            -- din,  ARG[7]
           -> Signal' clk a"
    , "templateD" :
"// blockRam
reg ~TYPO ~SYM[0] [0:~LIT[0]-1];
reg ~SIGD[~SYM[1]][7];

reg ~TYP[3] ~SYM[2];
integer ~SYM[3];
initial begin
  ~SYM[2] = ~ARG[3];
  for (~SYM[3]=0; ~SYM[3] < ~LIT[0]; ~SYM[3] = ~SYM[3] + 1) begin
    ~SYM[0][~LIT[0]-1-~SYM[3]] = ~SYM[2][~SYM[3]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
  end
end

always @(posedge ~CLK[2]) begin : blockRam_~COMPNAME_~SYM[4]
  if (~ARG[6]) begin
    ~SYM[0][~ARG[4]] <= ~ARG[7];
  end
  ~SYM[1] <= ~SYM[0][~ARG[5]];
end

assign ~RESULT = ~SYM[1];"
    }
  }
]