clash-verilog-0.5.5: primitives/CLaSH.Driver.TestbenchGen.json

[ { "BlackBox" :
    { "name"      : "CLaSH.Driver.TestbenchGen.clockGen"
    , "templateD" :
"// pragma translate_off
reg ~TYPO ~SYM[0];
always begin
  ~SYM[0] = 0;
  #~LIT[0] forever begin
    ~SYM[0] = ~ ~SYM[0];
    #~LIT[1];
    ~SYM[0] = ~ ~SYM[0];
    #~LIT[2];
  end
end
assign ~RESULT = ~SYM[0];
// pragma translate_on"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Driver.TestbenchGen.resetGen"
    , "templateD" :
"// pragma translate_off
reg ~TYPO ~SYM[0];
initial begin
  ~SYM[0] = 0;
  #~LIT[0] ~SYM[0] = 1;
end
assign ~RESULT = ~SYM[0];
// pragma translate_on"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Driver.TestbenchGen.doneGen"
    , "templateD" :
"assign ~RESULT = ~ARG[0];

// pragma translate_off
always @(*) begin
  if (~ARG[0] == 1'b1) begin
    $finish;
  end
end
// pragma translate_on
"
    }
  }
, { "BlackBox" :
    { "name"      : "CLaSH.Driver.TestbenchGen.finishedGen"
    , "templateD" :
"reg ~TYPO ~SYM[0];
always begin
// pragma translate_off
  ~SYM[0] <= 1'b0;
  #~LIT[0]
// pragma translate_on
  ~SYM[0] = 1'b1;
end
assign ~RESULT = ~SYM[0];"
    }
  }
]