clash-systemverilog-0.7: primitives/CLaSH.Prelude.BlockRam.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.BlockRam.blockRam#"
    , "type" :
"blockRam# :: KnownNat n       -- ARG[0]
           => SClock clk       -- clk,  ARG[1]
           -> Vec n a          -- init, ARG[2]
           -> Signal' clk Int  -- rd,   ARG[3]
           -> Signal' clk Bool -- wren, ARG[4]
           -> Signal' clk Int  -- wr,   ARG[5]
           -> Signal' clk a    -- din,  ARG[6]
           -> Signal' clk a"
    , "templateD" :
"// blockRam begin
~SIGD[~GENSYM[RAM][0]][2];
logic [~SIZE[~TYP[6]]-1:0] ~GENSYM[dout][1];
initial begin
  ~SYM[0] = ~LIT[2];
end
always @(posedge ~CLK[1]) begin : ~GENSYM[~COMPNAME_blockRam][2]
  if (~ARG[4]) begin
    ~SYM[0][~ARG[5]] <= ~TOBV[~ARG[6]][~TYP[6]];
  end
  ~SYM[1] <= ~SYM[0][~ARG[3]];
end
assign ~RESULT = ~FROMBV[~SYM[1]][~TYP[6]];
// blockRam end"
    }
  }
]