clash-systemverilog-0.7: primitives/CLaSH.Prelude.BlockRam.File.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.BlockRam.File.blockRamFile#"
    , "type" :
"blockRamFile# :: KnownNat m                 -- ARG[0]
               => SClock clk                 -- clk,  ARG[1]
               -> SNat n                     -- sz,   ARG[2]
               -> FilePath                   -- file, ARG[3]
               -> Signal' clk Int            -- rd,   ARG[4]
               -> Signal' clk Bool           -- wren, ARG[5]
               -> Signal' clk Int            -- wr,   ARG[6]
               -> Signal' clk (BitVector m)  -- din,  ARG[7]
               -> Signal' clk (BitVector m)"
    , "templateD" :
"// blockRamFile begin
~SIGDO[~GENSYM[RAM][0]] [0:~LIT[2]-1];
~SIGD[~GENSYM[dout][1]][7];

initial begin
  $readmemb(~FILE[~LIT[3]],~SYM[0]);
end

always @(posedge ~CLK[1]) begin : ~GENSYM[~COMPNAME_blockRamFile][2]
  if (~ARG[5]) begin
    ~SYM[0][~ARG[6]] <= ~ARG[7];
  end
  ~SYM[1] <= ~SYM[0][~ARG[4]];
end

assign ~RESULT = ~SYM[1];
// blockRamFile end"
    }
  }
]