clash-systemverilog-0.6: primitives/CLaSH.Prelude.ROM.File.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.ROM.File.asyncRomFile#"
    , "type" :
"asyncRomFile :: KnownNat m -- ARG[0]
              => SNat n     -- sz,   ARG[1]
              -> FilePath   -- file, ARG[2]
              -> Int        -- rd,   ARG[3]
              -> BitVector m"
    , "templateD" :
"// asyncRomFile begin
~SIGDO[ROM_~SYM[0]] [0:~LIT[1]-1];

initial begin
  $readmemb(~FILE[~LIT[2]],ROM_~SYM[0]);
end

assign ~RESULT = ROM_~SYM[0][~ARG[3]];
// asyncRomFile end"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Prelude.ROM.File.romFile#"
    , "type" :
"romFile# :: KnownNat m      -- ARG[0]
          => SClock clk      -- clk,  ARG[1]
          -> SNat n          -- sz,   ARG[2]
          -> FilePath        -- file, ARG[3]
          -> Signal' clk Int -- rd,   ARG[4]
          -> Signal' clk (BitVector m)"
    , "templateD" :
"// romFile begin
~SIGDO[ROM_~SYM[0]] [0:~LIT[2]-1];

initial begin
  $readmemb(~FILE[~LIT[3]],ROM_~SYM[0]);
end

~SIGDO[dout_~SYM[1]];
always @(posedge ~CLK[1]) begin : romFile_~COMPNAME_~SYM[2]
  dout_~SYM[1] <= ROM_~SYM[0][~ARG[4]];
end

assign ~RESULT = dout_~SYM[1];
// romFile end"
    }
  }
]