clash-systemverilog-0.5: primitives/CLaSH.Signal.Internal.json

[ { "BlackBox" :
    { "name" : "CLaSH.Signal.Internal.register#"
    , "type" :
"register# :: SClock clk     -- ARG[0]
           -> a              -- ARG[1]
           -> Signal' clk a  -- ARG[2]
           -> Signal' clk a"
    , "templateD" :
"~SIGD[~SYM[0]][2];

always_ff @(posedge ~CLK[0] or negedge ~RST[0])
if (~ ~RST[0]) begin
  ~SYM[0] <= ~ARG[1];
end else begin
  ~SYM[0] <= ~ARG[2];
end

assign ~RESULT = ~SYM[0];"
    }
  }
, { "BlackBox" :
    { "name" : "CLaSH.Signal.Internal.regEn#"
    , "type" :
"regEn# :: SClock clk       -- ARG[0]
        -> a                -- ARG[1]
        -> Signal' clk Bool -- ARG[2]
        -> Signal' clk a    -- ARG[3]
        -> Signal' clk a"
    , "templateD" :
"~SIGD[~SYM[0]][3];

always_ff @(posedge ~CLK[0] or negedge ~RST[0])
if (~ ~RST[0]) begin
  ~SYM[1] <= ~ARG[1];
end else begin
  if (~ARG[2]) begin
    ~SYM[1] <= ~ARG[3];
  end
end

assign ~RESULT = ~SYM[1];"
    }
  }

, { "Primitive" :
    { "name"      : "CLaSH.Signal.Internal.signal#"
    , "primType"  : "Function"
    }
  }
, { "Primitive" :
    { "name"      : "CLaSH.Signal.Internal.mapSignal#"
    , "primType"  : "Function"
    }
  }
, { "Primitive" :
    { "name"      : "CLaSH.Signal.Internal.appSignal#"
    , "primType"  : "Function"
    }
  }
, { "Primitive" :
    { "name"      : "CLaSH.Signal.Internal.foldr#"
    , "primType"  : "Function"
    }
  }
, { "Primitive" :
    { "name"      : "CLaSH.Signal.Internal.traverse#"
    , "primType"  : "Function"
    }
  }
]