clash-systemverilog-0.5.6: primitives/CLaSH.Prelude.Testbench.json

[ { "BlackBox" :
    { "name" : "CLaSH.Prelude.Testbench.assert"
    , "type" :
"assert :: (Eq a,Show a) -- (ARG[0],ARG[1])
        => SClock t      -- ^ ARG[2]
        -> String        -- ^ ARG[3]
        -> Signal' t a   -- ^ Checked value (ARG[4])
        -> Signal' t a   -- ^ Expected value (ARG[5])
        -> Signal' t b   -- ^ Return valued (ARG[6])
        -> Signal' t b"
    , "templateD" :
"// assert begin
// pragma translate_off
always @(posedge ~CLK[2] or posedge ~RST[2]) begin
  if (~ARG[4] != ~ARG[5]) begin
    $display(\"%s, expected: %b, actual: %b\", ~LIT[3], ~TYPM[3]_to_lv(~ARG[5]), ~TYPM[2]_to_lv(~ARG[4]));
    $stop;
  end
end
// pragma translate_on
assign ~RESULT = ~ARG[6];
// assert end"
    }
  }
]