clash-lib-1.6.0: prims/verilog/Clash_Prelude_ROM_Blob.primitives.yaml

- BlackBox:
    name: Clash.Prelude.ROM.Blob.asyncRomBlob#
    kind: Declaration
    type: |-
      asyncRomBlob#
        :: MemBlob n m  -- ARG[0]
        -> Int          -- ARG[1]
        -> BitVector m
    template: |-
      // asyncRomBlob begin
      wire ~TYPO ~GENSYM[ROM][0] [0:~LENGTH[~TYP[0]]-1];

      wire ~TYP[0] ~GENSYM[romflat][1];
      assign ~SYM[1] = ~CONST[0];
      genvar ~GENSYM[i][2];
      ~GENERATE
      for (~SYM[2]=0; ~SYM[2] < ~LENGTH[~TYP[0]]; ~SYM[2]=~SYM[2]+1) begin : ~GENSYM[mk_array][3]
        assign ~SYM[0][(~LENGTH[~TYP[0]]-1)-~SYM[2]] = ~SYM[1][~SYM[2]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
      end
      ~ENDGENERATE

      assign ~RESULT = ~SYM[0][~ARG[1]];
      // asyncRomBlob end