clash-lib-1.6.0: prims/verilog/Clash_Explicit_BlockRam_Blob.primitives.yaml

- BlackBox:
    name: Clash.Explicit.BlockRam.Blob.blockRamBlob#
    kind: Declaration
    outputReg: true
    type: |-
      blockRamBlob#
        :: KnownDomain dom           --       ARG[0]
        => Clock dom                 -- clk,  ARG[1]
        -> Enable dom                -- en,   ARG[2]
        -> MemBlob n m               -- init, ARG[3]
        -> Signal dom Int            -- rd,   ARG[4]
        -> Signal dom Bool           -- wren, ARG[5]
        -> Signal dom Int            -- wr,   ARG[6]
        -> Signal dom (BitVector m)  -- din,  ARG[7]
        -> Signal dom (BitVector m)
    template: |-
      // blockRamBlob begin
      reg ~TYPO ~GENSYM[~RESULT_RAM][1] [0:~LENGTH[~TYP[3]]-1];

      reg ~TYP[3] ~GENSYM[ram_init][3];
      integer ~GENSYM[i][4];
      initial begin
        ~SYM[3] = ~CONST[3];
        for (~SYM[4]=0; ~SYM[4] < ~LENGTH[~TYP[3]]; ~SYM[4] = ~SYM[4] + 1) begin
          ~SYM[1][~LENGTH[~TYP[3]]-1-~SYM[4]] = ~SYM[3][~SYM[4]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
        end
      end
      ~IF ~ISACTIVEENABLE[2] ~THEN
      always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[1]) begin : ~GENSYM[~RESULT_blockRam][5]~IF ~VIVADO ~THEN
        if (~ARG[2]) begin
          if (~ARG[5]) begin
            ~SYM[1][~ARG[6]] <= ~ARG[7];
          end
          ~RESULT <= ~SYM[1][~ARG[4]];
        end~ELSE
        if (~ARG[5] & ~ARG[2]) begin
          ~SYM[1][~ARG[6]] <= ~ARG[7];
        end
        if (~ARG[2]) begin
          ~RESULT <= ~SYM[1][~ARG[4]];
        end~FI
      end~ELSE
      always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[1]) begin : ~SYM[5]
        if (~ARG[5]) begin
          ~SYM[1][~ARG[6]] <= ~ARG[7];
        end
        ~RESULT <= ~SYM[1][~ARG[4]];
      end~FI
      // blockRamBlob end