clash-lib-1.6.0: prims/systemverilog/Clash_Explicit_BlockRam_Blob.primitives.yaml
- BlackBox:
name: Clash.Explicit.BlockRam.Blob.blockRamBlob#
kind: Declaration
type: |-
blockRamBlob#
:: KnownDomain dom -- ARG[0]
=> Clock dom -- clk, ARG[1]
-> Enable dom -- en, ARG[2]
-> MemBlob n m -- init, ARG[3]
-> Signal dom Int -- rd, ARG[4]
-> Signal dom Bool -- wren, ARG[5]
-> Signal dom Int -- wr, ARG[6]
-> Signal dom (BitVector m) -- din, ARG[7]
-> Signal dom (BitVector m)
template: |-
// blockRamBlob begin
~SIGD[~GENSYM[RAM][1]][3];
logic [~SIZE[~TYP[7]]-1:0] ~GENSYM[~RESULT_q][2];
initial begin
~SYM[1] = ~CONST[3];
end~IF ~ISACTIVEENABLE[2] ~THEN
always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[1]) begin : ~GENSYM[~COMPNAME_blockRam][3]~IF ~VIVADO ~THEN
if (~ARG[2]) begin
if (~ARG[5]) begin
~SYM[1][~ARG[6]] <= ~ARG[7];
end
~SYM[2] <= ~SYM[1][~ARG[4]];
end~ELSE
if (~ARG[5] & ~ARG[2]) begin
~SYM[1][~ARG[6]] <= ~ARG[7];
end
if (~ARG[2]) begin
~SYM[2] <= ~SYM[1][~ARG[4]];
end~FI
end~ELSE
always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[1]) begin : ~SYM[3]
if (~ARG[5]) begin
~SYM[1][~ARG[6]] <= ~ARG[7];
end
~SYM[2] <= ~SYM[1][~ARG[4]];
end~FI
assign ~RESULT = ~SYM[2];
// blockRamBlob end