packages feed

clash-lib-1.6.0: prims/commonverilog/Clash_Intel_DDR.primitives.yaml

- BlackBox:
    name: Clash.Intel.DDR.altddioOut#
    kind: Declaration
    libraries:
    - altera_mf
    type: |-
      altddioOut#
        :: ( HasCallStack             -- ARG[0]
           , KnownConfi~ fast domf    -- ARG[1]
           , KnownConfi~ slow doms    -- ARG[2]
           , KnownNat m )             -- ARG[3]
        => SSymbol deviceFamily       -- ARG[4]
        -> Clock slow                 -- ARG[5]
        -> Reset slow                 -- ARG[6]
        -> Enable slow                -- ARG[7]
        -> Signal slow (BitVector m)  -- ARG[8]
        -> Signal slow (BitVector m)  -- ARG[9]
        -> Signal fast (BitVector m)
    template: |-
      // altddioOut begin
      altddio_out
        #(
          .extend_oe_disable ("OFF"),
          .intended_device_family (~LIT[4]),
          .invert_output ("OFF"),
          .lpm_hint ("UNUSED"),
          .lpm_type ("altddio_out"),
          .oe_reg ("UNREGISTERED"),
          .power_up_high ("OFF"),
          .width (~SIZE[~TYPO])
        )
        ~GENSYM[~COMPNAME_ALTDDIO_OUT][7] (~IF ~ISSYNC[2] ~THEN
          .sclr (~ARG[6]),
          .aclr (1'b0),~ELSE
          .aclr (~ARG[6]),
          .sclr (1'b0),~FI
          .datain_h (~ARG[8]),
          .datain_l (~ARG[9]),
          .outclock (~ARG[5]),
          .outclocken (~IF ~ISACTIVEENABLE[7] ~THEN ~ARG[7] ~ELSE 1'b1 ~FI),
          .dataout (~RESULT),
          .aset (1'b0),
          .sset (1'b0),
          .oe (1'b1),
          .oe_out ()
        );
      // altddioOut end