clash-lib-1.2.0: prims/vhdl/Clash_Explicit_BlockRam.json

[ { "BlackBox" :
    { "name" : "Clash.Explicit.BlockRam.blockRam#"
    , "kind" : "Declaration"
    , "type" :
"blockRam#
  :: ( KnownDomain dom        ARG[0]
     , HasCallStack  --       ARG[1]
     , Undefined a ) --       ARG[2]
  => Clock dom       -- clk,  ARG[3]
  -> Enable dom      -- en,   ARG[4]
  -> Vec n a         -- init, ARG[5]
  -> Signal dom Int  -- rd,   ARG[6]
  -> Signal dom Bool -- wren, ARG[7]
  -> Signal dom Int  -- wr,   ARG[8]
  -> Signal dom a    -- din,  ARG[9]
  -> Signal dom a"
    , "template" :
"-- blockRam begin
~GENSYM[~RESULT_blockRam][1] : block
  signal ~GENSYM[~RESULT_RAM][2] : ~TYP[5] := ~CONST[5];
  signal ~GENSYM[rd][4]  : integer range 0 to ~LENGTH[~TYP[5]] - 1;
  signal ~GENSYM[wr][5]  : integer range 0 to ~LENGTH[~TYP[5]] - 1;
begin
  ~SYM[4] <= to_integer(~ARG[6])
  -- pragma translate_off
                mod ~LENGTH[~TYP[5]]
  -- pragma translate_on
                ;

  ~SYM[5] <= to_integer(~ARG[8])
  -- pragma translate_off
                mod ~LENGTH[~TYP[5]]
  -- pragma translate_on
                ;
~IF ~VIVADO ~THEN
  ~SYM[6] : process(~ARG[3])
  begin
    if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[3]) then
      if ~ARG[7] ~IF ~ISACTIVEENABLE[4] ~THEN and ~ARG[4] ~ELSE ~FI then
        ~SYM[2](~SYM[5]) <= ~TOBV[~ARG[9]][~TYP[9]];
      end if;
      ~RESULT <= fromSLV(~SYM[2](~SYM[4]));
    end if;
  end process; ~ELSE
  ~SYM[6] : process(~ARG[3])
  begin
    if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[3]) then
      if ~ARG[7] ~IF ~ISACTIVEENABLE[4] ~THEN and ~ARG[4] ~ELSE ~FI then
        ~SYM[2](~SYM[5]) <= ~ARG[9];
      end if;
      ~RESULT <= ~SYM[2](~SYM[4]);
    end if;
  end process; ~FI
end block;
--end blockRam"
    }
  }
, { "BlackBox" :
    { "name" : "Clash.Explicit.BlockRam.blockRamU#"
    , "kind" : "Declaration"
    , "type" :
"blockRamU#
  :: ( KnownDomain dom        ARG[0]
     , HasCallStack  --       ARG[1]
     , Undefined a ) --       ARG[2]
  => Clock dom       -- clk,  ARG[3]
  -> Enable dom      -- en,   ARG[4]
  -> SNat n          -- len,  ARG[5]
  -> Signal dom Int  -- rd,   ARG[6]
  -> Signal dom Bool -- wren, ARG[7]
  -> Signal dom Int  -- wr,   ARG[8]
  -> Signal dom a    -- din,  ARG[9]
  -> Signal dom a"
    , "template" :
"-- blockRamU begin
~GENSYM[~RESULT_blockRam][1] : block
  type ~GENSYM[ram_t][8] is array (0 to integer'(~LIT[5])-1) of ~TYP[9];
  signal ~GENSYM[~RESULT_RAM][2] : ~SYM[8];
  signal ~GENSYM[rd][4]  : integer range 0 to ~LIT[5] - 1;
  signal ~GENSYM[wr][5]  : integer range 0 to ~LIT[5] - 1;
begin
  ~SYM[4] <= to_integer(~ARG[6])
  -- pragma translate_off
                mod ~LIT[5]
  -- pragma translate_on
                ;

  ~SYM[5] <= to_integer(~ARG[8])
  -- pragma translate_off
                mod ~LIT[5]
  -- pragma translate_on
                ;
~IF ~VIVADO ~THEN
  ~SYM[6] : process(~ARG[3])
  begin
    if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[3]) then
      if ~ARG[7] ~IF ~ISACTIVEENABLE[4] ~THEN and ~ARG[4] ~ELSE ~FI then
        ~SYM[2](~SYM[5]) <= ~TOBV[~ARG[9]][~TYP[9]];
      end if;
      ~RESULT <= fromSLV(~SYM[2](~SYM[4]));
    end if;
  end process; ~ELSE
  ~SYM[6] : process(~ARG[3])
  begin
    if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[3]) then
      if ~ARG[7] ~IF ~ISACTIVEENABLE[4] ~THEN and ~ARG[4] ~ELSE ~FI then
        ~SYM[2](~SYM[5]) <= ~ARG[9];
      end if;
      ~RESULT <= ~SYM[2](~SYM[4]);
    end if;
  end process; ~FI
end block;
--end blockRamU"
    }
  }
, { "BlackBox" :
    { "name" : "Clash.Explicit.BlockRam.blockRam1#"
    , "kind" : "Declaration"
    , "type" :
"blockRam1#
  :: ( KnownDomain dom        ARG[0]
     , HasCallStack  --       ARG[1]
     , Undefined a ) --       ARG[2]
  => Clock dom       -- clk,  ARG[3]
  -> Enable dom      -- en,   ARG[4]
  -> SNat n          -- len,  ARG[5]
  -> a               -- init, ARG[6]
  -> Signal dom Int  -- rd,   ARG[7]
  -> Signal dom Bool -- wren, ARG[8]
  -> Signal dom Int  -- wr,   ARG[9]
  -> Signal dom a    -- din,  ARG[10]
  -> Signal dom a"
    , "template" :
"-- blockRam1 begin
~GENSYM[~RESULT_blockRam][1] : block
  type ~GENSYM[ram_t][8] is array (0 to integer'(~LIT[5])-1) of ~TYP[6];
  signal ~GENSYM[~RESULT_RAM][2] : ~SYM[8] := (others => ~CONST[6]);
  signal ~GENSYM[rd][4]  : integer range 0 to ~LIT[5] - 1;
  signal ~GENSYM[wr][5]  : integer range 0 to ~LIT[5] - 1;
begin
  ~SYM[4] <= to_integer(~ARG[7])
  -- pragma translate_off
                mod ~LIT[5]
  -- pragma translate_on
                ;

  ~SYM[5] <= to_integer(~ARG[9])
  -- pragma translate_off
                mod ~LIT[5]
  -- pragma translate_on
                ;
~IF ~VIVADO ~THEN
  ~SYM[6] : process(~ARG[3])
  begin
    if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[3]) then
      if ~ARG[8] ~IF ~ISACTIVEENABLE[4] ~THEN and ~ARG[4] ~ELSE ~FI then
        ~SYM[2](~SYM[5]) <= ~TOBV[~ARG[10]][~TYP[10]];
      end if;
      ~RESULT <= fromSLV(~SYM[2](~SYM[4]));
    end if;
  end process; ~ELSE
  ~SYM[6] : process(~ARG[3])
  begin
    if ~IF~ACTIVEEDGE[Rising][0]~THENrising_edge~ELSEfalling_edge~FI(~ARG[3]) then
      if ~ARG[8] ~IF ~ISACTIVEENABLE[4] ~THEN and ~ARG[4] ~ELSE ~FI then
        ~SYM[2](~SYM[5]) <= ~ARG[10];
      end if;
      ~RESULT <= ~SYM[2](~SYM[4]);
    end if;
  end process; ~FI
end block;
--end blockRam1"
    }
  }
]