clash-lib-1.2.0: prims/systemverilog/GHC_Classes.json
[ { "BlackBox" :
{ "name" : "GHC.Classes.divInt#"
, "kind" : "Declaration"
, "type" : "divInt# :: Int# -> Int# -> Int#"
, "template" :
"// divInt# begin
logic ~GENSYM[resultPos][1];
logic ~GENSYM[dividerNeg][2];
logic signed [~SIZE[~TYPO]:0] ~GENSYM[dividend2][3];
logic signed [~SIZE[~TYPO]:0] ~GENSYM[dividendE][4];
logic signed [~SIZE[~TYPO]:0] ~GENSYM[dividerE][5];
logic signed [~SIZE[~TYPO]:0] ~GENSYM[quot_res][6];
assign ~SYM[1] = ~VAR[dividend][0][~SIZE[~TYPO]-1] == ~VAR[divider][1][~SIZE[~TYPO]-1];
assign ~SYM[2] = ~VAR[divider][1][~SIZE[~TYPO]-1] == 1'b1;
assign ~SYM[4] = $signed({{~VAR[dividend][0][~SIZE[~TYPO]-1]},~VAR[dividend][0]}); // sign extension
assign ~SYM[5] = $signed({{~VAR[divider][1][~SIZE[~TYPO]-1]} ,~VAR[divider][1]} ); // sign extension
assign ~SYM[3] = ~SYM[1] ? ~SYM[4]
: (~SYM[2] ? (~SYM[4] - ~SYM[5] - ~SIZE[~TYPO]'sd1)
: (~SYM[4] - ~SYM[5] + ~SIZE[~TYPO]'sd1));
assign ~SYM[6] = ~SYM[3] / ~SYM[5];
assign ~RESULT = $signed(~SYM[6][~SIZE[~TYPO]-1:0]);
// divInt# end"
}
}
, { "BlackBox" :
{ "name" : "GHC.Classes.modInt#"
, "kind" : "Declaration"
, "type" : "modInt# :: Int# -> Int# -> Int#"
, "template" :
"// modInt# begin
// remainder
~SIGD[~GENSYM[rem_res][0]][0];
assign ~SYM[0] = ~VAR[dividend][0] % ~VAR[divider][1];
// modulo
assign ~RESULT = (~VAR[dividend][0][~SIZE[~TYPO]-1] == ~VAR[divider][1][~SIZE[~TYPO]-1]) ?
~SYM[0] :
((~SYM[0] == ~SIZE[~TYPO]'sd0) ? ~SIZE[~TYPO]'sd0 : ~SYM[0] + ~VAR[divider][1]);
// modInt# end"
}
}
]