clash-lib-1.2.0: prims/systemverilog/Clash_Signal_Internal.json

[ { "BlackBox" :
    { "name" : "Clash.Signal.Internal.delay#"
    , "kind" : "Declaration"
    , "type" :
"delay#
  :: ( KnownDomain dom        -- ARG[0]
     , Undefined a )          -- ARG[1]
  => Clock dom                -- ARG[2]
  -> Enable dom               -- ARG[3]
  -> a                        -- ARG[4]
  -> Signal clk a             -- ARG[5]
  -> Signal clk a"
    , "resultName" : { "template" : "~CTXNAME" }
    , "resultInit" : { "template" : "~IF~ISINITDEFINED[0]~THEN~CONST[4]~ELSE~FI" }
    , "template" :
"// delay begin~IF ~ISACTIVEENABLE[3] ~THEN
always_ff @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[2]) begin : ~GENSYM[~RESULT_delay][1]
  if (~ARG[3]) begin
    ~RESULT <= ~ARG[5];
  end
end~ELSE
always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[2]) begin : ~SYM[1]
  ~RESULT <= ~ARG[5];
end~FI
// delay end"
    }
  }
, { "BlackBox" :
    { "name" : "Clash.Signal.Internal.register#"
    , "kind" : "Declaration"
    , "type" :
"register#
  :: ( KnownDomain dom        -- ARG[0]
     , Undefined a )          -- ARG[1]
  => Clock dom                -- ARG[2]
  -> Reset dom                -- ARG[3]
  -> Enable dom               -- ARG[4]
  -> a                        -- ARG[5] (powerup value)
  -> a                        -- ARG[6] (reset value)
  -> Signal clk a             -- ARG[7]
  -> Signal clk a"
    , "resultName" : { "template" : "~CTXNAME" }
    , "resultInit" : { "template" : "~IF~ISINITDEFINED[0]~THEN~CONST[5]~ELSE~FI" }
    , "template" :
"// register begin
always_ff @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[2]~IF ~ISSYNC[0] ~THEN ~ELSE or ~IF ~ISACTIVEHIGH[0] ~THEN posedge ~ELSE negedge ~FI ~VAR[rst][3]~FI) begin : ~GENSYM[~RESULT_register][1]
  if (~IF ~ISACTIVEHIGH[0] ~THEN ~ELSE ! ~FI~VAR[rst][3]) begin
    ~RESULT <= ~CONST[6];
  end else ~IF ~ISACTIVEENABLE[4] ~THEN if (~ARG[4]) ~ELSE ~FI begin
    ~RESULT <= ~ARG[7];
  end
end
// register end"
    }
  }
, { "BlackBox" :
    { "name" : "Clash.Signal.Internal.clockGen"
    , "workInfo" : "Always"
    , "kind" : "Declaration"
    , "warning" : "Clash.Signal.Internal.clockGen is not synthesizable!"
    , "type" :
"clockGen
  :: KnownDomain dom     -- ARG[0]
  => Clock dom"
    , "template" :
"// clockGen begin
// pragma translate_off
// 1 = 0.1ps
localparam ~GENSYM[half_period][0] = (~PERIOD[0]0 / 2);
always begin
  ~RESULT = ~IF~ACTIVEEDGE[Rising][0]~THEN 0 ~ELSE 1 ~FI;
  #30000 forever begin
    ~RESULT = ~ ~RESULT;
    #~SYM[0];
    ~RESULT = ~ ~RESULT;
    #~SYM[0];
  end
end
// pragma translate_on
// clockGen end"
    }
  }
, { "BlackBox" :
    { "name" : "Clash.Explicit.Testbench.tbClockGen"
    , "workInfo" : "Always"
    , "kind" : "Declaration"
    , "warning" : "Clash.Signal.Internal.tbClockGen is not synthesizable!"
    , "type" :
"tbClockGen
  :: KnownDomain dom     -- ARG[0]
  => Signal dom Bool      -- ARG[1]
  -> Clock dom"
    , "template" :
"// tbClockGen begin
// pragma translate_off
// 1 = 0.1ps
localparam ~GENSYM[half_period][0] = (~PERIOD[0]0 / 2);
always begin
  ~RESULT = ~IF~ACTIVEEDGE[Rising][0]~THEN 0 ~ELSE 1 ~FI;
  #30000 forever begin
    if (~ ~ARG[1]) begin
      $finish;
    end
    ~RESULT = ~ ~RESULT;
    #~SYM[0];
    ~RESULT = ~ ~RESULT;
    #~SYM[0];
  end
end
// pragma translate_on
// tbClockGen end"
    }
  }
, { "BlackBox" :
    { "name" : "Clash.Signal.Internal.resetGenN"
    , "workInfo" : "Always"
    , "kind" : "Declaration"
    , "type" : "resetGenN :: (KnownDomain dom, 1 <= n) => SNat n -> Reset dom"
    , "template" :
"// resetGen begin
// pragma translate_off
~IF~ISSYNC[0]~THEN
localparam ~GENSYM[reset_period][1] = 29998 + (~LIT[2] * ~PERIOD[0]0);
initial begin
  #1 ~RESULT = ~IF ~ISACTIVEHIGH[0] ~THEN 1 ~ELSE 0 ~FI;
  #~SYM[1] ~RESULT = ~IF ~ISACTIVEHIGH[0] ~THEN 0 ~ELSE 1 ~FI;
end~ELSE
localparam ~SYM[1] = 30001 + ((~LIT[2] - 1) * ~PERIOD[0]0);
initial begin
  #1     ~RESULT = ~IF ~ISACTIVEHIGH[0] ~THEN 1 ~ELSE 0 ~FI;
  #~SYM[1] ~RESULT = ~IF ~ISACTIVEHIGH[0] ~THEN 0 ~ELSE 1 ~FI;
end
~FI
// pragma translate_on
// resetGen end"
    }
  }
]