clash-lib-1.10.0: prims/verilog/Clash_Explicit_ROM.primitives.yaml

- BlackBox:
    name: Clash.Explicit.ROM.rom#
    kind: Declaration
    outputUsage: NonBlocking
    type: |-
      rom# :: ( KnownDomain dom        ARG[0]
               , KnownNat n    --       ARG[1]
               , NFDataX a )   --       ARG[2]
            => Clock dom       -- clk,  ARG[3]
            -> Enable dom      -- en,   ARG[4]
            -> Vec n a         -- init, ARG[5]
            -> Signal dom Int  -- rd,   ARG[6]
            -> Signal dom a
    template: |-
      // rom begin
      reg ~TYPO ~GENSYM[ROM][1] [0:~LIT[1]-1];

      reg ~TYP[5] ~GENSYM[rom_init][3];
      integer ~GENSYM[i][4];
      initial begin
        ~SYM[3] = ~LIT[5];
        for (~SYM[4]=0; ~SYM[4] < ~LIT[1]; ~SYM[4] = ~SYM[4] + 1) begin
          ~SYM[1][~LIT[1]-1-~SYM[4]] = ~SYM[3][~SYM[4]*~SIZE[~TYPO]+:~SIZE[~TYPO]];
        end
      end
      ~IF ~ISACTIVEENABLE[4] ~THEN
      always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin : ~GENSYM[~COMPNAME_rom][5]
        if (~ARG[4]) begin
          ~RESULT <= ~SYM[1][~ARG[6]];
        end
      end~ELSE
      always @(~IF~ACTIVEEDGE[Rising][0]~THENposedge~ELSEnegedge~FI ~ARG[3]) begin : ~SYM[5]
        ~RESULT <= ~SYM[1][~ARG[6]];
      end~FI
      // rom end