clash-lib-1.10.0: prims/verilog/Clash_Explicit_DDR.primitives.yaml

- BlackBox:
    name: Clash.Explicit.DDR.ddrIn#
    kind: Declaration
    type: |-
      ddrIn# :: forall a dom domDDR
              . HasCallStack             -- ARG[0]
             => NFDataX a                -- ARG[1]
             => KnownDomain dom          -- ARG[2]
             => KnownDomain domDDR       -- ARG[3]
             => DomPeriod ~ 2 * ...      -- ARG[4]
             => Clock dom                -- ARG[5]
             -> Reset dom                -- ARG[6]
             -> Enable dom               -- ARG[7]
             -> a                        -- ARG[8]
             -> a                        -- ARG[9]
             -> a                        -- ARG[10]
             -> Signal domDDR a          -- ARG[11]
             -> Signal dom (a,a)
    template: |-
      // ddrIn begin
      reg ~SIGD[~GENSYM[data_Pos][1]][11];
      reg ~SIGD[~GENSYM[data_Neg][2]][11];
      reg ~SIGD[~GENSYM[data_Neg_Latch][3]][11];
      always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[5]~IF~ISSYNC[2]~THEN)~ELSE or ~IF~ISACTIVEHIGH[2]~THENposedge~ELSEnegedge~FI ~ARG[6])~FI begin : ~GENSYM[~COMPNAME_ddrIn_pos][6]
        if (~IF~ISACTIVEHIGH[2]~THEN~ARG[6]~ELSE! ~ARG[6]~FI) begin
          ~SYM[1] <= ~ARG[9];
        end else ~IF ~ISACTIVEENABLE[7] ~THEN if (~ARG[7]) ~ELSE ~FI begin
          ~SYM[1] <= ~ARG[11];
        end
      end
      always @(~IF~ACTIVEEDGE[Rising][2]~THENnegedge~ELSEposedge~FI ~ARG[5]~IF~ISSYNC[2]~THEN)~ELSE or ~IF~ISACTIVEHIGH[2]~THENposedge~ELSEnegedge~FI ~ARG[6])~FI begin : ~GENSYM[~COMPNAME_ddrIn_neg][7]
        if (~IF~ISACTIVEHIGH[2]~THEN~ARG[6]~ELSE! ~ARG[6]~FI) begin
          ~SYM[2] <= ~ARG[10];
        end else ~IF ~ISACTIVEENABLE[7] ~THEN if (~ARG[7]) ~ELSE ~FI begin
          ~SYM[2] <= ~ARG[11];
        end
      end
      always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[5]~IF~ISSYNC[2]~THEN)~ELSE or ~IF~ISACTIVEHIGH[2]~THENposedge~ELSEnegedge~FI ~ARG[6])~FI begin : ~GENSYM[~COMPNAME_ddrIn_neg_latch][8]
        if (~IF~ISACTIVEHIGH[2]~THEN~ARG[6]~ELSE! ~ARG[6]~FI) begin
          ~SYM[3] <= ~ARG[8];
        end else ~IF ~ISACTIVEENABLE[7] ~THEN if (~ARG[7]) ~ELSE ~FI begin
          ~SYM[3] <= ~SYM[2];
        end
      end

      assign ~RESULT = {~SYM[3], ~SYM[1]};
      // ddrIn end
- BlackBox:
    name: Clash.Explicit.DDR.ddrOut#
    kind: Declaration
    type: |-
      ddrOut# :: forall a dom domDDR
               . HasCallStack                 -- ARG[0]
              => NFDataX a                    -- ARG[1]
              => KnownDomain dom              -- ARG[2]
              => KnownDomain domDDR           -- ARG[3]
              => DomPeriod ~ 2 * ...          -- ARG[4]
              => Clock dom                    -- ARG[5]
              -> Reset dom                    -- ARG[6]
              -> Enable dom                   -- ARG[7]
              -> a                            -- ARG[8]
              -> Signal dom a                 -- ARG[9]
              -> Signal dom a                 -- ARG[10]
              -> Signal domDDR a
    template: |-
      // ddrOut begin
      reg ~SIGD[~GENSYM[data_Pos][1]][8];
      reg ~SIGD[~GENSYM[data_Neg][2]][8];
      ~IF ~VIVADO ~THENreg ~SIGDO[~GENSYM[ddrOut][3]];~ELSE~FI
      always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[5]~IF~ISSYNC[2]~THEN)~ELSE or ~IF~ISACTIVEHIGH[2]~THENposedge~ELSEnegedge~FI ~ARG[6])~FI begin : ~GENSYM[~COMPNAME_ddrOut_pos][5]
        if (~IF~ISACTIVEHIGH[2]~THEN~ARG[6]~ELSE! ~ARG[6]~FI) begin
          ~SYM[1] <= ~ARG[8];
        end else ~IF ~ISACTIVEENABLE[7] ~THEN if (~ARG[7]) ~ELSE ~FI begin
          ~SYM[1] <= ~ARG[9];
        end
      end
      always @(~IF~ACTIVEEDGE[Rising][2]~THENposedge~ELSEnegedge~FI ~ARG[5]~IF~ISSYNC[2]~THEN)~ELSE or ~IF~ISACTIVEHIGH[2]~THENposedge~ELSEnegedge~FI ~ARG[6])~FI begin : ~GENSYM[~COMPNAME_ddrOut_neg][6]
        if (~IF~ISACTIVEHIGH[2]~THEN~ARG[6]~ELSE! ~ARG[6]~FI) begin
          ~SYM[2] <= ~ARG[8];
        end else ~IF ~ISACTIVEENABLE[7] ~THEN if (~ARG[7]) ~ELSE ~FI begin
          ~SYM[2] <= ~ARG[10];
        end
      end

      ~IF ~VIVADO ~THENalways @(*) begin
        if (~ARG[5]) begin
          ~SYM[3] = ~IF~ACTIVEEDGE[Rising][2]~THEN~SYM[1]~ELSE~SYM[2]~FI;
        end else begin
          ~SYM[3] = ~IF~ACTIVEEDGE[Rising][2]~THEN~SYM[2]~ELSE~SYM[1]~FI;
        end
      end
      assign ~RESULT = ~SYM[3];~ELSE
      assign ~RESULT = ~ARG[5] ? ~IF~ACTIVEEDGE[Rising][2]~THEN~SYM[1] : ~SYM[2]~ELSE~SYM[2] : ~SYM[1]~FI;~FI

      // ddrOut end