clash-lib-1.10.0: prims/systemverilog/Clash_Intel_DDR.primitives.yaml

- BlackBox:
    name: Clash.Intel.DDR.altddioIn#
    kind: Declaration
    libraries:
    - altera_mf
    type: |-
      altddioIn#
        :: forall deviceFamily n dom domDDR
         . HasCallStack                 -- ARG[0]
        => KnownDomain dom              -- ARG[1]
        => KnownDomain domDDR           -- ARG[2]
        => DomPeriod ~ 2 * ...          -- ARG[3]
        => DomEdge ~ Rising             -- ARG[4]
        => KnownNat n                   -- ARG[5]
        => SSymbol deviceFamily         -- ARG[6]
        -> Clock dom                    -- ARG[7]
        -> Reset dom                    -- ARG[8]
        -> Enable dom                   -- ARG[9]
        -> Signal domDDR (BitVector n)  -- ARG[10]
        -> Signal dom (BitVector n, BitVector n)
    template: |-
      // altddioIn begin
      ~SIGD[~GENSYM[dataout_l][1]][10];
      ~SIGD[~GENSYM[dataout_h][2]][10];

      altddio_in
        #(
          .intended_device_family (~LIT[6]),
          .invert_input_clocks ("OFF"),
          .lpm_hint ("UNUSED"),
          .lpm_type ("altddio_in"),
          .power_up_high ("OFF"),
          .width (~SIZE[~TYP[10]])
        )
        ~GENSYM[~COMPNAME_ALTDDIO_IN][7] (~IF ~ISSYNC[1] ~THEN
          .sclr (~ARG[8]),
          .aclr (1'b0),~ELSE
          .aclr (~ARG[8]),
          .sclr (1'b0),~FI
          .datain (~ARG[10]),
          .inclock (~ARG[7]),
          .inclocken (~IF ~ISACTIVEENABLE[9] ~THEN~ARG[9]~ELSE1'b1~FI),
          .dataout_h (~SYM[2]),
          .dataout_l (~SYM[1]),
          .aset (1'b0),
          .sset (1'b0)
        );
      assign ~RESULT = {~SYM[1],~SYM[2]};
      // altddioIn end