clash-lib-1.0.0: prims/vhdl/Clash_Explicit_DDR.json

[ { "BlackBox" :
    { "name" : "Clash.Explicit.DDR.ddrIn#"
    , "kind" : "Declaration"
    , "type" :
"ddrIn# :: forall a slow fast n pFast enabled synchronous.
           ( HasCallStack           -- ARG[0]
           , Undefined a            -- ARG[1]
           , KnownConfi~ fast domf  -- ARG[2]
           , KnownConfi~ slow doms  -- ARG[3]
        => Clock slow               -- ARG[4]
        -> Reset slow               -- ARG[5]
        -> Enable slow              -- ARG[6]
        -> a                        -- ARG[7]
        -> a                        -- ARG[8]
        -> a                        -- ARG[9]
        -> Signal fast a            -- ARG[10]
        -> Signal slow (a,a)"
    , "template" :
"-- ddrIn begin
~GENSYM[~COMPNAME_ddrIn][0] : block
  signal ~GENSYM[data_Pos][1]       : ~TYP[9];
  signal ~GENSYM[data_Neg][2]       : ~TYP[9];
  signal ~GENSYM[data_Neg_Latch][3] : ~TYP[9];
begin
 ~IF ~ISSYNC[3] ~THEN
  -- sync
  -------------
  ~GENSYM[~COMPNAME_ddrIn_pos][6] : process(~ARG[4])
  begin
    if ~IF~ACTIVEEDGE[Rising][2]~THENrising_edge~ELSEfalling_edge~FI(~ARG[4]) then
      if ~ARG[5] = ~IF~ISACTIVEHIGH[2]~THEN'1'~ELSE'0'~FI then
        ~SYM[1] <= ~ARG[8];
      els~IF ~ISACTIVEENABLE[6] ~THENif ~ARG[6] then~ELSEe~FI
        ~SYM[1] <= ~ARG[10];
      end if;
    end if;
  end process;

  ~GENSYM[~COMPNAME_ddrIn_neg][7] : process(~ARG[4])
  begin
    if ~IF~ACTIVEEDGE[Rising][2]~THENfalling_edge~ELSErising_edge~FI(~ARG[4]) then
      if ~ARG[5] = ~IF~ISACTIVEHIGH[2]~THEN'1'~ELSE'0'~FI then
        ~SYM[2] <= ~ARG[9];
      els~IF ~ISACTIVEENABLE[6] ~THENif ~ARG[6] then~ELSEe~FI
        ~SYM[2] <= ~ARG[10];
      end if;
    end if;
  end process;

  ~GENSYM[~COMPNAME_ddrIn_neg_latch][8] : process(~ARG[4])
  begin
    if ~IF~ACTIVEEDGE[Rising][2]~THENrising_edge~ELSEfalling_edge~FI(~ARG[4]) then
      if ~ARG[5] = ~IF~ISACTIVEHIGH[2]~THEN'1'~ELSE'0'~FI then
        ~SYM[3] <= ~ARG[7];
      els~IF ~ISACTIVEENABLE[6] ~THENif ~ARG[6] then~ELSEe~FI
        ~SYM[3] <= ~SYM[2];
      end if;
    end if;
  end process;
 ~ELSE
  -- async
  --------------
  ~SYM[6] : process(~ARG[4],~ARG[5]~VARS[9])
  begin
    if ~ARG[5] = ~IF~ISACTIVEHIGH[2]~THEN'1'~ELSE'0'~FI then
      ~SYM[1] <= ~ARG[8];
    elsif ~IF ~ISACTIVEENABLE[6] ~THEN ~ARG[6] and ~ELSE ~FI ~IF~ACTIVEEDGE[Rising][2]~THENrising_edge~ELSEfalling_edge~FI(~ARG[4]) then
      ~SYM[1] <= ~ARG[10];
    end if;
  end process;

  ~SYM[7] : process(~ARG[4],~ARG[5]~VARS[9])
  begin
    if ~ARG[5] = ~IF~ISACTIVEHIGH[2]~THEN'1'~ELSE'0'~FI then
      ~SYM[2] <= ~ARG[9];
    elsif ~IF ~ISACTIVEENABLE[6] ~THEN ~ARG[6] and ~ELSE ~FI ~IF~ACTIVEEDGE[Rising][2]~THENfalling_edge~ELSErising_edge~FI(~ARG[4]) then
      ~SYM[2] <= ~ARG[10];
    end if;
  end process;

  ~SYM[8] : process(~ARG[4],~ARG[5],~SYM[2])
  begin
    if ~ARG[5] = ~IF~ISACTIVEHIGH[2]~THEN'1'~ELSE'0'~FI then
      ~SYM[3] <= ~ARG[7];
    elsif ~IF ~ISACTIVEENABLE[6] ~THEN ~ARG[6] and ~ELSE ~FI ~IF~ACTIVEEDGE[Rising][2]~THENrising_edge~ELSEfalling_edge~FI(~ARG[4]) then
      ~SYM[3] <= ~SYM[2];
    end if;
  end process;
 ~FI
  ~RESULT <= (~SYM[3], ~SYM[1]);
end block;
-- ddrIn end"
    }
  }
, { "BlackBox" :
    { "name" : "Clash.Explicit.DDR.ddrOut#"
    , "kind" : "Declaration"
    , "type" :
"ddrOut# :: ( HasCallStack               -- ARG[0]
            , Undefined a                -- ARG[1]
            , KnownConfi~ fast domf      -- ARG[2]
            , KnownConfi~ slow doms      -- ARG[3]
         => Clock slow                   -- ARG[4]
         -> Reset slow                   -- ARG[5]
         -> Enable slow                  -- ARG[6]
         -> a                            -- ARG[7]
         -> Signal slow a                -- ARG[8]
         -> Signal slow a                -- ARG[9]
         -> Signal fast a"
    , "template" :
"-- ddrOut begin
~GENSYM[~COMPNAME_ddrIn][0] : block
  signal ~GENSYM[data_Pos][1] : ~TYP[7];
  signal ~GENSYM[data_Neg][2] : ~TYP[7];
begin
 ~IF ~ISSYNC[3] ~THEN
  -- sync
  -------------
  ~GENSYM[~COMPNAME_ddrOut_pos][5] : process(~ARG[4])
  begin
    if ~IF~ACTIVEEDGE[Rising][2]~THENrising_edge~ELSEfalling_edge~FI(~ARG[4]) then
      if ~ARG[5] = ~IF~ISACTIVEHIGH[2]~THEN'1'~ELSE'0'~FI then
        ~SYM[1] <= ~ARG[7];
      els~IF ~ISACTIVEENABLE[6] ~THENif ~ARG[6] then~ELSEe~FI
        ~SYM[1] <= ~ARG[8];
      end if;
    end if;
  end process;

  ~GENSYM[~COMPNAME_ddrOut_neg][6] : process(~ARG[4])
  begin
    if ~IF~ACTIVEEDGE[Rising][2]~THENrising_edge~ELSEfalling_edge~FI(~ARG[4]) then
      if ~ARG[5] = ~IF~ISACTIVEHIGH[2]~THEN'1'~ELSE'0'~FI then
        ~SYM[2] <= ~ARG[7];
      els~IF ~ISACTIVEENABLE[6] ~THENif ~ARG[6] then~ELSEe~FI
        ~SYM[2] <= ~ARG[9];
      end if;
    end if;
  end process;
 ~ELSE
  -- async
  --------------
  ~SYM[5] : process(~ARG[4],~ARG[5]~VARS[8])
  begin
    if ~ARG[5] = ~IF~ISACTIVEHIGH[2]~THEN'1'~ELSE'0'~FI then
      ~SYM[1] <= ~ARG[7];
    elsif ~IF~ACTIVEEDGE[Rising][2]~THENrising_edge~ELSEfalling_edge~FI(~ARG[4]) then
      ~SYM[1] <= ~ARG[8];
    end if;
  end process;

  ~SYM[6] : process(~ARG[4],~ARG[5]~VARS[9])
  begin
    if ~ARG[5] = ~IF~ISACTIVEHIGH[2]~THEN'1'~ELSE'0'~FI then
      ~SYM[2] <= ~ARG[7];
    elsif ~IF~ACTIVEEDGE[Rising][2]~THENrising_edge~ELSEfalling_edge~FI(~ARG[4]) then
      ~SYM[2] <= ~ARG[9];
    end if;
  end process;
 ~FI
  ~RESULT <= ~IF~ACTIVEEDGE[Rising][2]~THEN~SYM[1]~ELSE~SYM[2]~FI when (~ARG[4] = '1' ~IF ~ISACTIVEENABLE[6] ~THEN and ~ARG[6] ~ELSE ~FI) else ~IF~ACTIVEEDGE[Rising][2]~THEN~SYM[2]~ELSE~SYM[1]~FI;
end block;
-- ddrOut end"
    }
  }
]